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2019 Spring Soln

The document is an exam paper for the course CSE345 & CSE347 on Real Time - Embedded System Design, dated June 19th, 2019. It consists of 6 questions covering topics such as I2C communication, RTOS task state machines, FreeRTOS interrupt handling, deadlock scenarios, FIFO buffers, and debugging breakpoints. The total marks for the exam are 40, and it is designed to be completed in 3 hours.

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0% found this document useful (0 votes)
3 views

2019 Spring Soln

The document is an exam paper for the course CSE345 & CSE347 on Real Time - Embedded System Design, dated June 19th, 2019. It consists of 6 questions covering topics such as I2C communication, RTOS task state machines, FreeRTOS interrupt handling, deadlock scenarios, FIFO buffers, and debugging breakpoints. The total marks for the exam are 40, and it is designed to be completed in 3 hours.

Uploaded by

zainbmaged114
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

June 19th.

, 2019 Course Code: CSE345 & CSE347 Time: 3 Hours


Real Time - Embedded System Design
The Exam Consists of 6 Questions in 4 Pages Total Marks: 40 Marks
‫هذه ورقة إجابة أيضا – على كل طالب تدبيسها من الناحية اليسرى يف الغالف الرمسي املعد لذلك – وكتابة بياانت الطالب عليه‬ 1/4
Question (1): (7 Marks)
In the figure below, there are two masters communicating on an I2C bus. Complete the SDA line bits
switching.

Question (2): (7 Marks)


The figure below shows a subset of RTOS task state machine. On “Cut” arrows, give all conditions of
transitions from one state to another.

Time Slice / task Scheduled to run

Time Slice Finished

Event Occured Waiting for Event

Sherif Hammad P.T.O


June 19th., 2019 Course Code: CSE345 & CSE347 Time: 3 Hours
Real Time - Embedded System Design
The Exam Consists of 6 Questions in 4 Pages Total Marks: 40 2/4

Question (3): (7 Marks)


The following figure is the timing diagram of a FreeRTOS application. Write the C-code that could
achieve this interrupt handling. Assume any missing data if any.

Sherif Hammad P.T.O


June 19th., 2019 Course Code: CSE345 & CSE347 Time: 3 Hours
Real Time - Embedded System Design
The Exam Consists of 6 Questions in 4 Pages Total Marks: 40 3/4

Question (4): (7 Marks) (Assume Missing Data if Any)


Write the code to reproduce the following “Dead Lock” scenario where Task A and Task B both need
to acquire mutex X and mutex Y in order to perform an action:
1. Task A executes and successfully takes mutex X.
2. Task A is pre-empted by Task B.
3. Task B successfully takes mutex Y before attempting to also take mutex X
4. If Task A continues executing, it will attempt to take mutex Y

Sherif Hammad P.T.O


June 19th., 2019 Course Code: CSE345 & CSE347 Time: 3 Hours
Real Time - Embedded System Design
The Exam Consists of 6 Questions in 4 Pages Total Marks: 40 4/4

Question (5): (5 Marks)


Complete the following:
END of the
FIFO buffers where data is written to --------------
a) Normally, queues are used as ---------------
FRONT of the queue.
queue and removed from ------------------
BLOCKED
b) A task, that is blocked on queue read, will be moved automatically from the ----------------------
READY
to the -------------------------- if the BLOCK TIME EXPIRED before data becomes
-----------------------------------------
available.

c) If the queue-blocked tasks have equal priority, and the chance comes, then the task that
HAS BEEN WAITING THE LONGEST will be unblocked.
------------------------------

d) During “queue write”, the block time is the maximum time the task should be held in the
BLOCKED SPACE TO BECOME AVAILABLE on the queue, should the queue already
------ state to wait for ---------------------------------------
FULL
be ----------.

Question (6): (7 Marks)


The figure below is a snap shot from a debugging session. In the following table, document your
expectation of the hitting-order of Breakpoints (designated by line numbers; 75, 86 and 87), and the
content of designated heap.

Hit Order Break Point No. Content of Designated Heap


1
2
3
4
5
6
7
End of Questions

Sherif Hammad P.T.O

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