4 - Processor Fundamentals

As learned previously in hardware, a computer needs a certain devices to take

data as input and the output that data. In this chapter we will look at how the
computer processes that data.

Von neuman architecture

This simple model shows the inner workings of a central processing unit (CPU). It
can access IAS (RAM) directly which is crucial in decoding the instruction. Before
we understand how it works, we need to be familiar with a few terms.

Components of a CPU
Inside a CPU, 3 things are needed. Somewhere to store data (registers), Someone
to direct orders (CU), Something to perform calculations (Arithmetic logical unit).

Registers
Registers are temporary memory storages used to store bits of information
needed to decode the instruction. Remember, the smaller the size of a storage,

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 the faster its access speed. Registers benefit from this as they a size of only
around 64 to 128 bits. This comes in handy as the ALU might need an address,
data or instruction to execute the program.

Hold the address of the next instruction to

Program Counter (PC)
be fetched

Holds the address of the memory location

Memory Address Register (MAR)
currently being read

Stores the data which has been read from

Memory Data Register (MDR \ MBR)
memory or is about to be written to memory

Stores the current instruction being

Current Instruction Register (CIR)
executed

Stores intermediate results of arithmetic and

Accumulator (ACC)
logical operations.

Used to store and modify memory

Index Register (IX) addresses during the execution of a
program

Contains bits which can be set or cleared

depending on the operation. It has 4 flags,
Status Register (SR)
Zero (Z), Negative (N), Overflow (V), Carry
(C)

There are two types of registers, general purpose and special purpose. As the
name suggests, Special purpose registers are used for a specific purpose. Like
MDR can only be used to store the data, etc. General purpose registers holds data
that is in frequent use and is not limited to just one task. An accumulator is a good
example of a general purpose register which stores data that needs to be
calculated on and the result of those calculations.

Buses Factors affecting CPU

There are 3 types of buses, they transmit performance
data between the RAM and CPU. Width of the bus, more width
would equal more data to be
Address Bus transmitted. We call a group
of bits which can be regarded

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 A unidirectional bus which is used in as a single unit as a “word”.
transferring addresses. Increasing the bus width
would increase the rate of
Control Bus transfer of words
A bidirectional bus which is used in Overclocking, which can be
transferring control signals from the Control done via the BIOS. It will
Unit to all the other components of the CPU speed up the CPU but can
cause serious
Data Bus unsynchronization or
A bidirectional bus which is used in overheating.
transferring data to and from components.
Increasing the number of
cores

Use of cache memory

Control Unit
The Control Unit (CU) acts like the computer’s neurons. It makes decisions and
communicates with other components using control signals sent via the control
bus. CU ensures that different operations of the CPU dont crash into one another.
A system clock is used to produce timing signals, controlled by the clock speed,
and ensures that everything is in sync

Synchronises actions

Sends control signals

Manages order of execution of instructions

Immediate Access Store (IAS)

IAS or RAM, as detailed in unit 3, is a memory device that stores the contents of
an instruction at a specified address.

Fetch Decode Execute cycle

First, address of the instruction is copied from the PC to the MAR using address
bus. The contents present at that address are then copied into the MDR from

4 - Processor Fundamentals 3
 where it makes its way to the CIR. The data is broken down into opcode and
operand, where the instruction execution requires data from another address.
Contents of that address are then copied into the MDR, from where it is sent to the
accumulator. ALU performs the task and PC increments by 1. Note that this
incrimination means that now the PC has the address of the next instruction.

Register Transfer Notation

Using this, we can generate a RTN; we know that the sequence goes something
like this:

1. PC copies the address into MAR

2. MAR goes to RAM and copies the contents of that address into MDR

3. MDR copies its contents into the CIR

4. Program Counter increments by 1.

Now lets generate a RTN. Note that in this notation [location] refers to the content
of that location, and [[location]] considers the contents of the location as an
address and goes to RAM to fetch data present at that address.

1. PC ← [PC] + 1

2. MAR ← [PC]

3. MDR ← [[MAR]]

4. CIR ← [MDR]

Cache
Cache is a fast access memory location where it stores frequently stored
instructions. It is situated in between the RAM and the CPU (sometimes within the
cpu). It speeds up the overall performance of a CPU

Interrupts

https://www.youtube.com/watch?v=aUhLQnr-y0Q&t=4s

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