UG0726

User Guide
PolarFire FPGA Board Design
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50200726. 10.0 7/21

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 10.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.5 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.6 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.7 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.8 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.9 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.10 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 PolarFire FPGA Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Designing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 PolarFire Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.2 Power-Supply Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3 Unused Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.4 Pin Assignment Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 I/O Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Cold Sparing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Hot Socketing (GPIO Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7 DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8 Device Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8.1 JTAG Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8.2 SPI Master Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8.3 SPI Slave Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.8.4 Special Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.9.1 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.10 MIPI Hardware Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.10.1 MIPI RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.10.2 MIPI TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.11 AC and DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.12 Brownout Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3 Board Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Layout Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 Appendix: General Layout Design Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 MIPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Microsemi Proprietary UG0726 User Guide Revision 10.0 iii

4.2.2 DC Blocking Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Microsemi Proprietary UG0726 User Guide Revision 10.0 iv

Figures

Figure 1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2 Example Power-Supply Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3 Option 1 for unused Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4 Option 2 for Unused Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5 Cold Sparing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 JTAG Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7 SPI Master Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8 SPI Slave Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9 MIPI RX Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10 MIPI TX Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11 MIPI TX Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12 Skew Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13 Example of Asymmetric and Symmetric Differential Pairs Structure . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14 Ground Planes for Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15 Via Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16 Non-Functional Pads of Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17 Via-to-Via Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18 GND Via or Return Via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19 Capacitor Pad Reference Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Microsemi Proprietary UG0726 User Guide Revision 10.0 v

Tables

Table 1 Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2 Power-Supply Decoupling Capacitors—MPF300T - FCG1152/FCG784 (1mm) . . . . . . . . . . . . . . . 5
Table 3 Power-Supply Decoupling Capacitors—MPF300T - FCG1152/FCG784/FCG484 (1 mm) . . . . . . . . 6
Table 4 Power-Supply Decoupling Capacitors—MPF300T - FCVG484 (0.8mm) . . . . . . . . . . . . . . . . . . . . . 6
Table 5 Power-Supply Decoupling Capacitors—MPF300T - FCSG536 (0.5mm) . . . . . . . . . . . . . . . . . . . . . 7
Table 6 Power-Supply Decoupling Capacitors—MPF200T - FCVG484 (0.8 mm) . . . . . . . . . . . . . . . . . . . . 8
Table 7 Power-Supply Decoupling Capacitors—MPF200T - FCG784/FCG484 (1mm) . . . . . . . . . . . . . . . . 8
Table 8 Power-Supply Decoupling Capacitors—MPF200T - FCSG536 (0.5 mm) . . . . . . . . . . . . . . . . . . . . 9
Table 9 Power-Supply Decoupling Capacitors—MPF200T - FCSG325 (0.5 mm) . . . . . . . . . . . . . . . . . . . 10
Table 10 Power-Supply Decoupling Capacitors—MPF100T - FCSG325 (0.5 mm) . . . . . . . . . . . . . . . . . . . 10
Table 11 Power-Supply Decoupling Capacitors—MPF100T - FCVG484 (0.8 mm) . . . . . . . . . . . . . . . . . . . 11
Table 12 Power-Supply Decoupling Capacitors—MPF100T - FCG484 (1 mm) . . . . . . . . . . . . . . . . . . . . . . 12
Table 13 Recommended Decoupling Capacitors For PolarFire Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 14 Power Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 15 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 16 Over-Voltage Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 17 RC Oscillator Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 18 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 19 SPI Master Mode Programming Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 20 Transceiver Support in PolarFire Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 21 Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22 Layout Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Microsemi Proprietary UG0726 User Guide Revision 10.0 vi

Revision History

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the current publication.

1.1 Revision 10.0

The following is a summary of changes made in this revision.
• Updated the device variant to MPF300T in table title, see Table 2, page 5.
• Added more information in new footnotes for VDD and VDDA in Table 1, page 4.
• Added footnote in Table 2, page 5 to Table 12, page 12 to specify the objective of decoupling
capacitors.
• Updated I/O Glitch, page 15 and Table 15, page 16 for power-up and power-down sequencing
requirements for mitigating I/O glitch.

1.2 Revision 9.0

The following is a summary of changes made in this revision.
• Updated the glitch information in I/O Glitch, page 15.
• Updated Figure 5, page 17 to power VDDI3 (JTAG Bank) required for cold sparing.

1.3 Revision 8.0

The following is a summary of changes made in this revision.
• Updated the glitch information in I/O Glitch, page 15.
• Added more information on the VDDI and VDDAUX in Power Supplies, page 4.

1.4 Revision 7.0

The following is a summary of the changes made in this revision:
• Added MIPI Hardware Design Guidelines, page 22.
• Added reset guidelines in Reset, page 18.
• Added power-supply decoupling capacitors for the following device packages:
• MPF200T-FCG484 (0.8 mm), see Table 7, page 8.
• MPF200T-FCSG536 (0.5 mm), see Table 8, page 9.
• MPF200T-FCG325 (0.5 mm), see Table 9, page 10.
• MPF100T-FCG325 (0.5 mm), see Table 10, page 10.
• MPF100T-FCG484 (0.8 mm), see Table 11, page 11.

1.5 Revision 6.0

The following is a summary of the changes made in revision 6.0 of this document:
• Reference Voltage (VREFx)information updated in Power Supplies, page 4.
• Added basic information about Pin Assignment Tables, page 15.
• Power-Supply Decoupling Capacitors—MPF300T - FCG1152/FCG784/FCG484 updated in Table 3,
page 6.
• Power-Supply Decoupling Capacitors—MPF500T - FCG1152/FCG784 (1mm), Power-Supply
Decoupling Capacitors—MPF200T - FCG784/FCG484 (1mm), and MPF100T - FCG484 (1mm)
added in Table 2, page 5, Table 6, page 8, and Table 12, page 12 respectively.
• Added MIPI Hardware Design Guidelines, page 22.
• Added Reset, page 18.

1.6 Revision 5.0

The following is a summary of the changes made in revision 5.0 of this document:

Microsemi Proprietary UG0726 User Guide Revision 10.0 1

Revision History

• Details of power supply decoupling capacitors for MPF300-FCG1152, MPF300-FCG484, MPF300-

FCG784, MPF300-FCVG484, and MPF300-FCSG536 devices were updated. For more information,
see Table 3, page 6, Table 4, page 6, and Table 5, page 7.
• XCVR_REF and VDD_XCVR_CLK supply pins details were added. For more information, see
Power Supplies, page 4).
• Information about VDDIx and VDDAUXx power supplies was updated. For more information, see
Unused Power Supply, page 14.
• A note about the power supply constraint of VDDI3 and VDD_XCVR_CLK pins was added. For more
information, see Power Supplies, page 4.
• Details of decoupling capacitors in PolarFire devices were added. For more information, see
Table 13, page 12.
• Additional information about VDDIx, VDDAUXx, and VDD_XCVR_CLK pins was added. For more
information, see Unused Power Supply, page 14.
• The design checklist for XCVR pins was updated. For more information, see Table 21, page 25.
• Information about VREF was added to core power supply operation details. For more information,
see Power Supplies, page 4.
• Information about cold sparing was updated. For more information, see Cold Sparing, page 16.
• JTAG pin details were updated. For more information, see Table 18, page 19.
• The SPI master mode programming connectivity diagram was updated. For more information, see
Figure 7, page 20.
• Information about device reset was updated. For more information, see Reset, page 18.
• DDR3 and DDR4 placement and routing guidelines were removed. These guidelines are available in
UG0676: PolarFire FPGA DDR Memory Controller User Guide.

1.7 Revision 4.0

Revision 4.0 was published in September 2017. The sections Termination Schemes and PCB Capacitor
Placement and Mounting Techniques were removed from this document.

1.8 Revision 3.0

Following is a summary of changes made in revision 3.0 of this document:
• Added the Board Design Checklist chapter. For more information, see Board Design Checklist,
page 25.
• Added the Special Pins, page 21 section in the PolarFire FPGA Board Design, page 3 chapter.
• Updated the Power-up sequence for core supplies. For more information, see Power Supplies,
page 4 and Power-Supply Topology, page 13.
• Removed a note related to XCVR_TX and RX signals under the Unused Power Supply, page 14
section.
• Updated the VDDI pin name from VDDIx to VDDI3 in the Device Programming section. For more
information, see Device Programming, page 19.

1.9 Revision 2.0

Following was a summary of changes made in revision 2.0 of this document:
• Values in the Power-Supply Decoupling Capacitors—MPF300-FCG484 table were updated.
• Values and parameters were updated in the SPI Master Mode Programming Pins table. For more
information, see Table 19, page 20.
• Updated Figure 2. For more information, see Figure 2, page 13.

1.10 Revision 1.0

The first publication of this document.

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PolarFire FPGA Board Design

2 PolarFire FPGA Board Design

Good board design practices are required to achieve expected performance from both PCBs and
PolarFire® devices. High-quality and reliable results depend on minimizing noise levels, preserving
signal integrity, meeting impedance and power requirements, and using appropriate transceiver
protocols. These guidelines must be treated as a supplement to the standard board-level design
practices.
This document is intended for readers who are familiar with the PolarFire device, experienced in digital
board design, and know about the electrical characteristics of systems. It discusses power supplies,
high-speed interfaces, various control interfaces, and the associated peripheral components of PolarFire
FPGAs.

2.1 Designing the Board

PolarFire FPGAs are flash-based FPGAs that support various high-speed memory interfaces such as
DDR3/DDR4, lowest power 12.7 Gbps transceiver (XCVR), built-in low-power dual PCIe Gen2, and
fabric I/O such as high-speed I/O (HSIO) and general-purpose I/O (GPIO).
Subsequent sections discuss the following:
• Power Supplies, page 4
• User I/O, page 16
• Clocks, page 18
• Reset, page 18
• Device Programming, page 19
• Transceiver, page 22
• AC and DC Coupling, page 24
• Brownout Detection, page 24

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2.2 Power Supplies

The following illustration shows the typical power supply requirements for PolarFire devices, and the
recommended connections of power rails when every part of the device is used in a system. For
information on decoupling capacitors associated with individual power supplies, see PolarFire
Decoupling Capacitors, page 5.
Figure 1 • Power Supplies

1.0/1.05 V PolarFire FPGA 2.5/3.3 V

VDD VDD_XCVR_CLK
(Core Supply) (XCVR ref clk Supply)
VSS

1.8/2.5/3.3 V 0.9/1.25 V

VDDI3 (JTAG Bank) (XCVR ref Supply) XCVR_VREF

1.2/1.5/1.8/2.5/3.3 V 2.5 V

VDDIx (GPIO Bank (2, 4, (XCVR PLL Supply) VDDA25

1.2/1.35/1.5/1.8 V and 5))
1.0/1.05 V

VDDIx (HSIO Bank (0, 1,

VDDA
2.5/3.3 V 6, and 7))
(XCVR Tx/Rx Lanes Supply)

VDDAUXx (GPIO Bank AUX)

1.8 V 2.5 V

VDD18 (Programming and HSIO (PLL and PNVM Supply) VDD25

Banks AUX)

For the device to operate successfully, power supplies must be free from unregulated spikes and the
associated grounds must be free from noise. All overshoots and undershoots must be within the absolute
maximum ratings provided in the DS0141: PolarFire FPGA Datasheet.
The following table lists the various power supplies required for PolarFire FPGAs.

Table 1 • Supply Pins

Name Description
XCVR_VREF Voltage reference for transceivers
VDD_XCVR_CLK Power to input buffers for the transceiver reference
clock
VDDA25 Power to the transceiver PLL
VDDA1 Power to the transceiver TX and RX lanes
VSS Core digital ground
VDD2 Device core digital supply
VDDI3 (JTAG Bank) Power to JTAG bank pins

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Table 1 • Supply Pins (continued)

Name Description
VDDIx (GPIO Banks) Power to GPIO bank pins
VDDIx (HSIO Banks) Power to HSIO bank pins
VDD25 Power to corner PLLs and PNVM
VDD18 Power to programming and HSIO auxiliary supply
VDDAUXx Power to GPIO auxiliary supply

1. VDDA—This supply can be powered to 1.0V or 1.05V. For more information, see
tables 4-2 in DS0141: PolarFire FPGA Datasheet. This is a quiet supply for the
device. One method would be to use a Linear regulator to ensure the supply is
quiet.
2. VDD —This supply can be powered to 1.0V or 1.05V. For more information, see
tables 4-2 in DS0141: PolarFire FPGA Datasheet.

• VREFx—is the reference voltage for DDR3 and DDR4 signals. VREF voltages can be generated
internally and externally.
• Internal VREF - not subjected to PCB and package inductance and capacitance loss. These
changes provide the highest performance and can be programmed as required by DDR
controller.
• External VREF—is fixed and cannot be programed as required. The PCB and package
inductance and capacitance impact the VREF performance.
If VDDI and VDDAUX need to be configured to the same voltage (2.5V or 3.3V), ensure both VDDI and
VDDAUX are supplied from the same regulator. Do not use different regulators to source these rails. This
prevents any voltage variations between VDDI and VDDAUX. In this case, the board must not supply the
VDDI and VDDAUX from individual voltage supplies.
When a GPIO bank requires the VDDI to be less than 2.5V (1.2V, 1.5V, or 1.8V), the VDDAUX for that
bank must be tied to 2.5V supply irrespective of the VDDI supply. The VDDI requires a separate supply
for the specific I/O type (1.5V or 1.8V).
Note: The on-chip power-on reset circuitry requires the VDD, VDD18, and VDD25 supplies to ramp monotonically
from 0 V to the minimum recommended operating voltage.
For a detailed pin description, see UG0722: PolarFire FPGA Packaging and Pin Descriptions User
Guide.

2.2.1 PolarFire Decoupling Capacitors

The following table lists the requirement of all decoupling capacitors for the MPF300-FCG1152 device.

Table 2 • Power-Supply Decoupling Capacitors1—MPF300T - FCG1152/FCG784 (1mm)

Ceramic Tantalum
Pin Name 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 3
VDD18 2 2
VDD25 5 1
VDDA 3 1 6 2
VDDA25 4 1
VDDIO3 2 1
VDDAUXx 2 2 1
GPIO Bank3 2 1

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Table 2 • Power-Supply Decoupling Capacitors1—MPF300T - FCG1152/FCG784 (1mm) (continued)

Ceramic Tantalum
Pin Name 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
HSIO Bank4 2 1
VDD_XCVR_CLK 2 1
XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on a different
PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power delivery to the FPGA.
Please follow the recommended operational conditions as per DS0141: PolarFire FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

The following table lists the requirement of all decoupling capacitors for the MPF300T-FCG1152/784/484
(1 mm).

Table 3 • Power-Supply Decoupling Capacitors1—MPF300T - FCG1152/FCG784/FCG484 (1 mm)

Ceramic Tantalum
Pin Name 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 2
VDD18 2 2
VDD25 5 1
VDDA 3 1 6 1
VDDA25 4 1
2
VDDAUXx 5 1
VDDIO3 2 1
GPIO Bank3 2 1
HSIO Bank4 2 1
VDD_XCVR_CLK 2 1
XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on a different
PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power delivery to the FPGA.
Please follow the recommended operational conditions as per DS0141: PolarFire FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

The following table lists the requirement of all decoupling capacitors for the MPF300-FCVG484 (0.8mm)
device.

Table 4 • Power-Supply Decoupling Capacitors1—MPF300T - FCVG484 (0.8mm)

Ceramic Tantalum
Pin Name 1 nF 2.2 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 1 2
VDD18 2 2
VDD25 5 1

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Table 4 • Power-Supply Decoupling Capacitors1—MPF300T - FCVG484 (0.8mm) (continued)

Ceramic Tantalum
Pin Name 1 nF 2.2 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDDA 2 2 1 1
VDDA25 1 1 1
VDDAUXx 2 2 1
VDDIO3 2 1
3
GPIO Bank 2 1
4
HSIO Bank 2 1
VDD_XCVR_CLK 2 1
XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on a different
PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power delivery to the FPGA.
Please follow the recommended operational conditions as per DS0141: PolarFire FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

The following table lists the requirement of all decoupling capacitors for the MPF300-FCSG536 (0.5mm)
device.

Table 5 • Power-Supply Decoupling Capacitors1—MPF300T - FCSG536 (0.5mm)

Ceramic Tantalum
Pin Name 1 nF 2.2 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 1 2
VDD18 1 2 2
VDD25 5 1
VDDA 2 3 1 1 1
VDDA25 1 1 1
VDDAUXx2 2 1
VDDIO3 2 1
GPIO Bank3 2 1
HSIO Bank4 2 1
VDD_XCVR_CLK 2 1
XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on a different
PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power delivery to the FPGA.
Please follow the recommended operational conditions as per DS0141: PolarFire FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

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Table 6 • Power-Supply Decoupling Capacitors1—MPF200T - FCG784/FCG484 (1mm)

Ceramic Tantalum
Pin Name 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 2 2 2
VDD18 2 2
VDD25 5 1
VDDA 3 1 6 1
VDDA25 4 1
VDDIO3 2 1
VDDAUXx2 2 1
3
GPIO Bank 2 1
HSIO Bank4 2 1
VDD_XCVR_CLK 2 1
XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on a different
PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power delivery to the FPGA.
Please follow the recommended operational conditions as per DS0141: PolarFire FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

The following table lists the requirement of all decoupling capacitors for the MPF200T-FCG484 (0.8 mm)
device.

Table 7 • Power-Supply Decoupling Capacitors1—MPF200T - FCVG484 (0.8 mm)

Ceramic Tantalum
Pin Name
1 nF 2.2 nF 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 1 2
VDD18 2 2
VDD25 5 1
VDDA 2 2 1 1
VDDA25 1 1 1
VDDIO3 2 1
2
VDDAUXx 2 1
GPIO Bank3 2 1
4
HSIO Bank 2 1

VDD_XCVR_CLK 2 1

XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on a different
PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power delivery to the FPGA.
Please follow the recommended operational conditions as per DS0141: PolarFire FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

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The following table lists the requirement of all decoupling capacitors for the MPF200T-FCSG536 (0.5 mm) device.

Table 8 • Power-Supply Decoupling Capacitors1—MPF200T - FCSG536 (0.5 mm)

Ceramic Tantalum
Pin Name
1 nF 2.2 nF 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 1 2
VDD18 2 2
VDD25 5 1
VDDA 2 3 1 1 1
VDDA25 1 1 1
VDDIO3 2 1
2 2 1
VDDAUXx
GPIO Bank3 2 1
4
HSIO Bank 2 1

VDD_XCVR_CLK 2 1

XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on a
different PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power delivery to
the FPGA. Please follow the recommended operational conditions as per DS0141: PolarFire FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

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The following table lists the requirement of all decoupling capacitors for the MPF200T-FCG325 (0.5 mm) device.

Table 9 • Power-Supply Decoupling Capacitors1—MPF200T - FCSG325 (0.5 mm)

Ceramic Tantalum
Pin Name
1 nF 2.2 nF 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 1 2
VDD18 2 2
VDD25 5 1
VDDA 1 1 1 1 1
VDDA25 1 1 1
VDDIO3 2 1
2 2 1
VDDAUXx
GPIO Bank3 2 1
4
HSIO Bank 2 1

VDD_XCVR_CLK 2 1

XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed on
a different PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power
delivery to the FPGA. Please follow the recommended operational conditions as per DS0141: PolarFire FPGA
Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

The following table lists the requirement of all decoupling capacitors for the MPF100T-FCSG325 (0.5 mm) device.

Table 10 • Power-Supply Decoupling Capacitors1—MPF100T - FCSG325 (0.5 mm)

Ceramic Tantalum
Pin Name 1 nF 2.2 nF 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 1 1
VDD18 2 2
VDD25 5 1
VDDA 1 1 1 1 1
VDDA25 1 1 1
VDDIO3 2 1
2 2 1
VDDAUXx
GPIO Bank3 2 1
4
HSIO Bank 2 1

VDD_XCVR_CLK 2 1

XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed
on a different PCB or delivered through interconnects (flex cables or connectors), please ensure an effective
power delivery to the FPGA. Please follow the recommended operational conditions as per DS0141: PolarFire
FPGA Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.

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3. Required Decoupling Capacitor for each GPIO bank.

4. Required Decoupling Capacitor for each HSIO bank.

The following table lists the requirement of all decoupling capacitors for the MPF100T-FCVG484 (0.8
mm) device.

Table 11 • Power-Supply Decoupling Capacitors1—MPF100T - FCVG484 (0.8 mm)

Ceramic Tantalum
Pin Name 1 nF 2.2 nF 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 4 1 1
VDD18 2 2
VDD25 5 1
VDDA 2 2 1 1
VDDA25 1 1 1
VDDIO3 2 1
2 2 1
VDDAUXx
GPIO Bank3 2 1
4 2 1
HSIO Bank

VDD_XCVR_CLK 2 1

XCVR_VREF 2

1. The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is placed
on a different PCB or delivered through interconnects (flex cables or connectors), please ensure an effective power
delivery to the FPGA. Please follow the recommended operational conditions as per DS0141: PolarFire FPGA
Datasheet.
2. Required Decoupling Capacitor for each VDDAUXx.
3. Required Decoupling Capacitor for each GPIO bank.
4. Required Decoupling Capacitor for each HSIO bank.

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Table 12 • Power-Supply Decoupling Capacitors—MPF100T - FCG484 (1 mm)

Ceramic Tantalum
Pin Name 4.7 nF 10 nF 0.1 µF 1 µF 4.7 µF 10 µF 47 µF 330 µF
VDD 2 2 1
VDD18 2 2
VDD25 5 1
VDDA 3 1 6 1
VDDA25 4 1
VDDIO3 2 1
VDDAUXx 1 2 1
2
GPIO Bank 2 1
HSIO Bank3 2 1
VDD_XCVR_CLK 2 1
XCVR_VREF 2

1. Required Decoupling Capacitor for each VDDAUXx.

2. Required Decoupling Capacitor for each GPIO bank.
3. Required Decoupling Capacitor for each HSIO bank.

Note: The guidelines are provided on how to effectively decouple only the FPGA device. If the power source is
placed on different PCB or delivered through interconnects (flex cables or connectors), please ensure an
effective power delivery to the FPGA. Please follow the recommended operational conditions as per
DS0141: PolarFire FPGA Datasheet.
Decoupling capacitors other than those listed in the previous tables can be used if the physical sizes of
capacitors meet or exceed the performance of the network given in this example. Substitution would
require analyzing the resulting power distribution system's impedance versus frequency to ensure that
no resonant impedance spikes the result. See Figure 1, page 4 for power supply design.
For more information about the internal package capacitance for power supplies associated with
PolarFire packages, see section 2.4.2.1 section of UG0722: PolarFire FPGA Packaging and Pin
Descriptions User Guide.
The following table lists the required decoupling capacitors for PolarFire packages.

Table 13 • Recommended Decoupling Capacitors For PolarFire Devices

De-Cap Value Part Number Package Description

0.1 µF GRM155R71C104KA88D 0402 For 1 mm package
10 nF GRM15XR11C103KA86 0402 For 1 mm package
4.7 nF GRM155R11H472KA01 0402 For 1 mm package
10 µF GRM21BR71A106KE51 0805 Bulk Caps (for 0.5, 0.8, and 1 mm)
47 µF GRM31CR61A476KE15 1206 Bulk Caps (for 0.5, 0.8, and 1 mm)
330 µF T495D337K010ATE150 2917 Bulk Caps (for 0.5, 0.8, and 1 mm)
1 nF GRM033R71C102KA01 0201 For 0.8/0.5 mm package
2.2 nF GRM033R71A103KA01 0201 For 0.8/0.5 mm package
10 nF GRM033R71A103KA01 0201 For 0.8/0.5 mm package
0.1 µF GRM033C71C104KE14 0201 For 0.8/0.5 mm package

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Note: The user can use equivalent capacitor values from a different vendor. For more information about
Packaging Decoupling Capacitors, see UG0722: PolarFire FPGA Packaging and Pin Descriptions User
Guide.

2.2.2 Power-Supply Topology

PolarFire FPGAs require multiple power supplies. Figure 2, page 13 shows a power supply topology
example for generating the required power supplies from a single 12 V source. This example is based on
the PolarFire MPF300-FCG1152 device with DDR3 and DDR4 interfaces.
Figure 2 • Example Power-Supply Topology

VDD25/VDDA25/
12V Switching 5V VDD_XCVR_CLK
Linear Regulator
Regulator 2.5 V

Linear or Bank Supply

Switching Regulator 3.3/2.5/1.8/1.5/1.35/1.2 V

VDD18/Bank Supply
Linear Regulator
1.8 V

Switching VDDAUX[2, 4]
Regulator 2.5 V/3.3 V

Switching VDDAUX5
Regulator 2.5 V/3.3 V

Switching VDD
Regulator 1.0V\1.05 V

Switching 3.3 V
Regulator
Linear VDDA
Regulator 1.0V\1.05
Switching Bank Supply
Regulator 1.5 V
Linear DDR3-VTT
Regulator 0.75 V
Switching Bank Supply
Regulator 1.2 V Linear DDR4-VTT
Regulator 0.6 V

The following table lists the suggested Microchip power regulators for PolarFire FPGA voltage rails.

Table 14 • Power Regulators

Voltage rail Part Number Description Current

5V MIC24055YJL-TR IC REG BUCK ADJ 12A SYNC 28QFN 12A
VDD (1.0V) MIC45212-2YMP-T1 DC DC CONVERTER 0.8-5.5V 77W 14A
VDDIO (3.3V) MIC24055YJL-TR IC REG BUCK ADJ 12A SYNC 28QFN 12A
VCCIO_HPC_VADJ MIC24046YFL-TR IC REG BUCK PROG 5A SYNC 20VQFN 5A
DDR4 (1.2V) MIC23303YML-T5 IC REG BUCK ADJ 3A SYNC 12DFN 3A
DDR3 (1.5V) MIC23303YML-T5 IC REG BUCK ADJ 3A SYNC 12DFN 3A
VDDAUX[2,4] MIC23303YML-T5 IC REG BUCK ADJ 3A SYNC 12DFN 3A

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Table 14 • Power Regulators (continued)

Voltage rail Part Number Description Current

VDDAUX5 MIC23303YML-T5 IC REG BUCK ADJ 3A SYNC 12DFN 3A
VTT_DDR4 (0.6V) MIC5166YML-TR IC PWR SUP 3A HS DDR TERM 10MLF 3A
VTT_DDR3 (0.75V) MIC5166YML-TR IC PWR SUP 3A HS DDR TERM 10MLF 3A
VDDIO (1.8V) MIC24046YFL-TR IC REG BUCK PROG 5A SYNC 20VQFN 5A
VDDA (1.0V) MIC69502WR IC REG LINEAR POS ADJ 5A SPAK-7 5A
VDD25, VDDA25, MIC69502WR IC REG LINEAR POS ADJ 5A SPAK-7 5A
VDD_XCVR_CLK
VDD18 MIC69502WR IC REG LINEAR POS ADJ 5A SPAK-7 5A

2.2.3 Unused Power Supply

Figure 3, page 14 shows how power supplies may be configured when not in use and also to reduce
leakage and power for the system.
Figure 3 • Option 1 for unused Connections

1.0/1.05 V PolarFire 1.8/2.5/3.3 V

Power Supplies

VDD VDDI3 (JTAG Bank)

1.8 V 10 k
XCVR_VREF
VDD18
2.5 V 10 k
VDDAUXx (GPIO Bank AUX)
VDD25
10 k
VDD_XCVR_CLK
10 k
VDDA

10 k
VDDA25

10 k
VDDIx(HSIO Banks)

10 k
VDDIx(GPIO Banks)

Figure 4, page 15 also shows the power configuration of unused supplies. This option can be used when
there is an intent to power-up the various supplies at a later time in the system and the I/Os are not being
used.

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Figure 4 • Option 2 for Unused Connections

1.0/1.05 V PolarFire 2.5/3.3 V

Power Supplies

VDD VDD_XCVR_CLK
1.8 V 10 k
XCVR_VREF
VDD18
2.5 V 1.8/2.5/3.3 V

VDD25 VDDI3 (JTAG Bank)

1.0/1.05 V
2.5/3.3 V

VDDA VDDAUXx (GPIO Bank AUX)

2.5 V

VDDA25
1.2/1.35/1.5/1.8 V

VDDIx(HSIO Banks)
1.2/1.5/1.8/
2.5/3.3 V

VDDIx(GPIO Banks)

Note: To simplify the board-level routing, multiple 10 kΩ resistors can be used as required. Or the power
supplies can also be grouped into a single 10 kΩ resistor and tied-off to VSS.

2.2.4 Pin Assignment Tables

The Packaging Pin Assignment Table (PPAT) is available on the Microsemi PolarFire documentation web
page (https://www.microsemi.com/products/fpga-soc/fpga/polarfire-fpga#documentation). PPAT contains
information about the recommended DDR pin-outs, PCI EXPRESS capability for XCVR-0, DDR Lane
information for IO CDR, generic IOD interface pin placement, and unused condition for package pins.

2.3 I/O Glitch

A glitch may occur during power-up or power-down for GPIO/HSIO outputs in PolarFire devices. Glitch
can occur before or after the device reaches a functional state. These glitches are not observed on LVDS
outputs or Transceiver I/Os. No reliability issues are caused by either of the glitch types. There are three
types of glitch that can occur.
• Parasitic glitches may occur for GPIOs or HSIOs before the device reaches functional state with a
maximum glitch of 1V with a 0.4 ms width. This type of glitch can typically be ignored. It is
recommended to use a 100K pull-down resistor on critical signals1 of the GPIO or HSIO pins if this
type of glitch cannot be ignored. No glitches are observed once mitigation recommendations are
placed.
• Another type of glitch may occur on GPIOs and HSIOs during power-on sequencing or boot-up. This
is due to a weak pull up resistor being enabled by default on an input, output or bidirectional I/O. To
mitigate this glitch, use the Libero SoC I/O Editor or PDC constraint to program a weak pull-down on
the output buffer on the specified I/O.

1.Critical outputs like reset or clock of the HSIO or GPIOs going into another device.

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PolarFire FPGA Board Design

• The last type of glitch may occur after the device reaches functional state. This type of glitch is
related to the power-up and power-down sequence of VDDI and VDDAUX supplies. This occurs
only on GPIOs where the VDDI is 1.5V or 1.8V only with a maximum glitch of 1V with a 0.8 ms width
during power-up and a maximum glitch of 1.8V with a 1 ms width during power down. To mitigate the
post functional state glitch, please follow the recommendations in the following table.

Table 15 • Power Sequencing1

Power-up Sequencing Requirement for Power-down Sequencing Requirements

Use Cases for GPIO Mitigating Glitches2 for Mitigating Glitches2
VDDI VDDAUX
1.2V 2.5V No Glitch occurs No Glitch occurs
1.5V 2.5V Power up VDDAUX before VDDI of that Power down VDDI before VDDAUX of that
bank bank
1.8V 2.5V Power up VDDAUX before VDDI of that Power down VDDI before VDDAUX of that
bank bank
2.5V 2.5V Power VDDAUX and VDDI from the same No Glitch occurs
Regulator
3.3V 3.3V Power VDDAUX and VDDI from the same No Glitch occurs
Regulator

1. No glitches are observed once mitigation recommendations are placed.

2. The above power sequence does not mitigate any parasitic glitches. As mentioned above please add a 100K pull down
resistors to critical signals of GPIO or HSIO pins for mitigation of parasitic glitches.

2.4 User I/O

PolarFire FPGAs have two types of I/O buffers: HSIO and GPIO. HSIO buffers are optimized for
single-ended buffers with supplies from 1.2 V to 1.8 V. GPIO buffers support single-ended and true
differential interfaces with supplies from 1.2 V to 3.3 V.
Note: When the HSIO bank is configured as an LVDS receiver, the concerned I/Os must be connected
externally by a 100 Ω resistor.
For more information about key features of I/O buffers and supported standards, see UG0722: PolarFire
FPGA Packaging and Pin Descriptions User Guide and UG0686: PolarFire FPGA User I/O User Guide.

2.4.1 Cold Sparing

PolarFire devices support cold sparing for GPIO and HSIO. Cold sparing is implemented by connecting
the devices as shown in the following figure. The system board has two PolarFire devices in parallel and
the devices share I/O. The spare device has its HSIO VDDI banks powered-up to prevent I/O leakage
through the ESD diodes. As a result, low power and a protected state for the spare device is
established.The spare device can be changed to active device by powering-up all the supplies. The
active device can be changed to spare device by powering down all the supplies except HSIO VDDI
banks.
A typical cold sparing application integrates two parallel devices with shared I/O connections, as shown
in the following figure.

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PolarFire FPGA Board Design

Figure 5 • Cold Sparing

1.0/1.05 V

Device 1 10 k Device
VDD VDD
1.2–3.3V (Active) (Spare)
10 k
VDDI[GPIO Banks] VDDI[GPIO Banks]

2.5/3.3V 10 k
VDDAUX
VDDAUX
10 k
2.5V VDD25
VDD25 10 k
1.8V VDD18
VDD18
1.2–1.8V 1.2–1.8V
VDDI[HSIO Banks]
VDDI[HSIO Banks]
1.8/2.5/3.3V
1.8/2.5/3.3V
VDDI3[JTAG Bank] VDDI3[JTAG Bank]
1.0/1.05V
10 k
VDDA VDDA
2.5V
10 k
VDDA25 VDDA25
2.5/3.3V
10 k
VDD_XCVR_CLK VDD_XCVR_CLK

Shared I/Os

Other
Chips

Note: Transceiver pins do not support the cold sparing feature.

2.4.2 Hot Socketing (GPIO Only)

Hot socketing (also known as hot swapping or hot plug-in) prevents damage to the PolarFire FPGA if, at
any time, voltage is detected at I/O while the device is powered off. It also helps prevent disruptions that
may occur in the rest of the system if the I/O of a device are connected without a valid power supply.
Only GPIOs support hot socketing. In hot socketing, GPIOs are in high-impedance (hi-Z) state.
The GPIO maintains the following high-impedance state until the power supplies are at a valid state.
• VDDAUx is greater than or equal to 1.6 V
• VDDIx is greater than or equal to 0.8 V
• VDD and VDD25 are both high and the PolarFire FPGA controller has asserted the global I/O ring
signal (IO_EN)

2.4.2.1 Over-Voltage Tolerance for GPIO

If GPIO is configured with the following settings, GPIO supports over-voltage tolerance, ensuring that the
I/O signal at the pad is at a higher potential than the VDDIx power supply.

Table 16 • Over-Voltage Tolerance

Weak Pull-Up/
Standard OE Clamp Diode VREF (Input) Pull-Down Termination Hot-plug
PCI x On On On On Disabled
GPIO 1 On On On On Disabled
0 Off Off Off Off Enabled

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For recommended operating conditions about over-voltage tolerance, see DS0141: PolarFire FPGA
Datasheet.

2.5 Clocks
PolarFire devices offer two on-chip RC oscillators (one 2 MHz and one 160 MHz) to generate
free-running clocks. The clocks do not have any I/O pads and do not require external components to
operate.
The following table lists the number of RC oscillators available in PolarFire devices.

Table 17 • RC Oscillator Count

Resource Supported Range (MHz) MPF100 MPF200 MPF300 MPF500

On-chip oscillator 2 1 1 1 1
160 1 1 1 1

For more information about clocking in PolarFire devices, see UG0684: PolarFire FPGA Clocking
Resources User Guide.

2.6 Reset
For designing a robust system users may use the dedicated DEVRST_N pin or a general purpose reset
signal using any GPIO/HSIO as a global system level reset.
For the following cases the users must use the DEVRST_N as a warm reset for the device:
• A user design modifies auto-initialized fabric RAMs or PCIe configuration during operation.
• A user design is using PCIe, transceivers or user crypto.
For all other use cases, it is recommended to use a general purpose reset signal using any GPIO/HSIO
IO because they take much shorter time for design to come out of reset.
If the dedicated DEVRST_N is not used for warm resets, the DEVRST_N pin must be configured using
one of the following methods:
• Drive the signal with a POR chip or an external device and keep the DEVRST_N asserted till the
system/clocks are stable and the chip is properly powered up.
• Connect DEVRST_N to VDDI3 through a 1 kΩ resistor per pin without sharing with any other pins.
• In this case the user needs to ensure that all clocks are stable going to the device before the
user design is released from power-on reset. The details of the minimum time taken for the
fabric design to be activated after power-on is specified in the PolarFire datasheet (Power-Up
To Functional section).

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2.7 DDR
PolarFire devices support DDR3, DDR3L, LPDDR3, and DDR4. For more information about the DDR
support in PolarFire devices, see DS0141: PolarFire FPGA Datasheet.
The reliability of the DDR interface depends on the quality of the layout. For detailed information on
board layout and routing, see UG0676: PolarFire FPGA DDR Memory Controller User Guide.

2.8 Device Programming

The PolarFire device can be programmed using one of two dedicated interfaces: JTAG or SPI. These two
interfaces support the following programming modes:
• JTAG programming
• SPI master mode programming
• SPI slave mode programming
The PolarFire FPGA supports programming modes through the internal system controller using SPI
master mode, or an external master using JTAG or SPI interfaces. For detailed information on hardware
connections for each programming mode, see UG0714: PolarFire FPGA Programming User Guide.

2.8.1 JTAG Programming

The JTAG interface is used for device programming and testing, or for debugging firmware. When the
device reset (DEVRST_N) is asserted, JTAG I/Os are not accessible. JTAG I/Os are powered by Bank 3
VDDI.
The following illustration shows the board-level connectivity for JTAG programming mode in PolarFire
devices.
Figure 6 • JTAG Programming

VDDI3

1k VDDI3

PolarFire FPGA JTAG Header

CONN P\N:
HTST-105-01-L-DV-A
SPI_EN
2
GND
System Controller
1
TCK TCK 4
JTAG Controller

3 PROG_MODE x
TDO TDO
5 6
TMS TMS
7 VJTAG
VPUMP
9 8
TDI TDI
TRST
TRSTB
1k 10
GND
IO_CFG_INTF

1k

1k

The following table lists the JTAG pin names and descriptions.

Table 18 • JTAG Pins

Pin Names Direction Unused Condition Description

TMS Input DNC JTAG test mode select.
TRSTB Input Must be connected to VDDI3 JTAG test reset.
through a 1 kΩ resistor Must be held low during
device operation.

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Table 18 • JTAG Pins (continued)

Pin Names Direction Unused Condition Description

TDI Input DNC JTAG test data in.
TCK Input Must be connected to VSS JTAG test clock.
through a 10 kΩ resistor
TDO Output DNC JTAG test data out.

2.8.2 SPI Master Mode Programming

The embedded system controller contains a dedicated SPI block for programming, which can operate in
master or slave mode. In master mode, the PolarFire device interfaces are used to download
programming data through the external SPI flash. In slave mode, the SPI block communicates with a
remote device that initiates download of programming data to the device.
The following illustration shows the board-level connectivity for SPI master mode programming in
PolarFire devices.
Figure 7 • SPI Master Mode Programming

VDDI3 VDDI3 VDDI3 VDDI3

10 k
1k PolarFire FPGA External
(SPI Master) 10 k SPI Flash
WP
SPI_EN Vcc
HOLD
System Controller

SS CS
SPI
SCK SCK
SDO MOSI
SDI MISO

4.7 k GND

IO_CFG_INTF
1k

The following table lists the SPI master mode programming pins.

Table 19 • SPI Master Mode Programming Pins

SPI Pin Name Direction Unused Condition Description

SCK Bidirectional Connect to VSS SPI clock.1
through a
10 kΩ resistor
SS Bidirectional Connect to VSS SPI slave select.1
through a
10 kΩ resistor

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Table 19 • SPI Master Mode Programming Pins (continued)

SPI Pin Name Direction Unused Condition Description

SDI Input Connect to VDDI3 SDI input.1
through a
10 kΩ resistor
SDO Output DNC SDO output.1
SPI_EN Input Connect to VSS SPI enable.
through a 10 kΩ 0: SPI output tri-stated
resistor 1: Enabled
Pulled up or down through a resistor or
driven dynamically from an external source
to enable or tri-state the SPI I/O.
IO_CFG_INTF Input Connect to VSS SPI I/O configuration.
through a 10 kΩ 0: SPI slave interface
resistor 1: SPI master interface
Pulled up or down through a resistor or
driven dynamically from an external source
to indicate whether the shared SPI is a
master or slave.

1. The SCK, SS, SDI, and SDO pins are shared between the system controller and the FPGA fabric. When the system
controller’s SPI is enabled and configured as a master, the system controller hands over the control of the SPI to the
fabric (after device power-up).

2.8.3 SPI Slave Mode Programming

The following illustration shows the board-level connectivity for SPI slave mode programming in
PolarFire devices.
Figure 8 • SPI Slave Mode Programming
VDDI3 VDDI3
VDDI3

1k 10 k
PolarFire FPGA Header
(SPI Slave)
SPI_EN
2
GND
System Controller
1
SCK SCLK 4
3 PROG_MODE x
SDO MISO
SPI 5
SS SS 6
7 VSPI
VPUMP
SDI 9
MOSI 8
FL_GLD x

10
GND
IO_CFG_INTF

1k 1k

2.8.4 Special Pins

For information about special pins, see Table 13 of UG0722: PolarFire FPGA Packaging and Pin
Descriptions User Guide.

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2.9 Transceiver
The following table lists the transceiver features supported in PolarFire devices, and transceiver blocks
are located on the east corner of the device. PolarFire devices support PCIe interface supports only
Transceiver quad 0.
For more information about implementing PCIe interfaces, see UG0685: PolarFire FPGA PCI Express
User Guide. For more information about implementing other transceiver based interfaces and power
supplies, see UG0677: PolarFire FPGA Transceiver User Guide.
The following table lists the number of transceivers supported in various PolarFire devices.

Table 20 • Transceiver Support in PolarFire Devices

Device Transceiver Lane Tx PLL Reference Clock I/O

MPF100 8 6 12
MPF200 16 11 22
MPF300 16 11 22
MPF500 24 15 30

For more information about supported I/O standards, see UG0686: PolarFire FPGA User I/O User Guide.

2.9.1 Reference Clock

A transceiver reference clock is delivered to each transmit PLL for transmit functions and to each
receiver lane for receive clock data recovery (CDR).

2.9.1.1 Transceiver Reference Clock Requirements

The following are requirements for the transceiver reference clock:
• When differential clock input is provided to the reference clock:
• ODT must be enabled for transceiver reference clock pins.
• Must be within the range of 20 MHz to 400 MHz.
• Must be within the tolerance range of I/O standards. The reference input buffer is provided and is
expected to support these input standards directly without external components on the board. The
reference I/O standards such as LVCMOS25, SSTL18, LVDS25, and HCSL25 are supported. For
more information, see UG0677: PolarFire FPGA Transceiver User Guide.
See the PCI Express Base specification Rev 2.1 for detailed PHY specifications. Also, see the PCIe
Add-in Card Electro-Mechanical (CEM) specifications.

2.10 MIPI Hardware Design Guidelines

The following sections discuss the guidelines for MIPI RX and TX interface with PolarFire device.

2.10.1 MIPI RX
The MIPI RX is supported only in GPIO Bank. The corresponding Bank voltage (VDDI), and VDDAUX
voltage must be connected as shown in the following figure.

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PolarFire FPGA Board Design

Figure 9 • MIPI RX Connection

1.2V

VDDIx

MIPI_TX_P

MIPI TX PolarFire FPGA 2.5V

Device
MIPI_TX_N

VDDAUXx

MIPI RX signal connections are as follows:

• Four data and clock must be within one DDR_Lane.
• Connect the data signals to adjacent DDR_Lanes, if more than four data signals are available.
• The MIPI RX clock must be connected to a CLKIN pin.
For more information about DDR_Lane, see the package pin assignment tables available at
https://www.microsemi.com/product-directory/fpgas/3854-polarfire-fpgas#documentation.

2.10.2 MIPI TX
The MIPI LP (Low Power) signals should be connected to a 1.2 V GPIO\HSIO Bank supply and High-
speed signals should be connected to a 2.5 V GPIO Bank supply. Select the HS and LP pins in adjacent
pins to minimize the LP stub. The HS data and clock signals should be in one DDR_Lane. For more
information about DDR_Lane information, see the package pin assignment tables available at
https://www.microsemi.com/product-directory/fpgas/3854-polarfire-fpgas#documentation.
The MIPI TX standard can be implemented by using the resistor divider network for LP (Low Power) and
HS (High speed) signals, as shown in the following figure. The resistor values mentioned in the following
provide a throughput upto of 1 Gbps.
Figure 10 • MIPI TX Connections

PolarFire FPGA

VDDI=1.2V 49.9 ƻ
LP-N MIPI_TX_N
LVCMOS12

GPIO\HSIO MIPI RX
Bank
Device

LP-P 49.9 ƻ MIPI_TX_P

LVCMOS12

VDDI=2.5V 330 ƻ
HS-P

MIPIES25
330 ƻ
HS-N
GPIO Bank

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Note: Run the PDC verification in the Libero tool before moving to layout. To know about MIPI RX electrical
characteristics, refer the DS0141: PolarFire FPGA Datasheet.
For information about the MIPI layout guidelines, see MIPI, page 29.

2.11 AC and DC Coupling

Each transmit channel of a PCIe lane must be AC-coupled to allow link detection. Capacitors used for AC
coupling must be external to the device and large enough to avoid excessive low-frequency drops when
the data signal contains a long string of consecutive identical bits. For non-PCIe applications, Microsemi
recommends that a PolarFire device receives inputs that are AC-coupled to prevent common-mode
mismatches between devices. Suitable values (for example, 0.1 μF) for AC-coupling capacitors must be
used to maximize link signal quality and must conform to DS0141: PolarFire FPGA Datasheet electrical
specifications.
For lower data rates as per the data sheet, DC coupling is supported by PolarFire Transceiver Tx and Rx
interfaces through a configuration option. If a PolarFire transmitter is used to drive a PolarFire receiver in
DC-coupled mode, select the lowest common mode setting for the transmitter.

2.12 Brownout Detection

The PolarFire FPGA functionality is guaranteed only if VDD is above the recommended level specified in
the Datasheet. Brownout detection occurs when VDD drops below the minimum recommended operating
voltage. When this occurs, the device operation may not be reliable. The design might continue to
malfunction even after the supply is brought back to the recommended values because parts of the
device might have lost functionality during brownout. The VDD supply is protected by an built-in brownout
detection circuit.

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Board Design Checklist

3 Board Design Checklist

This chapter provides a set of hardware board design checks for designing hardware using Microsemi
PolarFire FPGAs. The checklists provided in this chapter are a high-level summary checklist to assist the
design engineers in the design process.

3.1 Prerequisites
Ensure that you have gone through the following chapters before reading this chapter:
• PolarFire FPGA Board Design, page 3
• Appendix: General Layout Design Practices, page 29
This checklist is intended as a guideline only. The PolarFire family consists of FPGAs ranging from
densities of 100 K to 500 K logic elements (LEs).

3.2 Design Checklist

The following table lists the various checks that design engineers must take care while designing the
system.

Table 21 • Design Checklist

Guideline Yes/No Remarks

Prerequisites
– See DS0141: PolarFire FPGA Datasheet
– See UG0722: PolarFire FPGA Packaging and Pin Descriptions User Guide
Refer to the board-level schematics of PolarFire Evaluation Kit
Device Selection
Check for available device variants for PolarFire FPGA
– Select a device based on I/O pin count, transceivers, package, phase-
locked loops (PLLs), and speed grade
Check device errata in PolarFire FPGA Errata
Design Checklist
Power Analysis
Download the PolarFire Power Estimator and
check for the power budget.
Power Supply Checklist
See Figure 1, page 4 for used power rails, and Figure 3, page 14 and
Figure 4, page 15 for unused rails.
Decoupling Capacitors
Follow PolarFire Decoupling Capacitors, page 5. Perform PI Analysis for any
deviation from the recommended capacitors.
Clocks
For more information about dynamic phase shift ports, see Table 6 of
UG0684: PolarFire FPGA Clocking Resources User Guide.
The XCVR reference clock ranges from 20 MHz to 400 MHz.

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Board Design Checklist

Table 21 • Design Checklist (continued)

Guideline Yes/No Remarks

The global clock network can be driven by any of the following:
– Preferred clock inputs (CLKIN_z_w)
– On-chip oscillators
– CCC (PLL/DLL)
– XCVR interface clocks

High-Speed I/O Clocks

High-speed I/O clock networks can be driven by I/O or CCCs. The
high-speed I/O clocks can feed reference clock inputs of adjacent CCCs
through hardwired connections.

CCC
The CCC can be configured to have a PLL or DLL clock output, driving a
high-speed I/O clock network.
Global buffer (GB) can be driven through the dedicated global I/O, CCC or
fabric (regular I/O) routing. The global network is composed of GBs to
distribute low-skew clock signals or high-fanout nets.
Dedicated global I/O drive the GBs directly and are the primary source for
connecting external clock inputs (to minimize the delay) to the internal global
clock network.
For more information about global clock network, see UG0684: PolarFire
FPGA Clocking Resources User Guide.

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Table 21 • Design Checklist (continued)

Guideline Yes/No Remarks

Reset
For more information about DEVRST_N and user reset, see Reset, page 18.
DDR Interface
For more information about DDR routing and topology, see UG0676:
PolarFire FPGA DDR Memory Controller User Guide.
Programming and Debugging Scheme
For programming and debugging information, see Device Programming,
page 19.
XCVR
For more information about XCVR, see UG0677: PolarFire FPGA
Transceiver User Guide.
For I/O gearing interfaces, place the clocks and data based on the defined
requirements by selecting the correct I/O. For more information about the
placement of User I/O, see UG0686: PolarFire FPGA User I/O User Guide.
There is one IO_CFG_INTF pin available, which can be used as input.
See the bank location diagrams in the
UG0722: PolarFire FPGA Packaging and Pin Descriptions User Guide to
assess the preliminary placement of major components on PCB.

3.3 Layout Checklist

The following table lists the layout checklist.

Table 22 • Layout Checklist

Guideline Yes/No
Power
Are the 0402 or lesser size capacitors used for all decapacitors?
Is the required copper shape provided to core voltage?
Are the required copper shape and sufficient vias provided to voltages?
Are VREF planes for the DDRx reference supply isolated from the noisy planes?
Are sufficient number of decoupling capacitors used for the DDRx core and VTT
supply?
Is one 0.1 µF capacitor for two VTT termination resistors used for DDRx?
Is the VTT plane width sufficient?
DDR Memories
Are the length-match recommended by Micron followed for DDR memories?
XCVR
Are the length-match recommendations for XCVR followed?
Are DC blocking capacitors required for PCIe interface?
Is tight-controlled impedance maintained along the XCVR traces?
Are differential vias well designed to match XCVR trace impedance?
Are DC blocking capacitor pads designed to match XCVR trace impedance?

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Table 22 • Layout Checklist (continued)

Guideline Yes/No
Dielectric Material
Is proper PCB material selected for critical layers?

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Appendix: General Layout Design Practices

4 Appendix: General Layout Design Practices

This chapter provides guidelines for the hardware board layout that incorporates PolarFire devices. Good
board layout practices are essential to achieve the expected performance from PCBs and PolarFire
devices. They help achieve high-quality and reliable results such as low-noise levels, signal integrity,
impedance, and power requirements. The guidelines mentioned in this document act as a supplement to
the standard board-level layout practices.
This chapter is intended for readers who are familiar with the PolarFire FPGA chip, experience in digital
board layout, and know about line theory and signal integrity.

4.1 MIPI
MIPI RX Layout Guidelines:
The data and clock must be matched within 20 mils in PCB.
MIPI TX Layout Guidelines:
As shown in Figure 11, page 29, the LP and HS resistors must be close to the PolarFire device pin. The
HS signals should be routed to LP resistors to minimize the LP signals PCB stub length. The LP signals
stub should be less than 500 mils. The data lane and clock should be length matched within 20 mils. 8
inches is the maximum length supported.
Figure 11 • MIPI TX Layout

PolarFire FPGA LP-P Pin

Ÿ

Ÿ
HS-P Pin
MIPI RX
Device
Ÿ
HS-N Pin

Ÿ

LP-N Pin

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Appendix: General Layout Design Practices

4.2 Transceiver
Collateral material of the PolarFire FPGA transceiver enables the system implementation easier for the
designer by providing the system solution. Transceivers are high-speed serial connectivity with
built-in, multi-gigabit, multi-protocol transceivers from 250 Mbps to 12.7 Gbps. For these
transceiver-based interfaces, the system designer must be familiar with the industry specifications,
transceivers technology, or RF/microwave PCB design. However, the PCB design can be evaluated by a
knowledgeable high-speed digital PCB designer.

4.2.1 Layout Considerations

This section describes differential traces and skew matching, which must be taken care while designing
the PCB layout.

4.2.1.1 Differential Traces

A well-designed differential trace must have the following qualities:
• No Mismatch in impedance
• Insertion loss and return loss
• Skew within the differential traces
The following points must be considered while routing the high-speed differential traces to meet the
previous qualities.
• The traces should be routed with tight length matching (skew) within differential traces. Asymmetry
in length causes conversion of differential signals in Common mode signals.
• The differential pair should be routed such that the skew within differential pairs is less than 5 mils.
The length match should be used by matching techniques.

4.2.1.2 Skew Matching

The length of differential lanes should be matched within the TX and RX group. This applies only to
specific protocols such as XAUI.
Differential pairs should be routed symmetrically in-to and out of structures, as shown in Figure 13,
page 30.
The following figure shows the skew matching.
Figure 12 • Skew Matching
Skew compensation
deviates too far away
from neighbor trace. Multiple small Trace-to-itself spacing
bumps are better must be at least 4X the Skew is
than one large trace width. compensated as
bump for skew soon as it is needed.
compensation Deviation must not
exceed 3X the nominal
Trace-to-itself trace-to-itself spacing
spacing is too close. rule for the diff pair.
Best way to
compensate for skew
NO!

Do not wait until the

end to put in skew
compensation

Figure 13 • Example of Asymmetric and Symmetric Differential Pairs Structure

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Appendix: General Layout Design Practices

Skin effect dominates as the speed increases. To reduce the skin effect, the width of the trace must be
increased (loosely coupled differential traces). Increase in trace width causes increase in dielectric
losses. To minimize dielectric loss, use low dissipation factor (DF) PCB materials such as
Nelco 4000-13EP SI. Cost is significantly higher than FR4 PCB material, but FR4 PCB material cannot
provide increased eye-opening when longer trace interconnections are required. Ensure that a 85 - 100
Ω differential impedance is maintained. This is an important guideline to be followed if the data rate is 5
Gbps or higher.
Far end crosstalk is eliminated by using stripline routing. However, this type of routing in stripline causes
more dielectric loss. In order to minimize dielectric loss, it is better to route as a microstrip if there is
enough space between differential pairs (>4 times the width of the conductor). Simulations are
recommended to see the best possible routing.
Instruct the fabrication vendor to use these PCB materials before manufacturing.
Transceiver traces must be kept away from the aggressive nets or clock traces. For example, on
MPF300 devices, the transceiver and DDR traces should not be adjacent to each other. Trace stubs
must be avoided.
It is recommended to use low roughness, that is, smooth copper. As the speed increases, insertion loss
due to the copper roughness increases. The attenuation due to skin effect is increased proportional to
the square root of frequency. Microsemi recommends instructing the PCB fabrication house to use
smooth copper, if the frequency exceeds 2 Gbps.
Split reference planes should be avoided. Ground planes must be used for reference for all transceiver
lanes.
Figure 14 • Ground Planes for Reference

4.2.1.3 Via
The target impedance of vias are designed by adjusting the pad clearance (anti-pad size). Field solver
should be used to optimize the via according to the stack-up.
Figure 15 • Via Illustration

Anti-Pad
Pad

Dielectric
Via Typ.

Via
Barrel
Copper
Stub
Planes
Typ.

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• Many vias on different traces should be avoided, or minimized as much as possible.

• The length of via stubs should be minimized by back-drilling the vias, routing signals from the
near-top to the near-bottom layer, or using blind or buried vias. Using blind-vias and back drilling are
good methods to eliminate via stubs and reduce reflections.
• If feasible, non-functional pads should be removed. Non-functional pads on-via are the pads where
no trace is connected. This reduces the via capacitance and stub effect of pads.
Figure 16 • Non-Functional Pads of Via

Circuit
Model
Via

Unused
Pad

Changing Pad and Anti-Pad

diameter changes capacitance

Using tight via-to-via pitches helps reducing the effect of crosstalk, as shown in the following figure.
Figure 17 • Via-to-Via Pitch
NO!
Wide
Placement

GOOD!
Vias are narrowly
spaced

Symmetrical ground vias (return vias) should be used to reduce discontinuity for Common mode signal
components, as shown in the following figure. Common mode of part of the signal requires continuous
return path for TX and RX to GND. Return vias help maintain the continuity.
Figure 18 • GND Via or Return Via

4.2.2 DC Blocking Capacitors

The plane underneath the pads of DC blocking capacitors should be removed, as shown in the following
figure, to match the impedance of the pad to 50 Ω.

Microsemi Proprietary UG0726 User Guide Revision 10.0 32

Appendix: General Layout Design Practices

Figure 19 • Capacitor Pad Reference Plane

Microsemi Proprietary UG0726 User Guide Revision 10.0 33