Lecture No.

Course Name Electronic (3)

CMOS VLSI Design

Lecture 4-1: CMOS Transistor Theory

Instructor Dr. Samia Heshmat

Credits: David Harris
Harvey Mudd College

(Material taken/adapted from Harris’ lecture notes)

email [email protected] CMOS VLSI Design 20 October 2024

 Summary of Shockley model

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body


 0 Vgs  Vt cutoff


I ds =   Vgs − Vt − ds V V  V
V
 ds linear
  
2 ds dsat

 
( gs t )
2
 V − V Vds  Vdsat saturation
2

for nMOS for pMOS

CMOS VLSI Design Slide 2

 C-V Characteristics
❑ Each terminal of an MOS transistor has capacitance
to the other terminals.
❑ These capacitances are nonlinear and voltage
dependent (C-V)
❑ These capacitances can be approximated as simple
capacitors when their behavior is averaged across
the switching voltages of a logic gate

CMOS VLSI Design Slide 3

 Capacitance
❑ Any two conductors separated by
an insulator have capacitance
❑ Gate to channel capacitor is very
important
– Creates channel charge
necessary for operation
❑ Source and drain have
capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance
because it is associated with
source/drain diffusion

CMOS VLSI Design Slide 4

 Gate Capacitance
❑ High gate capacitance is required to obtain high Ids.
❑ The gate capacitor can be viewed as a parallel plate
capacitor with the gate on top and channel on
bottom with the thin oxide dielectric between.

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

CMOS VLSI Design

 Gate Capacitance
❑ Cgs = oxWL/tox = CoxWL = CpermicronW
❑ Cpermicron is typically about 2 fF/m (for L=0.6)

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

CMOS VLSI Design Slide 6

 Source/Drain diffusion capacitance

❑ Csb, Cdb
❑ Undesirable, called parasitic
Channel-stop implant
capacitance N
A1

❑ Capacitance depends on area Side wall

and perimeter W Source
ND
– Use small diffusion nodes Bottom
– Comparable to Cg
xj Side wall
– Varies with process Channel
LS SubstrateNA

CMOS VLSI Design Slide 7

 Diffusion Capacitance
❑ Csb, Cdb
❑ Undesirable, called parasitic capacitance
❑ Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg or
for diffusion w/ contact
– Reduced for merged
transistors (uncontacted)
– Varies with process

CMOS VLSI Design Slide 8

Gate capacitance as a function of Vgs

QuickTime™ and a
decompressor
are needed to see this picture.

CMOS VLSI Design Slide 9

Non-ideal Transistor Behavior
❑ Non-ideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage

CMOS VLSI Design 10

 Ideal Transistor I-V
❑ Shockley long-channel transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds =   Vgs − Vt −  ds linear
 2 
ds dsat

 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2

CMOS VLSI Design 11

 Ideal vs. Simulated nMOS I-V Plot

❑ The saturation current

increases less than Ids (A)

Simulated

squared with increasing 1200

Ideal
Vgs = 1.0

Velocity saturation & Mobility degradation:

Ion lower than ideal model predicts
Vgs . 1000
Ion = 747 mA @

❑ This is caused by effects:

Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

− velocity saturation
Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than

− mobility degradation 400 quadratically with Vgs

Vgs = 0.6

❑ The saturation current of 200 Vgs = 0.6

Vgs = 0.4

the nonideal transistor 0

0 0.2 0.4 0.6 0.8 1
Vds

increases somewhat with

Vds caused by channel
length modulation

CMOS VLSI Design 12

 Ideal vs. Simulated nMOS I-V Plot

❑ The saturation current

increases less than squared Ids (A)

Simulated

with increasing Vgs . 1200

Ideal
Vgs = 1.0

Velocity saturation & Mobility degradation:

Ion lower than ideal model predicts

❑ velocity saturation 1000

Ion = 747 mA @
Channel length modulation: V = V = V

❑ mobility degradation
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8

❑ channel length modulation 600

Velocity saturation & Mobility degradation:
Saturation current increases less than
Vgs = 0.8

❑ higher Vds increases the 400 quadratically with Vgs

Vgs = 0.6

size of the depletion region200 Vgs = 0.6

Vgs = 0.4

around the drain and thus 0

0 0.2 0.4 0.6 0.8 1
Vds

effectively shortens the

channel.

CMOS VLSI Design 13

 Ideal vs. non-ideal
ideal Non-ideal

▪ Saturation current does not increase quadratically with Vgs

▪ Saturation current lightly increases with increase in Vds
CMOS VLSI Design Slide 14
 Ideal vs. non-ideal

▪ There is leakage current when the transistor is in cut off

▪ Ids depends on the temperature

CMOS VLSI Design Slide 15

 ON and OFF Current
Ids (A)
1000
Ion = 747 mA @

❑ Ion = Ids @ Vgs = Vds = VDD

Vgs = Vds = VDD

800 Vgs = 1.0

– Saturation
600

Vgs = 0.8

400

Vgs = 0.6
200

Vgs = 0.4

0 Vds
0 0.2 0.4 0.6 0.8 1

❑ Ioff = Ids @ Vgs = 0, Vds = VDD

– Cutoff

CMOS VLSI Design 16

 Electric Fields Effects
❑ Vertical electric field: Evert = Vgs / tox
– Attracts carriers into channel
– Long channel: Qchannel  Evert
polysilicon
gate
W

t ox
Mobility degradation L
n+ n+

p-type body

❑ Side electric field: Elat = Vds / L

– Accelerates carriers from drain to source
– Long channel: v = Elat
Velocity saturation

CMOS VLSI Design 17

 Electric Fields Effects
❑ Vertical electric field: Evert = Vgs / tox
– Attracts carriers into channel
– Long channel: Qchannel  Evert
polysilicon
gate
W

Mobility degradation t ox

L
n+ n+

p-type body

❑ Side electric field: Elat = Vds / L

– Accelerates carriers from drain to source
– Long channel: v = Elat
Velocity saturation

CMOS VLSI Design 18

 Coffee Cart Analogy
❑ Tired student runs from VLSI lab to coffee cart
❑ Freshmen are pouring out of the physics lecture hall
❑ Vds is how long you have been up
– Your velocity = fatigue × mobility
❑ Vgs is a wind blowing you against the glass (SiO2) wall
❑ At high Vgs, you are buffeted against the wall
– Mobility degradation
❑ At high Vds, you scatter off freshmen, fall down, get up
– Velocity saturation
• Don’t confuse this with the saturation region

CMOS VLSI Design 19

 Mobility Degradation
❑ High Evert effectively reduces mobility
– Collisions with oxide interface

A universal model matches experimental data

CMOS VLSI Design 20

 Velocity Saturation
❑ At high Elat (side elec. field), carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
– Better model

Critical level

CMOS VLSI Design 21

 Vel Sat I-V Effects
❑ Ideal transistor ON current increases with VDD2
W (Vgs − Vt )
2

= (Vgs − Vt )
2
I ds = Cox
L 2 2
❑ Velocity-saturated ON current increases with VDD

I ds = CoxW (Vgs − Vt ) vmax

❑ Real transistors are partially velocity saturated

– Approximate with -power law model
– Ids  VDD
– 1 <  < 2 determined empirically (≈ 1.3 for 65 nm)

CMOS VLSI Design 22

 -Power Model
The α-power law model provides a
simple approximation to capture this
behavior. α is called the velocity
saturation index and is determined by
curve fitting measured I-V data.
The fit is poor at low Vds , but the current
at Vds = VDD matches simulation fairly
well across the full range of Vgs
 0 Vgs  Vt cutoff

( − Vt )

 I dsat = Pc V
 V gs
I ds =  I dsat ds Vds  Vdsat linear 2
 Vdsat
Vdsat = Pv (Vgs − Vt )
 /2
 I dsat Vds  Vdsat saturation
Pc, Pv and alpha are found by fitting the model to the empirical modeling results

CMOS VLSI Design 23