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This document provides a step-by-step guide for designing a JK Flip-Flop using D Flip-Flops in Quartus II software. It includes instructions for creating a new project, adding VHDL files for the D Flip-Flop and JK Flip-Flop modules, compiling the design, and running simulations. The document also details how to set up the waveform editor for simulation input signals and clock settings.

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3 views

embedded lab

This document provides a step-by-step guide for designing a JK Flip-Flop using D Flip-Flops in Quartus II software. It includes instructions for creating a new project, adding VHDL files for the D Flip-Flop and JK Flip-Flop modules, compiling the design, and running simulations. The document also details how to set up the waveform editor for simulation input signals and clock settings.

Uploaded by

ashimsapkota0.32
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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JK-FLIPFLOP USING D FLIP-FLOP

(SEQUENTIAL LOGIC)
DESIGN:
Step 1: Open Quartus II
1. Launch the Quartus II software.
2. Create a new project by clicking File > New Project Wizard.

Step 2: Create a New Project


1. Project Name and Directory:
o Set a directory for the project.
o Name your project (e.g., JK_FlipFlop_Project).
o Click Next.
2. Add Files:
o Skip this step for now. We will add files later.
3. Specify Device:
o Choose the appropriate FPGA device family (e.g., Cyclone II).
o Select a specific device based on your FPGA development board (EP2C35F672C6).
o Click Finish.

Step 3: Create VHDL Files


1. Create the D Flip-Flop Module:
o Go to File > New > VHDL File.
o Copy the D_FlipFlop code provided earlier into the editor.
o Save the file as D_FlipFlop.vhd.
2. Create the JK Flip-Flop Module:
o Create another VHDL file.
o Copy the JK_FlipFlop code provided earlier into the editor.
o Save the file as JK_FlipFlop.vhd.
3. Create the Testbench:
o Create a third VHDL file.
o Copy the TB_JK_FlipFlop code into the editor.
o Save the file as TB_JK_FlipFlop.vhd.

Step 4: Add Files to the Project


1. Go to Project > Add/Remove Files in Project.
2. Add the following files:
o D_FlipFlop.vhd
o JK_FlipFlop.vhd
o TB_JK_FlipFlop.vhd
3. Set JK_FlipFlop as the top-level entity:
o Go to Assignments > Settings > General.
o In the Top-level entity field, type JK_FlipFlop.

Step 5: Compile the Design


1. Click Processing > Start Compilation.
2. Wait for Quartus to compile the project.
o If there are errors, double-check the VHDL code for typos or syntax issues.

SIMULATION:
Open the Waveform Editor:

 Go to File > New > University Program VWF (Vector Waveform File) or Simulation > New
Waveform File.
Insert Nodes/Signals:

 Go to Edit > Insert Node or Bus.

 Use Node Finder to add the signals (J, K, CLK, Q, Q_bar) from your design.
Set Clock Signal (CLK):

 Right-click the CLK signal in the Waveform Editor.

 Select Properties or Clock (depending on your version of Quartus).

 Define the clock's period (e.g., 20 ns for 50 MHz) and duty cycle (e.g., 50%).
Set Input Signals (J, K):
 To set the J and K signals manually:
o Option 1: Use the Toolbar:

 Select the time range in the waveform timeline where you want the input to be 1 or
0.

 Use the Force High (1) or Force Low (0) icons on the toolbar to set the value.
o Option 2: Draw the Waveform:

 Click and drag the waveform for J or K to manually create high (1) or low (0) regions.
Save Your Work:

 Save the .vwf file after defining the input stimuli.


Run the Simulation:

 Set the .vwf file as the simulation input file (under Assignments > Settings > Simulation).

 Run the simulation, and the outputs will be displayed in the Waveform Editor.

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