Lecture 3 – The Wires
Digital Integrated Circuits
Yoonmyung Lee
[email protected]
College of Information & Communication Engineering
Kang Ch. 6.5-6.6
Sungkyunkwan University Rabaey Ch. 4.1-4.5
Materials adapted from Textbook,
KW Kwon, SY Kim (SKKU)
Blaauw, Zhang (U of Michigan)
Integrated Circuits & Systems Design Lab.
Metal Wires
Source: ITRS
Source: Larry Zhao
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Capacitance of Wire Interconnect
VDD VDD
M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2
Cdb1 Cw Cg3
M1 M3
Interconnect
Fanout
Vin Vout
Simplified
Model CL
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Single Wire Capacitance
Parallel-plate capacitance
Fringe capacitance due to fringing field at the edges
(from [Bakoglu89])
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Single Wire Capacitance: Empirical Model
Empirical model for quick capacitance calculation
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Inter-wire Capacitance
Capacitance between wires in multiple layers
(from [Bakoglu89])
Inter-wire capacitance can be significant in advanced technology
EDA tool parasitic extraction: R only, C only, R+C, R+C+CC
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Parasitic Parallel-plate Capacitance Values
Area Capacitance: aF/μm2
FOX PO M1 M2 M3 M4 M5 M6 M7 M8 M9
FOX - 6.37 5.14 2.98 1.99 1.49 1.20 0.99 0.85 3.23 2.45
PO 6.37 - 16.6 5.13 1.99 1.49 1.44 1.16 0.97 3.57 2.64
M1 5.14 16.6 - 15.1 4.28 2.50 1.76 1.36 1.11 3.96 2.85
M2 2.98 5.13 15.1 - 15.1 4.28 2.50 1.76 1.36 4.61 3.17
M3 1.99 1.99 4.28 15.1 - 15.1 4.28 2.50 1.76 5.51 3.57
M4 1.49 1.49 2.50 4.28 15.1 - 15.1 4.28 2.50 6.85 4.09
M5 1.20 1.44 1.76 2.50 4.28 15.1 - 15.1 4.28 9.05 4.79
M6 0.99 1.16 1.36 1.76 2.50 4.28 15.1 - 15.1 13.3 5.77
M7 0.85 0.97 1.11 1.36 1.76 2.50 4.28 15.1 - 25.3 7.26
M8 3.23 3.57 3.96 4.61 5.51 6.85 9.05 13.3 25.3 - 25.3
M9 2.45 2.64 2.85 3.17 3.57 4.09 4.79 5.77 7.26 25.3 -
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Parasitic Fringing-plate Capacitance Values
Fringe Capacitance: aF/μm
FOX PO M1 M2 M3 M4 M5 M6 M7 M8 M9
FOX - 23.4 15.1 13.2 11.5 10.7 10.2 10.4 10.5 12.3 11.2
PO 23.4 - 27.6 15.6 12.6 11.4 10.4 10.4 10.9 12.7 11.2
M1 15.1 27.6 - 26.4 14.5 12.3 11.3 10.8 11.3 13.2 11.8
M2 13.2 15.6 26.4 - 26.4 14.6 12.4 11.6 11.9 13.9 12.3
M3 11.5 12.6 14.5 26.4 - 26.4 14.7 12.7 12.7 14.9 12.8
M4 10.7 11.4 12.3 14.6 26.4 - 26.4 14.9 13.9 16.4 13.5
M5 10.2 10.4 11.3 12.4 14.7 26.4 - 26.8 16.4 18.6 14.3
M6 10.4 10.4 10.8 11.6 12.7 14.9 26.8 - 28.6 22.6 15.3
M7 10.5 10.9 11.3 11.9 12.7 13.9 16.4 28.6 - 33.0 16.7
M8 12.3 12.7 13.2 13.9 14.9 16.4 18.6 22.6 33.0 - 32.4
M9 11.2 11.2 11.8 12.3 12.8 13.5 14.3 15.3 16.7 32.4 -
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Resistance of Wire Interconnect
R= L
HW
L Sheet Resistance
H Ro
R1 R2
W
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Dealing with Resistance
Process: Selective Technology Scaling
Process: Use better interconnect material
e.g. copper, silicide
Design: More interconnect layers, more vias
Silicide
PolySilicon
SiO2
n+ n+
p
Silicides: WSi 2, TiSi 2, PtSi2 and TaSi
Conductivity: 8-10 times better than Poly
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Sheet Resistance Table
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Multi-Level Interconnect
Intel 0.25μm example
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Multi-Level Interconnect
Contact / Via Resistance is significant!!
Via Stack Resistance (Ω)
Diff-M1 11.0
Poly-M1 10.4
M2-M1 4.5
M3-M1 9.5
M4-M1 15.0
M5-M1 19.6
M6-M1 21.8 (180nm CMOS)
Resistance of M1-M6 via stack is equivalent to 0.1mm wire (~20Ω)
Use more vias in parallel to reduce effective contact resistance
Larger via/contact is NOT ALLOWED by process engineers
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The Ideal Wire Model
“Model” – needed for mathematical estimation / simulation
Ideal wire – no Resistance, no Capacitance, no Inductance
No propagation delay
A voltage change at one end is immediately visible at the other end
Entire wire is equipotential
Physically unrealizable
R = 0 : superconductor
C = 0 : zero permittivity (ε0) or infinite distance to other wires
L = 0 : zero permeability (μ0)
The delay is bounded by the speed of light
Local interconnects
Small parasitic – can be approximated with ideal wire
Most other interconnects
Wire delay is substantial
Precise estimation by EDA tool is critical
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Lumped C Model
Low R, only consider C
Rdriver
V
out
Vo ut
cwi re Vin
Driver Clumped
𝑑𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 − 𝑉𝑖𝑛
𝐶𝑙𝑢𝑚𝑝𝑒𝑑 + =0
𝑑𝑡 𝑅𝑑𝑟𝑖𝑣𝑒𝑟
𝑉𝑜𝑢𝑡 𝑡 = 1 − 𝑒 −𝑡/τ 𝑉 𝜏 = 𝑅𝑑𝑟𝑖𝑣𝑒𝑟 × 𝐶𝑙𝑢𝑚𝑝𝑒𝑑
Time to reach 50% point: t50% = ln(2) 𝜏 = 0.69 𝜏
Time to reach 63% point: t63% = ln(e) 𝜏 = 1.00 𝜏
Time to reach 10% 90% point: t10-90% = ln(9) 𝜏 = 2.2 𝜏
Lumped C (or R) model
Simple but inaccurate
Unrealistic for nested node
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Lumped RC Model : The Elmore Delay
Shard path resistance
Elmore delay (time constant – time to reach 63%)
Elmore delay of node ‘i’ in above example
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Elmore Delay of RC Chain
An RC chain example (no nested network)
Elmore delay of node N
Elmore delay of node ‘i’ in above example
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Time Constant of Resistive-Capacitive Wire
Segmented RC wire
Assume total wire length L partitioned into N identical segments
Each segment has…
segment length of L/N
segment resistance of rL/N
𝑳 𝑳
segment capacitance of cL/N 𝒓
𝑵
𝒄
𝑵
with N ∞,
Delay of a wire is a quadratic function of its length
Distributed RC model delay is half of lumped RC model delay (N=1 vs ∞)
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Distributed RC Model
KCL @ node i
ΔL 0 (diffusion equation)
When t << RC
When t >> RC
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Distributed RC Model
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Step Response of Lumped & Distributed RC Network
R R/2 R/2
Vin Vout Vin Vout
C C
(a) (b)
R/4 R/2 R/4 R
Vin V out Vin Vout
C/2 C/2 C/2 C/2
(c) (d)
R/2 R/2 R/3 R/3 R/3
Vin Vout Vin Vout
C/4 C/2 C/4 C/6 C/3 C/3 C/6
(e) (f)
Alternative simulation models for distributed RC network
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Driving a Distributed RC Line
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Driving Long Wires
Propagation vs. Elmore delay expression:
0.69×R×C vs. R×C for portion that can be calculated with lumped RC model
0.38×R×C vs. 0.5×R×C for portion that can be calculated
with distributed RC model
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Driving Distributed RC & Lumped RC Line
Ideal
Driver
Vout1
Vout2
Assume all resistance = R, capacitance = C
Elmore/propagation delay for Vout1
Elmore/propagation delay for Vout2
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