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Materials Today: Proceedings 4 (2017) 10309–10314 www.materialstoday.com/proceedings
ICEMS 2016
Write and Read Assist Techniques for SRAM Memories in
Nanometer Technology
Pulla Reddy A a*, G Sreenivasulu b, R Veerabadra Chary c
a
Research Scholar, Dept. of ECE, Sri Venkateswara University College of Egg, Tirupati, AP,India
b
Professor, Dept. of ECE, Sri Venkateswara University College of Egg, Tirupati, AP, India
c
Senior Manager, INVECAS, Inc
Abstract
SRAM cell stability is the primary concern for future technologies due to process variations like threshold voltage and
supply voltage scaling etc. The increased effect of process variation and increase in parasitic resistance and capacitance in Nano
scale technologies, the lower supply voltages, continuous increase in the size of SRAMs requires additional techniques such as
write assist and read assist to improve the write-ability, readability and stability of SRAM memories. In this paper various write
and read assist techniques are analyzed with their pros and cons and each technique is explained with their implementation and
their impact on write-ability, readability and stability of the SRAM memory. The SRAM bit cell write-ability is very critical at
lower voltages. The impact of the write assist technique analyzed across the process, voltage and temperature range. Along with
improving the write-ability of the SRAM cell the write assist techniques will impact the performance, power and area of the chip.
At lower voltages the noise margin is very crucial for the SRAM cell stability. Read assist techniques help in improving the cell
stability and these techniques analyzed across the process, voltage and temperature range. These read assist techniques not only
helps the readability and stability of SRAM bit cells but they also will impact the performance, power and area of the chip.
© 2017 Elsevier Ltd. All rights reserved.
Selection and Peer-review under responsibility of International Conference on Recent Trends in Engineering and Material
Sciences (ICEMS-2016).
Keywords: Read assist, Write assist, Stability, SRAM memory
* Corresponding author. Tel.: +91-9949921464.
E-mail address:
[email protected]2214-7853 © 2017 Elsevier Ltd. All rights reserved.
Selection and Peer-review under responsibility of International Conference on Recent Trends in Engineering and Material Sciences (ICEMS-
2016).
10310 Pulla Reddy A et al./ Materials Today: Proceedings 4 (2017) 10309–10314
1. Introduction
CMOS technology has been the source of semiconductor devices for ages. Moore's law motivates the technology
scaling in order to improve the performance features such as speed, power consumption and area. The power
consumption is a major concern in VLSI chip design of a battery operated system. Lowering the supply voltage is
the quadratic effect on the power. Down scaling on the supply voltage degrades the Static Noise Margin and Write
Margin of the SRAM bit cell. Process variation effects such as variation in critical dimensions (W and L), oxide
thickness (Tox) also leads to decrease in the write-ability and stability of the SRAM cell. Therefore assist circuits are
needed to maintain the cell stability at lower voltages and process variations.
The conventional 6T SRAM cell structure is shown in the Fig.1. It is composed of two cross-coupled inverters
(M1-M4) with two access transistors (M5, M6) connected to complementary bit-lines (BL, BLB). Both access
transistors are connected to word line (WL) to perform the access write and read operations through the bit lines.
There are three operating modes in SRAM [2]: standby/Hold, read and write. Each mode can define its own
operating margin. When the cell is in the standby, its word line (WL) is connected to ground. In order to hold its data
properly, the cross-coupled two inverters in the cell must sustain bi-stable operating points.
Fig. 1. Conventional 6T SRAM.
In write mode, bit-lines are driven to complementary voltage levels through a write driver. Then, with WL held
high the data on bit-line written to the internal storage node of the bit cell. In read mode the bit-lines are initially pre-
charged to VDD. Then with word-line is selected (VDD) bit-line discharges via M6 and M3 (node Q=0), so that
differential voltage develops across the bit-lines [3]. This differential voltage should be large enough for a sense
amplifier to detect the state of the cell.
To avoid the read disturb, cell ratio, i.e., ratio of strength of the pull-down transistor (M1/M3) to that of the access
transistor (M5/M6), should be sufficiently large. Cell ratio= M1/M5 (large)
Pull up ratio, i.e., ratio of strength of the access transistor (M5/M6) to that of the pull-up transistor (M2/M4)
should be sufficiently large to ensure a proper write operation. Pull up ratio=M5/M2 (large).
1.1. SRAM failure metrics
This paper defines three failure modes [11]: Readability, write-ability and read stability. Write-ability failure
occurs when the internal node voltage does not reach to the desired voltage level. Readability failures occurs when a
read bit lines discharge in specified time is less than the offset of the sense amplifier. Read stability failures occurs
when bit cell contents flip accidentally during the read operation.
This paper is organized as follows. In the first section different write assist methods are analyzed to improve the
write-ability of the SRAM bit cell. In the second section we analyzed various read assist techniques. Fourth section
various assist techniques are compared. Section five concludes the paper.
2. Write Margin Analysis
Write-ability: During write operation a low-going BL discharges the cell node ‘1’when WL is high. When
internal nodes of the bit cell are flipped and reaches to a pre-defined VDD level then write operation is successful as
shown in Fig. 2(b). If the internal nodes do not flip, it is a write failure as shown in Fig. 2(a).
Pulla Reddy A et al./ Materials Today: Proceedings 4 (2017) 10309–10314 10311
Fig. 2. (a) Unsuccessful write operation; (b) Successful write operation.
The ability to write and read which are referred to as write margin (WM), read static noise margin or static noise
margin, tend to decrease with scaling. WM is a measure of the write-ability of an SRAM cell. As reducing the
supply voltage causes the write failures that necessitate the need of additional circuitry to assist the SRAM cell to
operate at a lower supply range. To improve the WM of SRAMs, several write assist techniques have been
suggested [12]. These techniques are cell VDD collapse, Negative Bit-Line (NBL), Boosted Word-Line (BWL), cell
GND boost. These techniques are shown in Fig.3.
Fig. 3. Write-ability assist techniques.
2.1. Negative bit line voltage (NBL) write assist
Deep submicron SRAM suffers from large variability and problems associated with those. One of those problems
is write failure under extreme process conditions associated with process mismatch. Supply voltage scaling has put
stability issues. To maintain noise margin, we need to design cell for non-destructive read operation. This
requirement puts a limitation to the extent the memory cell can be made writable. Pulling the bit line below GND is
the most efficient way of providing Write Assist. Only concern with this technique is of gate reliability due to
overdrive created by negative voltage especially at higher voltages. Hence we need to either restrict this technique
for low voltage operation or verify gate oxide reliability at highest voltage of operation.
Fig. 4. Negative bit line circuit.
10312 Pulla Reddy A et al./ Materials Today: Proceedings 4 (2017) 10309–10314
Fig. 4 shows the negative bit line technique for expanding the write margin. Making use of a self-determining
circuitry as for the BL and /BL, it is essential to adjust the timing of forcing one of them to a negative bias.
Furthermore, excessive negative bias causes a data-flip in unselected cells on the selected column, so we should be
careful in designing the boost capacitance in this circuitry. Other problem with this assist technique is, if the
negative boost level is high then it leads to device reliability issue. The advantage of negative bias technique over
the VDD suppression technique [1,2] is that the increase of gate-source bias of the access-transistor (M5,M6) is
more effective for write margin than decrease of the drain-source bias of the load-PMOS transistor. Negative bit line
voltage is generated by coupling the bit line capacitance with a MOS device capacitance.
2.2. Word line (WL) boost write assist
WL boost assist technique helps to strengthen the pass gate transistor thereby improves WM during write event
as shown in Fig. 3. The boost voltage can be routed as a separate power supply or it can be generated internally by a
charge pump [8] or by capacitive coupling [9].The word-line boosting technique works on a row based. Hence all
the half-selected cells in a row are more prone to an upset due to reduction in their dynamic read noise margins. The
disadvantage of this assist techniques is degrades the stability of the cell.
2.3. Cell VDD collapse write assist
This write assist technique works on the base of reducing the cell VDD shown in the Fig. 3. This tends to weaken
the pull-up device with respect to the access transistor device. Once the pull-up device is weakened, it is easy to
write new data to the bit cell. It increases the write-ability of the cell. The primary challenge with this technique is to
make certain that the lowered column voltage is even more eminent than the retention voltage of the unselected bit
cells in the same column. To simplify the implementation, sometime the voltage supply of the whole array is
lowered during the write operation. However, this decreases the dynamic read noise margin of the half-selected bit
cells. Cell VDD collapsed by discharging the VDD supply. The main disadvantage of this assist techniques is it
violates the data retention voltage of un-accessed SRAMs in the same column.
2.4. Cell GND boost write assist
The raised ground assist scheme is another way to improve the write-ability of SRAM operation. This write assist
technique reduces the risk of data retention failure. This technique is also weaken the pull-up PMOS but in this
technique it is done by weakening the PMOS gate voltage instead of the source voltage as compared to cell VDD
collapse scheme. This extra ground voltage can be routed as a separate ground or can be generated internally using a
regulator. Cell GND level boosted using a NMOS diode on VSS node.
This assist scheme also impacts the dynamic read noise margin of half-selected bit cells, if implemented globally
for the whole array.
3. Stability Analysis
The traditional method of quantifying SRAM cell stability is based on measuring the static noise margin (SNM)
of the cross-coupled inverters in a memory cell. The static noise margin is a measure of the maximum amount of
noise voltage that can be tolerated at the cross-coupled inverter nodes without flipping the cell.
The investigation of SNM is done in two modes i.e. hold and read mode. Hold mode measurement is called as
Hold static noise margin and read mode measurement is called as read static noise margin (RSNM). Different
methods are used to find the SNM of the SRAM cell. The most commonly used SNM measurement is the simulation
method and second method is the graphical method where voltage transfer (VTC) characteristics of the SRAM cell
inverters are used to find the maximum size of square that fit in the VTC curves.
There are various read assist techniques are proposed to improve the readability of the SRAM cell. Some of these
assist circuits are reduced WL voltage, negative VSS, raised cell VDD.
Pulla Reddy A et al./ Materials Today: Proceedings 4 (2017) 10309–10314 10313
3.1. Boosted cell VDD as read assist technique
For readability, Pass gate and pull down devices should be strong enough. VDD boost improves the strength of
the pull down transistor and thus sufficiently improves RNM/SNM in read or standby mode. But, VDD boost
degrades WM during write mode. So, VDD boost should not be done for the selected columns during write. Cell
VDD boosted by using a charge pump.
3.2. Reduced word line voltage as read assist circuit
During write operation the half-selected cells on selected WL will be in read mode. Reducing WL voltage helps
SNM but it degrades WM for the selected bit cells. Word line voltage is reduced by a Vt drop using an NMOS
device.
3.3. Negative VSS technique
Reducing GND below ground level improves readability [10]. Negative GND is the most effective of all
readability assist techniques as it increases the Vgs on both the PD and PG by pulling the internal node holding ‘0’
below ground. Unfortunately, this technique has a very high energy cost for memory arrays, because GND lines
have large capacitance. Negative VSS level achieved by coupling capacitance method.
4. Comparison of Various Assist Techniques
4.1. Comparison of various write assist techniques
4.1.1. Word line boost assist technique
Advantages: 1.Performance improvement by virtue of increased IDSAT. 2. Significant improvement in WM and
Lesser Power consumption. 3. Less area penalty. 4. Easy to implement.
Disadvantages: 1.Read disturb to half selected bit cells makes it not suitable for Mux > 1
4.1.2. Negative bit line voltage (NBL) assist technique
Advantages: 1.Significant Write time and write-ability improvement. 2. Suited for all type of memories (single
port and dual port).
Disadvantages: 1.Increased overdrive causes reliability impact. 2. All selected bit lines need to bring low hence
more power is burned. 3. High SRAM compiler effort as boost size need. 4. To be changed with number of rows 5.
Boost capacitor takes significant area.
4.1.3. Cell VDD lowering assist technique
Advantages: 1. Write margin improves but remains less effective than NBL. 2. Lesser area overhead.
Disadvantages: 1. Need more WL window, it penalizes write timing and power. 2. Retention noise margin
degradation for unselected rows and selected column bit cells. 3. Higher Power as VDD cap is much more compared
to NBL Increased write time hence performance penalty.
4.1.4. Cell GND boost assist technique
Advantages: 1.Write margin improvement but remains less effective than NBL.
10314 Pulla Reddy A et al./ Materials Today: Proceedings 4 (2017) 10309–10314
Disadvantages: 1.Not practically possible to implement because of shared VSS across the rows. 2. Much higher
Power as the bit cell current flow through VSS so, there is a continuous DC current. 3. Increased write time hence
performance penalty.
4.2. Comparison of various read assist techniques
Various read assist techniques are compared with their advantages and disadvantages as shown in table1.
Table 1. Comparison of read assist techniques
Assist Techniques Advantages Dis-advantages
Boosted Cell VDD Improves SNM Impacts WM , More power
Reduced Word line Voltage SNM improvement Degrades WM during write
operation
Negative VSS Improves SNM Impacts power consumption
4.3. Effect of assist techniques on PVT
Worst case WM is at lower WL voltage (VDD), lower temperature, slow NMOS and fast PMOS case.
Worst case SNM is at lower supply voltage (VDD), higher temperature, fast NMOS and slow PMOS case.
5. Conclusion
In this paper we analysed the various write and read assist techniques with their impact on the write-ability,
readability and stability of the SRAM memory cell. Out of the discussed write assist techniques negative bit line
voltage (NBL) technique gives the best write margin compared to other techniques. To improve the SRAM cell
stability we discussed various read assist techniques. The impact of the PVT variation on SRAM cell is also
analysed at various process voltage and temperature values. Finally we conclude that by using these assist circuits,
write margin and read margin of the SRAM bit cell will be improved.
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