UNIT 5: VHDL

The Concept of Programmable Logic Devices

Programmable logic devices (PLDs) were introduced in the mid 1970s. The idea was to construct
combinational logic circuits that were programmable.
The first PLDs were called PAL (programmable array logic) or PLA (programmable logic array)

1. PAL Devices
PAL (programmable array logic) chips were introduced by Monolithic Memories in the mid 1970s.
Its basic architecture is illustrated in Figure 18.2, where the little ovals represent programmable
connections. As can be seen, the circuit is composed of a programmable array of AND gates
followed by a fixed array of OR gates. This implementation is based on the fact that any
combinational function can be represented by a sum-of-products (SOP)
A PAL-based example is depicted in Figure 18.3, which computes the combinational functions

The dark ovals indicate a connection. The outputs of nonprogrammed AND gates are set to zero.

2. PLA Devices
PLA (programmable logic array) chips were introduced in the mid 1970s by Signetics. The basic
architecture of a PLA is illustrated in Figure 18.4. Comparing it to that in Figure 18.2, we observe
that the only fundamental difference between them is that while a PAL has programmable AND
connections and fi xed OR connections, both are programmable in a PLA. The obvious advantage
is greater flexibility because more combinational functions (more product terms) can be
implemented with the same amount of hardware. On the other hand, the extra propagation delay
introduced by the additional programmable interconnections lowered their speed.
The technology then employed in the fabrication of PLAs was the same as that of PALs

CPLDs
A Complex Programmable Logic Device (CPLD) is a digital integrated circuit that can be
programmed to implement a variety of digital logic functions. CPLDs are used in a wide range of
applications, including system control, signal processing, and interface management.
1. Programmable Logic Unit
The role is the same as the basic I/O port of FPGA, but the application scope of CPLD is more
limited, and the performance and complexity of I/O has a certain gap compared with FPGA, and
the I/O standard supported is less, and the frequency is also lower.

2. Basic logic unit

The basic logic unit in CPLD is macro unit. The so-called macro unit is composed of some with
or arrays plus flip-flops, in which the "with or" array completes the combined logic function, and
the flip-flops are used to complete the timing logic.
Another important concept related to the basic logic unit of CPLD is the product term. The so-
called product term is the output of the macro cell with the array, and its number marks the CPLD
capacity. Multiplication term array is actually an "with or" array, each intersection is a
programmable fuse, if the conductor is to achieve "with" logic, in the "with" array after the general
There is also an "or" array, which is used to complete the "or" relationship in the minimum logic
expression.

3. Wiring pool and wiring matrix

The wiring resources in CPLD are much simpler than those in FPGA, and the wiring resources are
relatively limited, so the centralized wiring pool structure is generally used. The so-called wiring
pool is essentially a switching matrix, and the connection between input and output items of
different macrocells can be completed by tying junctions. Due to the lack of interconnection
resources inside CPLD devices, certain difficulties are encountered in wiring the devices in some
cases. Since the wiring pool structure of CPLD is fixed, the delay from the input pin to the output
pin of CPLD is fixed, which is called Pin to Pin delay and expressed by Tpd. The Tpd delay reflects
the highest frequency that can be achieved by the CPLD device, which clearly indicates the speed
level of the CPLD device.

FPGAs
Field programmable gate array (FPGA)
FPGA consists of 6 parts, which are programmable input/output unit, basic programmable logic
unit, embedded block RAM, rich wiring resources, underlying embedded functional unit and
embedded dedicated hard core.
1. Programmable Input/Output Unit (IOB)
The programmable I/O unit is the interface part between the chip and the external circuit, which
fulfills the requirements of driving and matching the input/output signals under different electrical
characteristics. the I/Os inside the FPGA are classified by groups, and each group can support
different I/O standards independently. Through flexible software configuration, it can adapt to
different electrical standards and I/O physical characteristics, adjust matching impedance
characteristics, change pull-up and pull-down resistors, and adjust the magnitude of drive current.
The external input signal can be input to the internal of FPGA through the memory cell of IOB
module, or directly input to the internal of FPGA. When the external input signal is input to the
internal of FPGA through the memory cell of IOB module, its hold time (Hold Time) requirement
can be reduced and usually defaulted to 0.

2. Basic Programmable Logic Unit (BPLU)

The basic programmable logic unit of FPGA is composed of a lookup table (LUT) and a register
(Register), the lookup table completes the pure combinational logic function. the internal register
of FPGA can be configured as a flip-flop with synchronous/asynchronous reset and reset, clock
enable, or as a latch. the FPGA generally relies on the register to complete the synchronous timing
logic design. In general, the more classical configuration of the basic programmable unit is a
register plus a lookup table, but the internal structure of registers and lookup tables varies
somewhat from vendor to vendor, and the combination pattern of registers and lookup tables also
varies.
An important implication of understanding the LUT and Register ratio of the underlying
configuration unit is in device selection and sizing estimation. Since there are embedded RAM,
PLL or DLL, dedicated Hard IP Core, etc. inside the FPGA in addition to the basic programmable
logic unit, these modules can also equate to a certain size of system gate, so a simple scientific
method is to measure the number of Register or LUT of the device.

3. Embedded block RAM

Most FPGAs today have embedded block RAM. embedded block RAM can be configured as
single-port RAM, dual-port RAM, content address memory (CAM), and FIFO and other common
storage structures.
CAM, or content address memory. Data written to the CAM is compared to each of its internal
stores and returns the address of all internal data that is the same as the port data. Simply put, RAM
is a write address, read data storage unit; CAM is the exact opposite of RAM.
In addition to block RAM, Xilinx and Lattice FPGAs have the flexibility to configure the LUT
into RAM, ROM, FIFO and other storage structures.

4. Rich Wiring Resources

Cabling resources connect all units inside the FPGA, and the length and process of the wires
determine how well the signals can be driven and how fast they can be transmitted across the wires.
They are divided into four different categories according to the process, length, width and
distribution location.
Global dedicated wiring resources: used to complete the wiring of the global clock and global
reset/set within the chip.
Long-wire resources: used to complete the wiring of some high-speed signals and some second
global clock signals between device banks.
Short-line resources: used to complete the logic interconnection and wiring between the basic logic
cells.
5. Underlying embedded functional units
Embedded functional modules mainly refer to soft processing cores (Soft Core) such as DLL
(Delay Locked Loop), PLL (Phase Locked Loop), DSP and CPU. Nowadays, more and more
abundant embedded functional units make monolithic FPGAs become system-level design tools,
making them capable of joint software and hardware design and gradually transitioning to SOC
platforms.
DLLs and PLLs have similar functions and can perform clock multiplication and division with
high accuracy and low jitter, as well as duty cycle adjustment and shift etc. DLLs are integrated
on chips from Xilinx, PLLs are integrated on chips from Altera, and both PLLs and DLLs are
integrated on new chips from Lattice. PLLs and DLLs can be easily managed and configured
through IP core generation tools.

Introduction to VHDL: Behavioral – data flow, and algorithmic and structural

description
VHDL is a technology and vendor independent hardware description language.
Its main applications include synthesis of digital circuits onto CPLD/FPGA chips.
VHDL stands for Very High Speed Integrated Circuit hardware description language.

Code Structure
1. Library declarations
The std library contains definitions for the standard data types (BIT, BOOLEAN, INTEGER,
BIT, BIT_VECTOR, etc.), plus information for text and fi le handling,
As illustrated below.
LIBRARY ieee;
USE ieee.std_logic_1164.all;

2. Entity
Entity is a list with specifi cations of all I/O ports of the circuit under design. It also allows generic
parameters to be declared, as well as several other declarations, subprogram bodies, and concurrent
statements. Its syntax is shown below.
ENTITY entity_name IS
GENERIC (constant_name: constant_type := constant_value; constant_name:
constant_type := constant_value; ...);
PORT (port_name: signal_mode signal_type; port_name: signal_mode signal_type;
...); [declarative part]
[BEGIN]
[statement part]
END entity_name;

3. Architecture
This part contains the code proper (the intended circuit’s structural or behavioral description). It
can be concurrent or sequential. The former is adequate for the design of combinational circuits,
while the latter can be used for sequential as well as combinational circuits. Its syntax is shown
below.
ARCHITECTURE architecture_name OF entity_name IS
[declarative part]
BEGIN
(code)
END architecture_name;

• Declarative part: Can contain the same items as the entity’s declarative part, plus
COMPONENT and CONFIGURATION declarations.
• Code: Can be concurrent, sequential, or mixed. To be sequential, the statements must be
placed
inside a PROCESS.

Data Types
The predefined data types are from the libraries/packages listed above. Those that are synthesizable
are listed in Figure 19.4, which shows their names, library/package of origin, and synthesizable
values.
 1. Operators
VHDL provides a series of operators that are divided into the six categories below.

a. Assignment operators
"<=", ":=", "=>" "<=" Used to assign values to signals.
":=" Used to assign values to variables, constants, or initial values.
"=>" Used with the keyword OTHERS to assign values to arrays.
Examples:
sig1 <= '1';
--assignment to a single-bit signal
sig2 <= "00001111";
--assignment to a multibit signal
sig3 <= (OTHERS =>'0');
--result is sig3<= "00...0"
VARIABLE var1:
--assignment of initial value
INTEGER := 0;
--assignment to a multibit variable
var2 := "0101";

b. Concatenation operators
"&" and "," These operators are employed to group values.
Example: The assignments to x, y, and z below are equivalent.
k: CONSTANT BIT_VECTOR(1 TO 4) := "1100";
x <= ('Z', k(2 TO 3), "11111"); -- result: x <= "Z1011111"
y <= 'Z' & k(2 TO 3) & "11111"; -- result: y <= "Z1011111"
z <= (7 =>'Z', 5=>'0', OTHERS=> '1'); -- result: z < ="Z1011111"
 c. Logical operators
NOT, AND, NAND, OR, NOR, XOR, XNOR
The only logical operator with precedence over the others is NOT.
Examples:
x <= a NAND b;
-- result: x = (a.b)'
y <= NOT(a AND
-- result: same as above
b);
-- result: x = a'. b
z <= NOT a AND b;

d. Arithmetic operators
+, –, *, /, **, ABS, REM, MOD
These are the classical operators: addition, subtraction, multiplication, division, exponentiation,
absolute-value, remainder, and modulo. They are also summarized in Figure 19.5 along with the
allowed data types.
Examples:
x <= (a + b)**N;
y <= ABS(a) + ABS(b);
z <= a/(a + b);

e. Shift operators
SLL, SRL, SLA, SRA, ROL, ROR
Shift operators are shown in Figure 19.5 along with the allowed data types. Their meanings are
described below.
SLL (shift left logical): Data are shifted to the left with '0's in the empty positions.
SRL (shift right logical): Data are shifted to the right with '0's in the empty positions.
SLA (shift left arithmetic): Data are shifted to the left with the rightmost bit in the empty positions.
SRA (shift right arithmetic): Data are shifted to the right with the leftmost bit in the empty
positions.
ROL (rotate left): Circular shift to the left.
ROR (rotate right): Circular shift to the right.
Examples:
a <= "11001";
x <= a SLL 2; --result: x <= "00100"
y <= a SLA 2; --result: y <= "00111"
 z <= a SLL –3; --result: z <= "00011"

f. Comparison operators
=, /=, >, <, >=, <=
Comparison operators are also shown in Figure 19.5 along with the allowed data types.
Example:
IF a >= b THEN x <= '1';

Attributes
The main purposes of VHDL attributes are to allow the construction of generic (fl exible) codes as
well as event-driven codes. They also serve for communicating with the synthesis tool to modify
synthesis directives.
The predefined VHDL attributes can be divided into the following three categories:
(i) range related
(ii) position related, and
(iii) event related.

(i) Range-related attributes

Return parameters regarding the range of a data array.
Example:
For the signal x specifi ed below, the range-related attributes return the values listed subsequently
(note that m > n).
SIGNAL x: BIT_VECTOR(m DOWNTO n);
x'LOW → n
x'HIGH → m
x'LEFT → m
x'RIGHT → n
x'LENGTH → m–n+1
x'RANGE → m DOWNTO n
x'REVERSE_RANGE → n TO m
x'ASCENDING → FALSE (because the range of x is descending)

(ii) Position-related attributes

Return positional information regarding enumerated data types.
For example, x'POS(value) returns the position of the specifi ed value, while x'VAL(position)
returns the value in the specifi ed position.
(iii) Event-related attributes
Employed for monitoring signal changes (like clock transitions). The most common of these is
x'EVENT, which returns TRUE when an event (positive or negative edge) occurs in x.

Logic Design - VHDL Behavioral, Dataflow and Structural Models

1. Behavioral Description Model:

In this Model we follow the Truth Table of a Circuit. So, we will have a if or case statement
inside of a process or a when-else, with-select statement for each output inside of the
architecture.
a Behavioral Description of a NAND Gate
library ieee;
use ieee.std_logic_1164.all;
entity nand is
port(
a, b: in std_logic;
c: out std_logic
);
end nand;
architecture arch of nand is
begin
process(a, b)
begin
if a='1' and b='1' then
c <= '0';
else
c <= '1';
end if;
end process;
end arch;

2. Dataflow Description Model:

A Dataflow Description is based on Boolean Functions/Expressions for each Output. So, we
will simply assign the Outputs directly having the Inputs inside of Expressions that give us the
Output values directly.

a ANDGate example in Dataflow Description Model

library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port(
a, b: in std_logic;
d: out std_logic
);
end and_gate;
architecture arch of and_gate is
begin
d <= a and b;
end arch;

3. Structural Description Model

The most descriptive Model is the Structural Description. To use this Model we need to know
the Structure/Gating of the Circuit. We will have to write a VHDL Description for all the Gates
and Sub-Circuits that the Structural Model Circuit contains. All this Circuits will be used
as Components.

Example 1:
The Circuit looks like this: implement all the above three models for given circuit.
Then the Karnaugh Map and Function look like this:

Using those 3 Things we can then write down the 3 Models like that:

Behavioral:
library ieee;
use ieee.std_logic_1164.all;
entity c_behavioral is
port(
A, B, C: in std_logic;
Y: out std_logic
);
end c_behavioral;

architecture arch of c_behavioral is

begin
process(A, B, C)
begin
if (C='0') then
Y <= '0';
elsif (A='1' and B='1') then
Y <= '0';
else
Y <= '1';
end if;
end process;
end arch;

Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity c_dataflow is
port(
A, B, C: in std_logic;
Y: out std_logic
);
end c_dataflow;

architecture arch of c_dataflow is

signal not_a: std_logic;
signal not_b: std_logic;
begin
not_a <= not A;
not_b <= not B;
Y <= (not_a and C) or (not_b and c);
end arch;

Structural:
library ieee;
use ieee.std_logic_1164.all;
entity c_structural is
port(
A, B, C: in std_logic;
 Y: out std_logic
);
end c_structural;

architecture arch of c_structural is

component not_gate
port(
a: in std_logic;
b: out std_logic
);
end component;

component or2_gate
port(
a, b: in std_logic;
c: out std_logic
);
end component;

component and2_gate
port(
a, b: in std_logic;
c: out std_logic
);
end component;

signal and1_to_or1: std_logic;

signal not1_to_or1: std_logic;
signal or1_to_not2: std_logic;

begin

and1: and2_gate port map(A, B, and1_to_or1);

not1: not_gate port map(C, not1_to_or1);
or1: or2_gate port map(and1_to_or1, not1_to_or1, or1_to_not2);
not2: not_gate port map(or1_to_not2, Y);
end arch;

Examples
1. VHDL Code for AND gate

library IEEE;
use IEEE.std_logic_1164.all;
---------------------------------- Entity Declarations -------------------------
entity andgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic );
end andgate;
architecture Behavioral of andgate is
begin
Y<= A and B ;
end Behavioral;
 2. VHDL Code for OR gate

-- Header file declaration

library IEEE;
use IEEE.std_logic_1164.all;

-- Entity declaration

entity orGate is
port(A : in std_logic; -- OR gate input
B : in std_logic; -- OR gate input
Y : out std_logic); -- OR gate output
end orGate;

architecture Behavioral of orGate is

begin
Y <= A OR B;
end Behavioral;

3. VHDL Code for NOT gate

-- Header file declaration

library IEEE;
use IEEE.std_logic_1164.all;

-- Entity declaration

entity notGate is
port(A : in std_logic; -- NOT gate input
Y : out std_logic); -- NOT gate output
end notGate;

architecture Behavioral of notGate is

begin
Y <= NOT A;
end Behavioral;
Write a VHDL program for the 8 :1 Multiplexer

library IEEE;
use IEEE.std_logic_1164.all;
---------------------------------- Entity Declarations -------------------------
entity mux8_1 is
port ( D: in STD_LOGIC_VECTOR (7 downto 0);
EN: in STD_LOGIC;
SEL: in STD_LOGIC_VECTOR (2 downto 0);
Y: out STD_LOGIC );
end mux8_1;
architecture mux8_1_arch of mux8_1 is
begin
process(EN,SEL,D)
begin
 if(EN='1')then
y<='0';
else
case SEL is
when "000" => y <= D(0);
when "001" => y <= D(1);
when "010" => y <= D(2);
when "011" => y <= D(3);
when "100" => y <= D(4);
when "101" => y <= D(5);
when "110" => y <= D(6);
when others=> y <= D(7);
end case;
end if;
end process;
end mux8_1_arch;

VHDL code for ‘1’ bit comparator

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
---------------------------------- Entity Declarations -------------------------
entity bitcomp is
port ( A: in STD_LOGIC;
B: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR(1 DOWNTO 0);
 Y: out BOOLEAN );
end bitcomp;

architecture bitcomp_arch of bitcomp is

begin
process(A,B,sel)
begin
case sel is
when "00" => y <= A=B;
when "01" => y <= A>B;
when "10" => y <= A y <= FALSE ;
end case;
end process;
end bitcomp_arch;

Classification and characteristics of memories (do your own)

RAM, ROM, EPROM, EEPROM, NVRAM, SRAM, DRAM