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Lecture-7

The document discusses dynamic logic circuits, specifically focusing on read-only memory (ROM) arrays and their implementations using NOR and NAND gates. It explains how binary information is stored in ROM through the presence or absence of data paths and details the design of row and column decoders for selecting word lines. Examples of 4-bit x4-bit NOR and NAND-based ROM arrays, along with a simple row address decoder, are provided to illustrate the concepts.

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2 views

Lecture-7

The document discusses dynamic logic circuits, specifically focusing on read-only memory (ROM) arrays and their implementations using NOR and NAND gates. It explains how binary information is stored in ROM through the presence or absence of data paths and details the design of row and column decoders for selecting word lines. Examples of 4-bit x4-bit NOR and NAND-based ROM arrays, along with a simple row address decoder, are provided to illustrate the concepts.

Uploaded by

tnagalaxmi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIT 4:

Dynamic logic circuits


ROM
• The read-only memory array can also be seen as a simple combinational
Boolean network which produces a specified output value for each input
combination,i.e., for each address.

• Storing binary information at a particular address location can be achieved


by the presence or absence of a data path from the selected row (word
line) to the selected column (bit line), which is equivalent to the presence
or absence of a device at that particular location.

• In the following, we will examine two different implementations for


MOS ROM arrays.

• In fig. the 4-bit x4-bit memory array is shown. Here, each column consists
of a pseudo-nMOS NOR gate driven by some of the row signals, i.e., the
word lines.
Example of a 4-bit x 4-bit NOR-based
ROM array
A 4-bit x 4-bit NAND-based ROM array.
Design of Row and Column Decoders
• A row decoder designed to drive a NOR ROM
array must, by definition, select one of the
2^N word lines by raising its voltage to VOH.

• As an example,consider the simple row


address decoder shown in Fig, which decodes
a two-bit row address and selects one out of
four word lines by raising its level.
Fig. Row address decoder example for 2 address bits and 4
word lines
• A most straightforward implementation of this
decoder is another NOR array, consisting of 4
rows (outputs) and 4 columns (two address bits
and their complements).
• NOR-based decoder array can be built just like
the NOR ROM array, using the same selective
programming approach.
• The ROM array and its row decoder can thus be
fabricated as two adjacent NOR arrays, as shown
in Fig. 10.12.
NOR-based row decoder circuit for 2
address bits and 4 word lines.

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