SN65HVD230Q-Q1

SN65HVD231Q-Q1
SN65HVD232Q-Q1

SGLS398A − APRIL 2002 − REVISED APRIL 2008

3.3-V CAN TRANSCEIVERS

FEATURES D Thermal Shutdown Protection

D Qualified for Automotive Applications D Open-Circuit Fail-Safe Design
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V SN65HVD230QD
Using Machine Model (C = 200 pF, R = 0) SN65HVD231QD

D Operates With a 3.3-V Supply (TOP VIEW)

D Low Power Replacement for the PCA82C250 D 1 8 RS

Footprint GND 2 7 CANH
D Bus/Pin ESD Protection Exceeds 15-kV HBM VCC 3 6 CANL
R
D Controlled Driver Output Transition Times for 4 5 Vref
Improved Signal Quality on the SN65HVD230Q
and SN65HVD231Q
D Unpowered Node Does Not Disturb the Bus SN65HVD232QD

D Compatible With the Requirements of the (TOP VIEW)

ISO 11898 Standard D 1 8 NC
D Low-Current SN65HVD230Q Standby Mode GND 2 7 CANH
370 µA Typical VCC 3 6 CANL
D Low-Current SN65HVD231Q Sleep Mode R 4 5 NC
0.1 µA Typical
NC − No internal connection
D Designed for Signaling Rates‡ Up To
1 Megabit/Second (Mbps)

logic diagram (positive logic)

SN65HVD230Q, SN65HVD231Q SN65HVD232Q
Logic Diagram (Positive Logic) Logic Diagram (Positive Logic)

3 5
VCC Vref
1
D
1
D
7
4 CANH
8 R
RS 6
CANL
7
4 CANH
R 6
CANL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

‡ The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

PRODUCTION DATA information is current as of publication date. Copyright  2008, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

DESCRIPTION
The SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q controller area network (CAN) transceivers are
designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers, or with
equivalent devices. They are intended for use in applications employing the CAN serial communication physical
layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential
transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
Designed for operation in especially-harsh environments, these devices feature cross-wire protection,
loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range.
The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications. It operates over a –2-V to 7-V common-mode range on the
bus, and it can withstand common-mode transients of ± 25 V.
On the SN65HVD230Q and SN65HVD231Q, RS (pin 8) provides three different modes of operation:
high-speed, slope control, and low-power modes. The high-speed mode of operation is selected by connecting
pin 8 to ground, allowing the transmitter output transistors to switch on and off as fast as possible with no
limitation on the rise and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground
at pin 8, since the slope is proportional to the pin’s output current. This slope control is implemented with external
resistor values of 10 kΩ, to achieve a 15-V/µs slew rate, to 100 kΩ, to achieve a 2-V/µs slew rate.
The circuit of the SN65HVD230Q enters a low-current standby mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to RS (pin 8). The DSP controller reverses this
low-current standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
The unique difference between the SN65HVD230Q and the SN65HVD231Q is that both the driver and the
receiver are switched off in the SN65HVD231Q when a high logic level is applied to RS (pin 8) and remain in
this sleep mode until the circuit is reactivated by a low logic level on RS.
The Vref (pin 5 on the SN65HVD230Q and SN65HVD231Q) is available as a VCC/2 voltage reference.
The SN65HVD232Q is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection.

AVAILABLE OPTIONS{}
FUNCTION LOW INTEGRATED SLOPE
Vref PIN
NUMBER POWER MODE CONTROL
’230 370-µA standby mode Yes Yes
’231 10-µA sleep mode Yes Yes
’232 No standby or sleep mode No No

PART NUMBER Q100 TA MARKED AS:

SN65HVD230QD No HV230Q
−40°C
40°C to
t
SN65HVD231QD No HV231Q
125°C
SN65HVD232QD No HV232Q
SN65HVD230QDQ1 Yes 230Q1
−40°C
40°C to
t
SN65HVD231QDQ1 Yes 231Q1
125°C
SN65HVD232QDQ1 Yes 232Q1
† For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at
http://www.ti.com/packaging.
The D package is available taped and reeled. Add the suffix R to device type (e.g.,
SN65HVD230QDRQ1).

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

Function Tables
DRIVER (SN65HVD230Q, SN65HVD231Q)
OUTPUTS
INPUT D RS BUS STATE
CANH CANL
L H L Dominant
V(Rs) < 1.2
12V
H Z Z Recessive
Open X Z Z Recessive
X V(Rs) > 0.75 VCC Z Z Recessive
H = high level; L = low level; X = irrelevant; ? = indeterminate
DRIVER (SN65HVD232Q)
OUTPUTS
INPUT D BUS STATE
CANH CANL
L H L Dominant
H Z Z Recessive
Open Z Z Recessive
H = high level; L = low level
RECEIVER (SN65HVD230Q)
DIFFERENTIAL INPUTS RS OUTPUT R
VID ≥ 0.9 V X L
0.5 V < VID < 0.9 V X ?
VID ≤ 0.5 V X H
Open X H
H = high level; L = low level; X = irrelevant; ? = indeterminate
RECEIVER (SN65HVD231Q)
DIFFERENTIAL INPUTS RS OUTPUT R
VID ≥ 0.9 V L
0.5 V < VID < 0.9 V V(Rs) < 1.2 V ?
VID ≤ 0.5 V H
X V(Rs) > 0.75 VCC H
X 1.2 V < V(Rs) < 0.75 VCC ?
Open X H
H = high level; L = low level; X = irrelevant; ? = indeterminate
RECEIVER (SN65HVD232Q)
DIFFERENTIAL INPUTS OUTPUT R
VID ≥ 0.9 V L
0.5 V < VID < 0.9 V ?
VID ≤ 0.5 V H
Open H
H = high level; L = low level; X = irrelevant; ? = indeterminate

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SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

Function Tables (Continued)

TRANSCEIVER MODES (SN65HVD230Q, SN65HVD231Q)
V(Rs) OPERATING MODE
V(RS) > 0.75 VCC Standby
10 kΩ to 100 kΩ to ground Slope control
V(RS) < 1 V High speed (no slope control)

Terminal Functions
SN65HVD230Q, SN65HVD231Q
TERMINAL
DESCRIPTION
NAME NO.
CANL 6 Low bus output
CANH 7 High bus output
D 1 Driver input
GND 2 Ground
R 4 Receiver output
RS 8 Standby/slope control
VCC 3 Supply voltage
Vref 5 Reference output

SN65HVD232Q
TERMINAL
DESCRIPTION
NAME NO.
CANL 6 Low bus output
CANH 7 High bus output
D 1 Driver input
GND 2 Ground
NC 5, 8 No connection
R 4 Receiver output
VCC 3 Supply voltage

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

equivalent input and output schematic diagrams

CANH and CANL Inputs D Input

VCC

VCC
16 V 110 kΩ 9 kΩ
100 kΩ
45 kΩ
Input 1 kΩ
Input

20 V 9 kΩ
9V

CANH and CANL Outputs R Output

VCC
VCC

16 V

5Ω
Output Output

9V
20 V

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SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise
noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Voltage range at any bus terminal (CANH or CANL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7 V to 16 V
Voltage input range, transient pulse, CANH and CANL, through 100 Ω (see Figure 7) . . . . . . . . . . . . −25 V to 25 V
Input voltage range, VI (D or R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Electrostatic discharge: Human body model (see Note 2) CANH, CANL and GND . . . . . . . . . . . . . . . . . . 15 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 kV
Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR‡ TA = 70°C TA = 85°C TA = 125°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

recommended operating conditions

PARAMETER MIN NOM MAX UNIT
Supply voltage, VCC 3 3.6 V
Voltage at any bus terminal (common mode) VIC −2§ 7 V
Voltage at any bus terminal (separately) VI −2.5 7.5 V
High-level input voltage, VIH D, R 2 V
Low-level input voltage, VIL D, R 0.8 V
Differential input voltage, VID (see Figure 5) −6 6 V
V(RS) 0 VCC V
V(RS) for standby or sleep 0.75 VCC VCC V
Rs wave-shaping resistance 0 100 kΩ
Driver −40
High level output current
High-level current, IOH mA
Receiver −8
Driver 48
Low level output current
Low-level current, IOL mA
Receiver 8
Operating free-air temperature, TA −40 125 °C
§ The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT

VI = 0 V, CANH 2.45 VCC

VOH Dominant See Figure 1 and Figure 3
Bus output CANL 0.5 1.25
voltage V
VI = 3 V, CANH 2.3
VOL Recessive See Figure 1 and Figure 3 CANL 2.3
VI = 0 V, See Figure 1 1.5 2 3
VOD(D) Dominant V
Differential output VI = 0 V, See Figure 2 1.2 2 3
voltage VI = 3 V, See Figure 1 −120 0 12 mV
VOD(R) Recessive
VI = 3 V, No load −0.5 −0.2 0.05 V
IIH High-level input current VI = 2 V −30 µA
IIL Low-level input current VI = 0.8 V −30 µA
VCANH = −2 V −250 250
IOS Short circuit output current
Short-circuit mA
VCANL = 7 V −250 250
Co Output capacitance See receiver
Standby SN65HVD230Q 370 600
V(RS) = VCC µA
A
Sleep SN65HVD231Q 0.1
ICC Supply current
Dominant VI = 0 V, No load Dominant 10 17
All devices mA
Recessive VI = VCC , No load Recessive 10 17
† All typical values are at 25°C and with a 3.3-V supply.

driver switching characteristics at TA = 25°C (unless otherwise noted)

SN65HVD230Q and SN65HVD231Q
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(RS) = 0 V 35 85
tPLH Propagation delay time, low
low-to-high-level
to high level output RS with 10 kΩ to ground 70 125 ns
RS with 100 kΩ to ground 500 870
V(RS) = 0 V 70 120
tPHL Propagation delay time, high
high-to-low-level
to low level output RS with 10 kΩ to ground 130 180 ns
RS with 100 kΩ to ground 870 1200
V(RS) = 0 V 35
RS with 10 kΩ to ground CL = 50 pF, 60
tsk(p) Pulse skew (|tP(HL) − tP(LH)|) ns
See Figure 4
RS with 100 kΩ to ground 370
tr Differential output signal rise time 25 50 100 ns
V(RS) = 0 V
tf Differential output signal fall time 40 55 80 ns
tr Differential output signal rise time 80 120 160 ns
RS with 10 kΩ to ground
tf Differential output signal fall time 80 125 150 ns
tr Differential output signal rise time 600 800 1200 ns
RS with 100 kΩ to ground
tf Differential output signal fall time 600 825 1000 ns

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SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

driver switching characteristics at TA = 25°C (unless otherwise noted)

SN65HVD232Q
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 35 85 ns
tPHL Propagation delay time, high-to-low-level output 70 120 ns
tsk(p) Pulse skew (|tP(HL) − tP(LH)|) CL = 50 pF, See Figure 4 35 ns
tr Differential output signal rise time 25 50 100 ns
tf Differential output signal fall time 40 55 80 ns

receiver electrical characteristics over recommended operating conditions (unless otherwise

noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIT+ Positive-going input threshold voltage 750 900 mV
See Table 1
VIT− Negative-going input threshold voltage 500 650
mV
Vhys Hysteresis voltage (VIT+ − VIT−) 100
−6 V ≤ VID ≤ 500 mV, IO = −8 mA, See Figure 5
VOH High-level output voltage 2.4
V
VOL Low-level output voltage 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 0.4
VIH = 7 V 100 250
µA
A
VIH = 7 V, VCC = 0 V Other input at 0 V, 100 350
II Bus input current
VIH = −2 V D=3V −200 −30
µA
A
VIH = −2 V, VCC = 0 V −100 −20
Pin-to-ground, V(D) = 3 V,
Ci CANH, CANL input capacitance 32 pF
VI = 0.4 sin(4E6πt) + 0.5 V
Pin-to-pin, V(D) = 3 V,
Cdiff Differential input capacitance 16 pF
VI = 0.4 sin(4E6πt) + 0.5 V
Rdiff Differential input resistance Pin-to-pin, V(D) = 3 V 40 70 100 kΩ
RT CANH, CANL input resistance 20 35 50 kΩ
ICC Supply current See driver
† All typical values are at 25°C and with a 3.3-V supply.

receiver switching characteristics at TA = 25°C (unless otherwise noted)

TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
tPLH Propagation delay time, low-to-high-level output 35 50 ns
tPHL Propagation delay time, high-to-low-level output See Figure 6 35 50 ns
tsk(p) Pulse skew (|tP(HL) − tP(LH)|) 10 ns
tr Output signal rise time 1.5 ns
See Figure 6
tf Output signal fall time 1.5 ns
t(loop) Total loop delay, driver input to receiver output V(RS) = 0 V 70 135
t(loop) Total loop delay, driver input to receiver output RS with 10 kΩ to ground 105 175 ns
t(loop) Total loop delay, driver input to receiver output RS with 100 kΩ to ground 535 920

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

device control-pin characteristics over recommended operating conditions (unless otherwise

noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
SN65HVD230Q wake-up time from standby mode with
RS 0.55 1.5 µS
t(WAKE) See Figure 8
SN65HVD231Q wake-up time from sleep mode with RS 3 µS
−5 µA < I(Vref) < 5 µA 0.45 VCC 0.55 VCC
Vref Reference output voltage V
−50 µA < I(Vref) < 50 µA 0.4 VCC 0.6 VCC
I(RS) Input current for high-speed V(RS) < 1 V −450 0 µA
† All typical values are at 25°C and with a 3.3 V supply.

PARAMETER MEASUREMENT INFORMATION

VCC
IO
II
D
VOD 0 V or 3 V 60 Ω
IO CANH

VI
CANL

Figure 1. Driver Voltage and Current Definitions

167 Ω

0V VOD 60 Ω
167 Ω
± −2 V ≤ VTEST ≤ 7 V

Figure 2. Driver VOD

Dominant
CANH ≈3V VOH CANH

Recessive
≈ 2.3 V VOL

CANL ≈1V VOH CANL

Figure 3. Driver Output Voltage Definitions

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

PARAMETER MEASUREMENT INFORMATION

RL = 60 Ω CL = 50 pF VO
(see Note B)
Signal
50 Ω
Generator
(see Note A) RS = 0 Ω to 100 kΩ for SN65HVD230Q and SN65HVD231Q
N/A for SN65HVD232Q

3V

Input 1.5 V

0V

tP(LH) tP(HL)

VOD(D)
90%
0.9 V
Output
0.5 V
10%
VOD(R)
tr tf
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
Zo = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 4. Driver Test Circuit and Voltage Waveforms

IO

VID

V )V VCANH
V + CANH CANL VO
IC 2
VCANL

Figure 5. Receiver Voltage and Current Definitions

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

PARAMETER MEASUREMENT INFORMATION

Output
Signal
50 Ω
Generator
1.5 V CL = 15 pF
(see Note A)
(see Note B)

2.9 V

Input 2.2 V

1.5 V

tP(LH) tP(HL)

VOH
90%
Output 1.3 V
10%
VOL
tr tf
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
Zo = 50 Ω.
B. CL includes probe and jig capacitance.

Figure 6. Receiver Test Circuit and Voltage Waveforms

100 Ω

Pulse Generator,
15 µs Duration,
1% Duty Cycle

Figure 7. Overvoltage Protection

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

PARAMETER MEASUREMENT INFORMATION

Table 1. Receiver Characteristics Over Common Mode With V(RS) at 1.2 V

VIC VID VCANH VCANL R OUTPUT
−2 V 900 mV −1.55 V −2.45 V L
7V 900 mV 8.45 V 6.55 V L
VOL
1V 6V 4V −2 V L
4V 6V 7V 1V L
−2 V 500 mV −1.75 V −2.25 V H
7V 500 mV 7.25 V 6.75 V H
1V −6 V −2 V 4V H VOH
4V −6 V 1V 7V H
X X Open Open H

VCC

10 kΩ
D R Output
0V 60 Ω
CL = 15 pF
RS
Generator
PRR = 150 kHz +
Signal
50% Duty Cycle 50 Ω V(RS)
Generator
tr, tf < 6 ns −
Zo = 50 Ω

VCC

V(RS) 1.5 V

0V

t(WAKE)

R Output 1.3 V

Figure 8. t(WAKE) Test Circuit and Voltage Waveforms

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

TYPICAL CHARACTERISTICS

SUPPLY CURRENT (RMS) LOGIC INPUT CURRENT (D PIN)

vs vs
FREQUENCY INPUT VOLTAGE
33 0

32 −2
I CC − Supply Current (RMS) − mA

I I(L) − Logic Input Current − µ A

31 −4

30 −6

29 −8

28 −10

27 −12

26 −14

25 −16
0 250 500 750 1000 1250 1500 1750 2000 0 0.6 1.1 1.6 2.1 2.6 3.1 3.6
f − Frequency − kbps
VI − Input Voltage − V
Figure 9 Figure 10

BUS INPUT CURRENT DRIVER LOW-LEVEL OUTPUT CURRENT

vs vs
BUS INPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
400 180
I OL − Driver Low-Level Output Current − mA

300 160
I I − Bus Input Current − µ A

140
200
VCC = 0 V
120
100
100
VCC = 3.6 V
0
80
−100
60
−200
40

−300 20

−400 0
−7 −6 −4 −3 −1 0 1 3 4 6 7 8 10 11 12 0 1 2 3 4
VO(CANL)− Low-Level Output Voltage − V
VI − Bus Input Voltage − V
Figure 11 Figure 12

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

TYPICAL CHARACTERISTICS

DRIVER HIGH-LEVEL OUTPUT CURRENT DOMINANT VOLTAGE (VOD)

vs vs
HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE
120 3
I OH − Driver High-Level Output Current − mA

VCC = 3.6 V
100 2.5 VCC = 3.3 V

VOD− Dominant Voltage − V

VCC = 3 V
80 2

60 1.5

40 1

20 0.5

0 0
0 0.5 1 1.5 2 2.5 3 3.5 −55 −40 0 25 70 85 125
VO(CANH) − High-Level Output Voltage − V TA − Free-Air Temperature − °C

Figure 13 Figure 14

RECEIVER LOW-TO-HIGH PROPAGATION DELAY TIME RECEIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs vs
t PHL− Receiver High-to-Low Propagation Delay Time − ns

FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE

t PLH − Receiver Low-to-High Propagation Delay Time − ns

38 40
RS = 0 RS = 0
37
39
36
VCC = 3 V 38 VCC = 3 V
35

VCC = 3.3 V
34 37 VCC = 3.3 V

VCC = 3.6 V
33
36 VCC = 3.6 V

32
35
31

30 34
−55 −40 0 25 70 85 125 −55 −40 0 25 70 85 125

TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 15 Figure 16

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 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

TYPICAL CHARACTERISTICS

DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE

t PHL− Driver High-to-Low Propagation Delay Time − ns

t PLH − Driver Low-to-High Propagation Delay Time − ns

55 90
RS = 0 RS = 0
VCC = 3 V
50 85 VCC = 3.6 V

45
80

40 VCC = 3.3 V
75 VCC = 3.3 V
35
VCC = 3.6 V 70
VCC = 3 V
30
65
25
60
20

55
15

10 50
−55 −40 0 25 70 85 125 −55 −40 0 25 70 85 125

TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 17 Figure 18

DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
t PLH − Driver Low-to-High Propagation Delay Time − ns

t PHL − Driver High-to-Low Propagation Delay Time − ns

90 150
RS = 10 kΩ RS = 10 kΩ
VCC = 3.6 V
80
140
VCC = 3 V
70 VCC = 3.3 V
130
60 VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
50 120

40 110

30
100
20
90
10

0 80
−55 −40 0 25 70 85 125 −55 −40 0 25 70 85 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 19 Figure 20

www.ti.com 15
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

TYPICAL CHARACTERISTICS

DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE

t PHL− Driver High-to-Low Propagation Delay Time − ns

t PLH − Driver Low-to-High Propagation Delay Time − ns

800 1000
RS = 100 kΩ RS = 100 kΩ

700 VCC = 3 V
950 VCC = 3.6 V

600
VCC = 3.3 V VCC = 3.3 V
900
500

400 VCC = 3.6 V 850

VCC = 3 V
300
800

200
750
100

0 700
−55 −40 0 25 70 85 125 −55 −40 0 25 70 85 125

TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 21 Figure 22

DRIVER OUTPUT CURRENT DIFFERENTIAL DRIVER OUTPUT FALL TIME

vs vs Source Resistance (RS)
SUPPLY VOLTAGE
50 1.50
1.40
µs

1.30 VCC = 3.3 V

40
1.20
I O − Driver Output Current − mA

t f − Differential Output Fall Time −

1.10 VCC = 3.6 V

30 1.00
0.90
0.80
20
0.70
0.60
VCC = 3 V
10 0.50
0.40
0.30
0
0.20
0.10
−10 0
1 1.5 2 2.5 3 3.5 4 0 50 100 150 200
VCC − Supply Voltage − V Rs − Source Resistance − kΩ

Figure 23 Figure 24

16 www.ti.com
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

TYPICAL CHARACTERISTICS
REFERENCE VOLTAGE
vs
REFERENCE CURRENT
3

2.5

V ref − Reference Voltage − V

2 VCC = 3.6 V

1.5
VCC = 3 V

0.5

0
−50 −5 5 50

Iref − Reference Current − µA

Figure 25

APPLICATION INFORMATION

This application provides information concerning the implementation of the physical medium attachment layer
in a CAN network according to the ISO 11898 standard. It presents a typical application circuit and test results,
as well as discussions on slope control, total loop delay, and interoperability in 5-V systems.

introduction
ISO 11898 is the international standard for high-speed serial communication using the controller area network
(CAN) bus protocol. It supports multimaster operation, real-time control, programmable data rates up to 1 Mbps,
and powerful redundant error checking procedures that provide reliable data transmission. It is suited for
networking intelligent devices as well as sensors and actuators within the rugged electrical environment of a
machine chassis or factory floor. The SN65HVD230Q family of 3.3-V CAN transceivers implement the lowest
layers of the ISO/OSI reference model. This is the interface with the physical signaling output of the CAN
controller of the Texas Instruments TMS320Lx240x 3.3-V DSPs, as illustrated in Figure 26.

www.ti.com 17
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

ISO 11898 Specification Implementation

TMS320Lx2403/6/7
Application Specific Layer 3.3-V
DSP

Logic Link Control

Data-Link
Embedded
Layer
Medium Access Control CAN
Controller

Physical Signaling

Physical Physical Medium Attachment

Layer SN65HVD230

Medium Dependant Interface

CAN Bus−Line

Figure 26. The Layered ISO 11898 Standard Architecture

The SN65HVD230Q family of CAN transceivers are compatible with the ISO 11898 standard; this ensures
interoperability with other standard-compliant products.

application of the SN65HVD230Q

Figure 27 illustrates a typical application of the SN65HVD230Q family. The output of a DSP’s CAN controller
is connected to the serial driver input, pin D, and receiver serial output, pin R, of the transceiver. The transceiver
is then attached to the differential bus lines at pins CANH and CANL. Typically, the bus is a twisted pair of wires
with a characteristic impedance of 120 Ω, in the standard half-duplex multipoint topology of Figure 28. Each end
of the bus is terminated with 120-Ω resistors in compliance with the standard to minimize signal reflections on
the bus.

18 www.ti.com
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

Electronic Control Unit (ECU)

TMS320Lx2403/6/7

CAN-Controller

CANTX/IOPC6 CANRX/IOPC7

D R
SN65HVD230

CANH CANL

CAN Bus Line

Figure 27. Details of a Typical CAN Node

ECU ECU ECU

1 2 n

CANH

120 Ω CAN Bus Line 120 Ω

CANL

Figure 28. Typical CAN Network

The SN65HVD230Q/231Q/232Q 3.3-V CAN transceivers provide the interface between the 3.3-V
TMS320Lx2403/6/7 CAN DSPs and the differential bus line, and are designed to transmit data at signaling rates
up to 1 Mbps as defined by the ISO 11898 standard.

features of the SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q

The SN65HVD230Q/231Q/232Q are pin-compatible (but not functionally identical) with one another and,
depending upon the application, may be used with identical circuit boards.
These transceivers feature 3.3-V operation and standard compatibility with signaling rates up to 1 Mbps, and
also offer 16-kV HBM ESD protection on the bus pins, thermal shutdown protection, bus fault protection, and
open-circuit receiver failsafe. The failsafe design of the receiver assures a logic high at the receiver output if
the bus wires become open circuited. If a high ambient operating environment temperature or excessive output
current result in thermal shutdown, the bus pins become high impedance, while the D and R pins default to a
logic high.

www.ti.com 19
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

features of the SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q (continued)

The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free
power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also
means that an unpowered node will not disturb the bus. Transceivers without this feature usually have a very
low output impedance. This results in a high current demand when the transceiver is unpowered, a condition
that could affect the entire bus.

operating modes
RS (pin 8) of the SN65HVD230Q and SN65HVD231Q provides for three different modes of operation:
high-speed mode, slope-control mode, and low-power standby mode.
high-speed mode
The high-speed mode can be selected by applying a logic low to Rs (pin 8). The high-speed mode of operation
is commonly employed in industrial applications. High-speed allows the output to switch as fast as possible with
no internal limitation on the output rise and fall slopes. The only limitations of the high-speed operation are cable
length and radiated emission concerns, each of which is addressed by the slope control mode of operation.
If the low-power standby mode is to be employed in the circuit, direct connection to a DSP output pin can be
used to switch between a logic-low level (< 1 V) for high speed mode operation, and the logic-high level (> 0.75
VCC) for standby mode operation. Figure 29 shows a typical DSP connection, and Figure 30 shows the
SN65HVD230Q driver output signal in high-speed mode on the CAN bus.
SN65HVD230Q
RS IOPF6
D 1 8
TMS320LF2406
GND 2 7 CANH
or
VCC 3 6 CANL TMS320LF2407
R 4 5 Vref

Figure 29. RS (Pin 8) Connection to a TMS320LF2406/07 for High-Speed or Standby Mode Operation

20 www.ti.com
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

high-speed mode (continued)

1 Mbps
Driver Output
NRZ Data

Figure 30. Typical SN65HVD230Q High-Speed Mode Output Waveform Into a 60-Ω Load

slope-control mode
Electromagnetic compatibility is essential in many applications using unshielded bus cable to reduce system
cost. To reduce the electromagnetic interference generated by fast rise times and resulting harmonics, the rise
and fall slopes of the SN65HVD230Q and SN65HVD231Q driver outputs can be adjusted by connecting a
resistor from RS (pin 8) to ground or to a logic low voltage, as shown in Figure 31. The slope of the driver output
signal is proportional to the pin’s output current. This slope control is implemented with an external resistor value
of 10 kΩ to achieve a ≈ 15 V/µs slew rate, and up to 100 kΩ to achieve a ≈ 2.0 V/µs slew rate as displayed in
Figure 32. Typical driver output waveforms from a pulse input signal with and without slope control are displayed
in Figure 33. A pulse input is used rather than NRZ data to clearly display the actual slew rate.
10 kΩ
SN65HVD230Q to
RS 100 kΩ
IOPF6
D 1 8
TMS320LF2406
GND 2 7 CANH
or
VCC 3 6 CANL TMS320LF2407
R 4 5 Vref

Figure 31. Slope-Control or Standby Mode Connection to a DSP

www.ti.com 21
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

DRIVER OUTPUT SIGNAL SLOPE

vs
SLOPE CONTROL RESISTANCE
25
Driver Output Signal Slope − V/µs

20

15

10

0
0 10
4.7 20
6.8 30
10 40
15 22 50 3360 47 70 80
68 90
100
Slope Control Resistance − kΩ

Figure 32. SN65HVD230Q Driver Output Signal Slope vs Slope Control Resistance Value

RS = 0 Ω

RS = 10 kΩ

RS = 100 kΩ

Figure 33. Typical SN65HVD230Q 250-kbps Output Pulse Waveforms With Slope Control

22 www.ti.com
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

standby mode (listen only mode) of the SN65HVD230Q

If a logic high (> 0.75 VCC) is applied to RS (pin 8) in Figures 29 and 31, the circuit of the SN65HVD230Q enters
a low-current, listen only standby mode during which the driver is switched off and the receiver remains active.
In this listen only state, the transceiver is completely passive to the bus. It makes no difference if a slope control
resistor is in place as shown in Figure 31. The DSP can reverse this low-power standby mode when the rising
edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The DSP, sensing bus
activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on RS (pin 8).
the babbling idiot protection of the SN65HVD231Q
Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what
is referred to in CAN jargon as a babbling idiot). When this occurs, the DSP can engage the listen-only standby
mode to disengage the driver and release the bus, even when access to the CAN controller has been lost. When
the driver circuit is deactivated, its outputs default to a high-impedance state.
sleep mode of the SN65HVD231Q
The unique difference between the SN65HVD230Q and the SN65HVD231Q is that both driver and receiver are
switched off in the SN65HVD231Q when a logic high is applied to RS (pin 8). The device remains in a very low
power-sleep mode until the circuit is reactivated with a logic low applied to RS (pin 8). While in this sleep mode,
the bus pins are in a high-impedance state, while the D and R pins default to a logic high.

loop propagation delay

Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the
driver input to the differential outputs, plus the delay from the receiver inputs to its output.
The loop delay of the transceiver displayed in Figure 34 increases accordingly when slope control is being used.
This increased loop delay means that the total bus length must be reduced to meet the CAN bit-timing
requirements of the overall system. The loop delay becomes ≈100 ns when employing slope control with a
10-kΩ resistor, and ≈500 ns with a 100-kΩ resistor. Therefore, considering that the rule-of-thumb propagation
delay of typical bus cable is 5 ns/m, slope control with the 100-kΩ resistor decreases the allowable bus length
by the difference between the 500-ns max loop delay and the loop delay with no slope control, 70.7 ns. This
equates to (500–70.7 ns)/5 ns, or approximately 86 m less bus length. This slew-rate/bus length trade-off to
reduce electromagnetic interference to adjoining circuits from the bus can also be solved with a high-quality
shielded bus cable.

www.ti.com 23
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

Figure 34. 70.7-ns Loop Delay Through the SN65HVD230Q With RS = 0

24 www.ti.com
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

interoperability with 5-V CAN systems

It is essential that the 3.3-V SN65HVD230Q family performs seamlessly with 5-V transceivers because of the
large number of 5-V devices installed. Figure 35 displays a test bus of a 3.3-V node with the SN65HVD230Q,
and three 5-V nodes: one for each of TI’s SN65LBC031 and UC5350 transceivers, and one using a competitor
X250 transceiver.

Tektronix
784D
Tektronix Trigger Oscilloscope
HFS−9003 Input
Pattern Tektronix
Generator P6243
Single-Ended
Probes

One Meter Belden Cable #82841

120 Ω 120 Ω

SN65HVD230Q SN65LBC031 UC5350 Competitor X250

HP E3516A HP E3516A
3.3-V Power 5-V Power
Supply Supply

Figure 35. 3.3-V/5-V CAN Transceiver Test Bed

www.ti.com 25
 SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008

APPLICATION INFORMATION

Driver
Input

CAN
Bus

Receiver
Output

Figure 36. SN65HVD230Q’s Input, CAN Bus, and X250’s RXD Output Waveforms

Figure 36 displays the SN65HVD230Q’s input signal, the CAN bus, and the competitor X250’s receiver output
waveforms. The input waveform from the Tektronix HFS-9003 Pattern Generator in Figure 35 to the
SN65HVD230Q is a 250-kbps pulse for this test. The circuit is monitored with Tektronix P6243, 1-GHz
single-ended probes in order to display the CAN dominant and recessive bus states.
Figure 36 displays the 250-kbps pulse input waveform to the SN65HVD230Q on channel 1. Channels 2 and
3 display CANH and CANL respectively, with their recessive bus states overlaying each other to clearly display
the dominant and recessive CAN bus states. Channel 4 is the receiver output waveform of the competitor X250.

26 www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN65HVD230QD OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 HV230Q

SN65HVD230QDG4Q1 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 230Q1 Samples

SN65HVD230QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV230Q Samples

SN65HVD230QDRG4 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 HV230Q

SN65HVD230QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 230Q1 Samples

SN65HVD231QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV231Q Samples

SN65HVD231QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV231Q Samples

SN65HVD231QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV231Q Samples

SN65HVD231QDRG4 OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 HV231Q

SN65HVD231QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 231Q1 Samples

SN65HVD231QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 231Q1 Samples

SN65HVD232QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q Samples

SN65HVD232QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q Samples

SN65HVD232QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q Samples

SN65HVD232QDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HV232Q Samples

SN65HVD232QDRG4Q1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 232Q1 Samples

SN65HVD232QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 232Q1 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2024

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN65HVD230Q, SN65HVD230Q-Q1, SN65HVD231Q, SN65HVD231Q-Q1, SN65HVD232Q, SN65HVD232Q-Q1 :

• Catalog : SN65HVD230Q, SN65HVD231Q, SN65HVD232Q

• Automotive : SN65HVD230Q-Q1, SN65HVD231Q-Q1, SN65HVD232Q-Q1

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD230QDR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD231QDR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD232QDR SOIC D 8 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD230QDR SOIC D 8 2500 353.0 353.0 32.0
SN65HVD231QDR SOIC D 8 2500 353.0 353.0 32.0
SN65HVD232QDR SOIC D 8 2500 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65HVD230QDG4Q1 D SOIC 8 75 507 8 3940 4.32
SN65HVD231QD D SOIC 8 75 507 8 3940 4.32
SN65HVD231QDG4 D SOIC 8 75 507 8 3940 4.32
SN65HVD232QD D SOIC 8 75 507 8 3940 4.32
SN65HVD232QDG4 D SOIC 8 75 507 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
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