Elements of Computing Systems-2 MIPS

Introduction to MIPS

MIPS Architecture

MIPS (Microprocessor without Interlocked Pipeline Stages) is a RISC

(Reduced Instruction Set Computing) architecture that is widely known
for its simplicity, efficiency, and scalability. Developed by MIPS
Computer Systems in the early 1980s, it has become a foundational
architecture in computer design and is extensively used in embedded
systems, networking equipment, and academic research. The design
philosophy of MIPS emphasizes streamlined instruction sets, high
performance, and ease of implementation.

MIPS follows the RISC principle, which means it uses a small, fixed set
of instructions that execute in a uniform amount of time. This enables
faster execution and simplifies hardware design, as there is less
complexity in handling instructions compared to Complex Instruction Set
Computing (CISC) architectures like x86.

The MIPS architecture implements a five-stage pipeline that breaks

down the instruction execution process into well-defined steps, enabling
the processing of up to five instructions simultaneously, with each
instruction at a different stage in the pipeline. This structure is
fundamental to achieving high instruction throughput while maintaining
a simple and regular design.

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Elements of Computing Systems-2 MIPS

Pipelining is a technique used in modern processors to improve

instruction throughput by overlapping the execution of multiple
instructions. Instead of waiting for one instruction to complete all stages
of execution before starting the next, pipelining divides the instruction
execution process into separate stages. Each stage performs a specific
task, and multiple instructions can be processed simultaneously, each in a
different stage of the pipeline. This approach significantly enhances the
processor's performance by utilizing its resources efficiently.

Figure: MIPS Architecture

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Components of MIPS Architecture

1. Program Counter (PC):

The PC holds the address of the next instruction to be executed. It

increments by 4 after every instruction fetch (since MIPS
instructions are 32 bits wide) to point to the next sequential
instruction. The PC can also be updated with a branch or jump
target address in case of control flow changes.
2. Arithmetic Logic Unit (ALU):

The ALU performs arithmetic operations (e.g., addition, subtraction)

and logical operations (e.g., AND, OR, NOT). It is a critical
component of the execution stage, handling calculations and
decision-making processes required by instructions.
3. Control Unit (CU):

The CU generates control signals based on the opcode of the

instruction. These signals coordinate the actions of other
components in the architecture, such as enabling data transfer
between registers, selecting ALU operations, and determining
memory access.
4. Instruction Memory:

This component stores the program's instructions. During the

instruction fetch stage, the PC is used to retrieve the instruction

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Elements of Computing Systems-2 MIPS

from this memory. Instruction memory is typically read-only

during program execution.
5. Data Memory:

Data memory stores the values used and produced by the program.
Load and store instructions access this memory to retrieve or save
data, respectively, during the memory access stage.
6. Two Adders:

The first adder calculates the next sequential instruction address by

adding 4 to the PC. The second adder is used in branch
instructions to compute the target address by adding an offset to
the PC or base address. These adders play a crucial role in control
flow management

Pipeline Stages

The MIPS pipeline consists of five stages, each handling a specific part
of the instruction execution process.

1. Instruction Fetch (IF):

In this stage, the instruction is fetched from memory using the

address stored in the PC. After the instruction is retrieved, the PC
is incremented by 4 to point to the next instruction. This ensures
the proper sequence of instruction execution. If a branch or jump

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Elements of Computing Systems-2 MIPS

occurs, the PC is updated with the branch or jump target address

instead.
2. Instruction Decode (ID):

During this stage, the fetched instruction is decoded to understand

its purpose and requirements. The opcode is analyzed, and control
signals are generated by the CU. The registers involved in the
instruction, such as source and destination registers, are identified,
and their values are fetched from the register file. If the
instruction includes an immediate value, it is extracted and
converted to the appropriate format (sign-extended) to prepare it
for execution.
3. Execution (EX):

In this stage, the actual operation specified by the instruction is

carried out. The ALU performs arithmetic or logical operations
using the data from the source registers or immediate values. For
load and store instructions, the memory address is calculated. If
the instruction involves branching, the target address is computed.
4. Memory Access (MEM):

This stage is responsible for memory-related operations. For load

instructions, data is retrieved from memory at the address
computed in the execution stage. For store instructions, data is
written to memory. Instructions that do not involve memory simply
pass their results unchanged to the next stage.

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Elements of Computing Systems-2 MIPS

5. Write Back (WB):

In the final stage, the result of the instruction is written back to

the destination register. This ensures the output of the instruction
is available for future operations or program requirements. For
instance, arithmetic results from the ALU or data loaded from
memory are stored in the register file in this stage.

The systematic division of tasks across these five stages ensures that
multiple instructions can be executed concurrently, maximizing efficiency
and throughput.

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MIPS Instruction Set

1. Arithmetic Instructions

a. Add

● Instruction: add $1, $2, $3

● Explanation: Adds the values in registers $2 and $3, and stores the
result in $1.
→ Signed addition of two registers. Signed operations treat the
numbers as two's complement integers, handling both positive and
negative values.
● Example:
○ Let $2 = 5 and $3 = 3.
○ After execution: $1 = $2 + $3 = 5 + 3 = 8.

b. Subtract Unsigned

● Instruction: subu $1, $2, $3

● Explanation: Subtracts the value in register $3 from the value in
register $2 using unsigned arithmetic, and stores the result in $1.
→ Unsigned subtraction of two registers. Unsigned operations
assume that all values are non-negative, thus ignoring the sign bit and
performing calculations as if the numbers are always positive.
● Example:
○ Let $2 = 100 and $3 = 30.
○ After execution: $1 = $2 - $3 = 100 - 30 = 70.

c. Add Immediate

● Instruction: addi $1, $2, 100

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● Explanation: Adds the immediate constant 100 to the value in register

$2, and stores the result in $1.
→ Adds a constant (immediate) to a register. Signed operations treat
the numbers as two's complement integers.
● Example:
○ Let $2 = 50.
○ After execution: $1 = $2 + 100 = 50 + 100 = 150.

d. Add Unsigned

● Instruction: addu $1, $2, $3

● Explanation: Adds the values in registers $2 and $3 using unsigned
arithmetic, and stores the result in $1.
→ Unsigned addition of two registers. Unsigned operations assume
that all values are non-negative, thus ignoring the sign bit and
performing calculations as if the numbers are always positive.
● Example:
○ Let $2 = 50 and $3 = 30.
○ After execution: $1 = $2 + $3 = 50 + 30 = 80.

e. Multiply without overflow

● Instruction: mul $1, $2, $3

● Explanation: Multiplies values in registers $2 and $3 and stores the
result in $1.
→ Here the result is within 32 bits
● Example:
○ mul $1, $2, $3

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● Input Values:
○ $2 = 15
○ $3 = 10
● Calculation:
15×10= 150=(10010110)
● Result:
○ The value 150 fits within 32 bits.
○ $1 = 150 (no overflow occurs).

e. Multiply with overflow

● Instruction: mult $2, $3

● Explanation: Multiplies values in registers $2 and $3
→ The result is a 64-bit value, which is split into two parts:
❖ Hi Register: Stores the upper 32 bits of the result.
❖ Lo Register: Stores the lower 32 bits of the result.

→ Here, the result exceeds 32 bits, and the upper bits are stored in the
Hi Register.

● Example:
○ mult $2, $3
● Input Values:
○ $2 = 100,000
○ $3 = 50,000

Calculation:

100,000×50,000=5,000,000,000

Binary Representation of the Result:

5,000,000,000=0000000100100100011110010000000000000000(64 bits)

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Elements of Computing Systems-2 MIPS

Split the result into:

● Hi Register (upper 32 bits): 0000 0001 0010 0100 =

18,30418,30418,304
● Lo Register (lower 32 bits): 0111 1001 0000 0000 0000 0000 =
2,867,200,0002,867,200,0002,867,200,000

f. Division

● Instruction: mult $2, $3

● Explanation: Divides the value in register $2 by the value in register
$3. The result is split into two parts:
❖ Hi Register: Stores the remainder of the division.
❖ Lo Register: Stores the quotient of the division.

→ This instruction is used to perform integer division, and both quotient

and remainder are preserved.

Example

Instruction: div $2, $3

Input Values:

● $2 = 20 (dividend)
● $3 = 6 (divisor)

Result Storage:

● Lo Register: Stores the quotient 3

● Hi Register: Stores the remainder 2

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2. Logical Instructions

a. Bitwise AND

● Instruction: and $1, $2, $3

● Explanation: Performs a bitwise AND between the values in registers
$2 and $3, and stores the result in $1.
→ Performs bitwise AND between two registers.
● Example:
○ Let $2 = 1010 (binary) and $3 = 1100 (binary).
○ After execution: $1 = $2 & $3 = 1010 & 1100 = 1000 (binary).
○ In decimal: $1 = 8.

b. Bitwise OR

● Instruction: or $1, $2, $3

● Explanation: Performs a bitwise OR between the values in registers
$2 and $3, and stores the result in $1.
→ Performs bitwise OR between two registers.
● Example:
○ Let $2 = 1010 (binary) and $3 = 1100 (binary).
○ After execution: $1 = $2 | $3 = 1010 | 1100 = 1110 (binary).
○ In decimal: $1 = 14.

c. AND Immediate

● Instruction: andi $1, $2, 100

● Explanation: Performs a bitwise AND between the value in register $2
and the immediate value 100, and stores the result in $1.
→ Performs bitwise AND between the value in $2 and the
immediate value 100. The result is stored in $1.

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● Example:
○ Let $2 = 150 and the immediate value 100 (binary 01100100).
○ $2 = 150 in binary is 10010110, and 100 is 01100100.
○ After execution: $1 = $2 & 100 = 10010110 & 01100100 =
00000100 (binary).
○ In decimal: $1 = 4.

d. OR Immediate

● Instruction: ori $1, $2, 100

● Explanation: Performs a bitwise OR between the value in register $2
and the immediate value 100, and stores the result in $1.
→ Performs bitwise OR between the value in $2 and the immediate
value 100. The result is stored in $1.
● Example:
○ Let $2 = 50 and the immediate value 100 (binary 01100100).
○ $2 = 50 in binary is 00110010, and 100 is 01100100.
○ After execution: $1 = $2 | 100 = 00110010 | 01100100 =
01110110 (binary).
○ In decimal: $1 = 118.

e. Shift Left Logical (SLL)

● Instruction: sll $1, $2, 10

● Explanation: Shifts the value in register $2 to the left by 10 bits and
stores the result in $1.
→ Shifts left by a constant number of bits.
● Example:
○ Let $2 = 5 (binary 0000000000000101).
○ After execution: $1 = 5 << 10 = 00000001010000000000
(binary)
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○ In decimal: $1 = 5120.

f. Shift Right Logical (SRL)

● Instruction: srl $1, $2, 10

● Explanation: Shifts the value in register $2 to the right by 10 bits and
stores the result in $1.
→ Shifts right by a constant number of bits.
● Example:
○ Let $2 = 1024 (binary 0000010000000000).
○ After execution: $1 = 1024 >> 10 = 0000000000000010 (binary)
○ In decimal: $1 = 2.

3. Branch Instructions

a. Branch on Equal

● Instruction: beq $1, $2, 100

● Explanation: Branches to address PC + 4 + 100 if the values in
registers $1 and $2 are equal.
→ Branches if two registers are equal.
● Example:
○ Let $1 = 10 and $2 = 10.
○ After execution: The branch will occur because the values in $1
and $2 are equal.

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Elements of Computing Systems-2 MIPS

b. Branch on Not Equal

● Instruction: bne $1, $2, 100

● Explanation: Branches to address PC + 4 + 100 if the values in
registers $1 and $2 are not equal.
→ Branches if two registers are not equal.
● Example:
○ Let $1 = 10 and $2 = 5.
○ After execution: The branch will occur because the values in $1
and $2 are not equal.

c. Branch on Greater Than

● Instruction: bgt $1, $2, 100

● Explanation: Branches to address PC + 4 + 100 if the value in register
$1 is greater than the value in register $2.
→ Branches if one register is greater than the other.
● Example:
○ Let $1 = 20 and $2 = 10.
○ After execution: The branch will occur because $1 is greater than
$2.

d. Branch on Greater Than or Equal

● Instruction: bge $1, $2, 100

● Explanation: Branches to address PC + 4 + 100 if the value in register
$1 is greater than or equal to the value in register $2.
→ Branches if one register is greater than or equal to the other.
● Example:
○ Let $1 = 15 and $2 = 15.
○ After execution: The branch will occur because $1 is equal to $2.

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Elements of Computing Systems-2 MIPS

e. Branch on Less Than

● Instruction: blt $1, $2, 100

● Explanation: Branches to address PC + 4 + 100 if the value in register
$1 is less than the value in register $2.
→ Branches if one register is less than the other.
● Example:
○ Let $1 = 5 and $2 = 10.
○ After execution: The branch will occur because $1 is less than $2.

4. Data Transfer and Unconditional Jumps

a. Load Word (LW)

● Instruction: lw $1, 0($2)

● Explanation: Loads a word from memory at the address calculated by
adding the offset 0 to the value in register $2, and stores the result in
register $1.
→ Loads data from memory to a register.
● Example:
○ Let $2 = 1000.
○ After execution: The instruction will load the word from memory
at address 1000 into register $1.

b. Store Word (SW)

● Instruction: sw $1, 0($2)

● Explanation: Stores the word in register $1 to memory at the address
calculated by adding the offset 0 to the value in register $2.
→ Stores data from a register to memory.
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● Example:
○ Let $1 = 50 and $2 = 2000.
○ The instruction will store the value 50 from register $1 into
memory at address 2000.

c. Jump (J)

● Instruction: j 0x00400020
● Explanation: Jumps to the address 0x00400020 unconditionally.
→ Jumps to a specified address.
● Example:
○ This instruction will set the Program Counter (PC) to
0x00400020 and continue execution from that address.

d. Jump and Link (JAL)

● Instruction: jal 0x00400020

● Explanation: Jumps to the address 0x00400020 and saves the address
of the next instruction (return address) in register $ra.
→ Jumps to a specified address and stores return address in $ra.
● Example:
○ This instruction will jump to address 0x00400020 and store the
current PC value (the address of the next instruction) in $ra for
future return.

e. Jump Register (JR)

● Instruction: jr $ra

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Elements of Computing Systems-2 MIPS

● Explanation: Jumps to the address stored in the register $ra. Typically

used to return from a function.
→ Jumps to the address in the register.
● Example:
○ After executing jal, the return address is stored in $ra. To return
from the function, jr $ra will jump to that address.

Registers in MIPS

CPI (Cycles Per Instruction) Metric

CPI, or Cycles Per Instruction , is a performance metric in computer

architecture that measures the average number of clock cycles a
processor takes to execute one instruction. It provides insight into how
efficiently a CPU executes instructions in a program.

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CPI=Total Clock Cycles Used/Total Instructions executed

● Total Clock Cycles Used : The total number of clock cycles the CPU
takes to execute the program.
● Total Instructions Executed : The total number of instructions in the
program.

Significance of CPI

1. Performance Measurement : A lower CPI indicates better

performance because fewer cycles are needed to execute an
instruction.
2. Hardware Efficiency : Reflects how well the hardware (e.g., pipeline
stages, caches, and ALU) is utilized.
3. Instruction Set Design : CPI varies depending on the instruction
set and the complexity of each instruction. RISC (Reduced
Instruction Set Computer) architectures like MIPS aim for a lower
CPI.
4. Impact of Instruction Mix : Different instructions (e.g., arithmetic,
memory, branch) have different cycle requirements. The overall CPI
depends on the mix of instructions in a program.

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CPI in Multi-Cycle Processors

In multi-cycle processors, instructions are executed in multiple steps,

and different instructions may take different numbers of cycles. For
example:

● Arithmetic instructions (e.g., add, sub): 4 cycles

● Load/store instructions (e.g., lw, sw): 5 cycles
● Branch instructions (e.g., beq, bne): 3 cycles

CPI (Cycles Per Instruction ) can be calculated as a weighted average

when a program consists of multiple types of instructions, each requiring

a different number of cycles to execute. This approach accounts for the
frequency of each instruction type and its respective CPI contribution.

Where:

● Instruction Counti_ii ​: The number of instructions of type iii.

● CPIi_ii ​: The cycles per instruction for type iii.

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Elements of Computing Systems-2 MIPS

● Total Instructions Executed : The sum of all instruction counts.

Example Calculation

Program Details:

● Total Instructions Executed: 1,000

● Total Clock Cycles: 2,500

CPI= 2.5 ,This means, on average, the processor takes 2.5 cycles per

instruction .

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