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29 views28 pages

New Lec18

Uploaded by

sinhakishan718
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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TMS320C6000

ARCHITECTURE - I
The TMS320 DSPs
 The TMS320 DSP family consists of fixed-point, floating-
point, and multiprocessor digital signal processors.

 TMS320 DSPs have an architecture designed specifically


for real-time signal processing.

 TMS320 family consists of many generations:


 C1x, C2x, C2xx, C5x, and C54x fixed-point DSPs
 C3x and C4x floating-point DSPs, and
 C8x multiprocessor DSPs.

 And the TMS320C6x generation,


The TMS320C6x Series
 The TMS320C6000 digital signal processor platform is
part of the TMS320 DSP family.

 Fixed Point Devices


 TMS320C62x DSP generation
 TMS320C64x DSP generation

 Floating point devices


 TMS320C67x DSP generation.

 All three use the VelociTI architecture, a high-performance,


advanced VLIW (very long instruction word) architecture
 Excellent choices for multichannel and multifunction
applications.
The TMS320C6x Series
 VelociTI’s advanced features include
 Instruction packing: reduced code size
 Gives code size equivalence for eight instructions
 Reduces code size, program fetches, and power consumption

 Conditional execution of all instructions


 Reduces costly branching
 Increases parallelism for higher sustained performance

 Fully pipelined branches: zero-overhead branching.


Features of the ’C67x

 Advanced VLIW CPU with eight functional


units
 Two multipliers & Six arithmetic units
 Executes up to eight 32-bit instructions per cycle
 Develop highly effective RISC-like code

 CPU consists of 32 general purpose registers (32-


bit )
Features of the ’C67x
 Variable-width instructions: flexibility of data
types
 8/16/32-bit data support, providing efficient memory
support

 Efficient code execution on independent


functional units
 Industry’s most efficient C compiler on DSP
benchmark suite
 Industry’s first assembly optimizer for fast
development and improved Parallelization
Features of the ’C67x

 40-bit arithmetic - vocoders & computationally


intensive applications.

 Saturation and normalization – support for key


arithmetic operations.

 Field manipulation and instruction extract, Set,


clear, and bit counting – support common
operations in control and data manipulation
applications.
Features of the ’C67x

 Hardware support for


 Single-precision (32-bit).
 Double-precision (64-bit) IEEE floating-point
operations.

 32 x 32-bit integer multiply with 32- or 64-


bit result
TMS320C67x Architecture
 TMS320C6000 devices come with
 Program memory
 Varying sizes of data memory
 Peripherals
 Direct memory access (DMA) controller
 Power-down logic
 External memory interface (EMIF)
 Serial ports
 Host ports
TMS320C67x Architecture
 Central Processing Unit (CPU)
 Program fetch unit
 Instruction dispatch unit
 Instruction decode unit
 Two data paths, each with four functional units
 Thirty two 32-bit registers
 Control registers
 Control logic
 Test, emulation, and interrupt logic
TMS320C67x Architecture
 Internal Memory
 32-bit, byte-addressable address space
 Internal (on-chip) memory
 Data and program spaces

 Off-chip memory - Unified memory space


 Two 32-bit internal ports to access internal
data
 Single internal port to access internal Program
memory – width of 256 bits
TMS320C67x Architecture
 Memory and Peripheral Options
 Large on–chip RAM, up to 7M bits
 Program cache
 2–level caches
 32–bit EMI supports SDRAM, SBSRAM, SRAM &
other asynchronous memories
 DMA Controller transfers data between address ranges
in the memory map
 The DMA controller has four programmable channels
and a fifth auxiliary channel
TMS320C67x Architecture

 EDMA Controller
 16 programmable channels
 RAM space to hold multiple configurations for
future transfers.
 HPI
 McBSP (multichannel buffered serial port) -
standard synchronous serial port
TMS320C67x Architecture
 Timers are two 32–bit general–purpose timers
 Time events
 Count events
 Generate pulses
 Interrupt the CPU
 Send synchronization events to the DMA/EDMA
controller
 Power–down logic allows reduced clocking to
reduce power consumption
CPU DATA PATHS &
CONTROL
Components of Data Path
 The components of data path consists of the
following
 Two general-purpose register files (A and B)
 Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2,
.D1, and .D2)
 Two load-from-memory data paths (LD1 and LD2)
 Two store-to-memory data paths (ST1 and ST2)
 Two data address paths (DA1 and DA2)
 Two register file data cross paths (1X and 2X).
Functional Units
 The eight functional units are divided into two
groups of four.
 Functional Units and Operations Performed:
Functional Units and Operations
Performed
General-Purpose Register Files
 There are two general-purpose register files (A and B) in the data paths.
Each of these files contains 16 32-bit registers (A0–A15 for file A and
B0–B15 for file B).

 The general-purpose registers can be used for data, data address pointers,
or condition registers.

 The C67x general-purpose register files support data ranging in size from
packed 16-bit data through 40-bit fixed-point and 64-bit floating point
data.

 Values larger than 32 bits, such as 40-bit long and 64-bit float quantities,
are stored in register pairs. In these the 32 LSBs of data are placed in an
even-numbered register and the remaining 8 or 32 MSBs in the next
upper register (which is always an odd-numbered register).
General-Purpose Register Files

 There are 16 valid


register pairs for 40-
bit and 64-bit data.

 In assembly language
syntax, a colon
between the register
names denotes the
register pairs, and the
odd-numbered
register is specified
first.
General-Purpose Register Files
 Register storage scheme for 40-bit long data:
 Operations requiring a long input ignore the 24 MSBs of the odd-numbered
register. Operations producing a long result zero-fill the 24 MSBs of the
odd-numbered register. The even-numbered register is encoded in the
opcode.
Register File Cross paths
 1X & 2X Register file cross paths
 Allow access of operands - functional
units of opposite data path
Memory Load Store Paths
 Two 32–bit paths for loading data from memory to
the register file
 LD1 (LD1 LSB and LD1 MSB) for register file A
 LD2 (LD2 LSB and LD2 MSB) for register file B

 LDDW instruction simultaneously load two 32–bit


values into register file A and two 32–bit values
into register file B
Memory Store Paths

 Two 32–bit paths for storing data to


memory from the register file
 ST1 for register file A
 ST2 for register file B
Data Address Paths
 DA1 & DA2 are connected to the .D units
in both data paths.
 The DA1 and DA2 resources and their
associated data paths are specified as T1
and T2 respectively.

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