PNR20250111 - Trainee Engineer, IC Physical Design
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MCQ
Which type of device is more susceptible to glitches?
Edge-triggered
Level-triggered
Both equally
Neither
Clear selection
What does the operator “&&” in the assign statement means in the following verilog code:
bit wise AND operator for 3 inputs a, b and c
Result will be true if all of a, b and c are true.
Result will be true if any of a or b or c is true
bit wise AND operator for only a and b
Clear selection
if a three variable switching function is expressed as the product of maxterms by the following function f,
then it can also be expressed as sum of minterms by :
∏(1,2,4,7)
∑(0,3,5,6)
∑(1,2,3,7)
∑(1,2,4,7)
Clear selection
Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-
0, as shown below. To complete the circuit , the input X should be:
Q2 + Q1
Q1 ⊕ Q2
Q2
(Q1 ⊕ Q2)'
Clear selection
How many times 0 will be printed if the following C program is executed?
Infinit
Never
Once
None of the above
Clear selection
What are the dominant faults in diffusion layers?
Short circuit faults
Open circuit faults
Both short and open circuit faults
None of the above
Clear selection
Switching speed of a MOS device depends on _______
Vg> Vth
Only electron mobility
Channel length of enhanement type MOS
None of the above
Clear selection
The figure shown below is a logic structure of _______?
Pulse Width Modulation
Static CMOS
Dynamic CMOS
None of the above
To propagate a fault along a selected path to primary output, setting _____ is done.
NAND to 0
AND to 1
NOR to 1
OR to 1
Which circuit does the following curve represent?
CMOS NAND
CMOS NOR
CMOS INVERTER
CMOS BUFFER
Clear selection
What will be the output of the following switching function:
∑(1,3,5,7,9)
∑(3,5,7,9,11)
∑(3,5,9,11,13)
∑(5,7,9,11,13)
What will be the output of a in the current time step if initially a=20 and b=10 for the following statement
in Verilog?
always @ (posedge clock) begin a <= b; b <= a; end
30
20
10
0
Clear selection
What is the output of the following C program:
0
1
2
Compile error
Clear selection
The high current driving capability of the BiCMOS is due to ___________
NMOS in saturation mode
PMOS in saturation mode
CMOS
BJT
Clear selection
What will be the output of the following program:
1
2
5
6
What will be the output of the following c program?
32
3210123
3210
None of the above
Clear selection
Pass transistors are used as ____________
Switches connected in parallel
Switches connected in series
Inverter connected in parallel
Inverter connected in series
Clear selection
What will be the output of the following C code?
65
A
0
c
Clear selection
Which circuit can be implemented using the following truth table:
4:2 Decoder
4:2 Mux
4:2 encoder
4:2 Demux
Clear selection
If p is an integer pointer with a value 1000, then what will be the value of p + 5 be?
1005
1020
1004
10100
Clear selection
The difference between two decimal numbers 83 and 67 in binary format will be :
1100110
110011
100000
101010
Clear selection
Sudden transient in power can cause latch-up.
TRUE
FALSE
Clear selection
Which type of circuit is represented by the following diagram?
Pass transistor circuit
Non-inverting buffer
Tri-state inverter
Transmission gate circuit
Clear selection
A flip flop has __________stable status
2
3
4
5
Clear selection
Which data type is used for declaring module ports in verilog?
wire
reg
port
int
Clear selection
The gate ideally suited for bit comparison is a
Two input exclusive NOR gate
Two input exclusive OR gate
Two input NAND date
Two input NOR gate
Clear selection
Identify the error in the below C code:
Wrong printf format
syntax error
Cannot take characters in '_'
No error
Clear selection
An AND gate __________
implements logic addition
is equivalent to a series switching circuit
is an any-or-all gate
is equivalent to a parallel switching circuit
Clear selection
Which case/cases will be executed from the following c program?
Case 1 & Case 2
Case 2 & Case 3 & default
default
None of the case will be executed
The following logic expression can be implemented by given inputs A and B to two input _________
NOR gate
NAND gate
X-OR gate
X-NOR gate
Clear selection
Given the following Verilog code, what value of "a" is displayed?
1
0
garbage value
no value will be shown in the ouput
In latchup condition, parasitic component gives rise to _________ conducting path.
Low capacitance
High capacitance
Low resistance
High resistance
What will be the output of the following truth table for a transmission gate?
0,0,1,1
1,1,0,0
Z,Z,0,1
0,1,Z,Z
Source and drain in nMOS device are isolated by __________
A single diode
Two diodes
Three diodes
Four diodes
Clear selection
What does the following c program print?
3
2
1
0
Clear selection
How many times "find" will be printed in the output for the following C program?
50
0
10
20
What change/changes need to be made to get output as “YES”?
#include <stdbool.h>
bool ok = YES
bool ok=true
both a & c
A 2-input XOR gate can be worked as an Inverter (NOT Gate) if A =? & B =?
A = a , B =0
A = a , B =1
A=b, B=a
None
If inputs are controlled by equal amount of charge, which one the following will be true?
Cs(MOS) is lesser than Cbase(bipolar)
Cg(MOS) is greater than Cbase(bipolar)
Cg(MOS)=Cbase(bipolar)
Cg(MOS) is lesser than Cbase(bipolar)
Clear selection
The power consumption of the dynamic RAM is _________
More than that of the static RAM
Equal to that the static RAM
Less than that of the static RAM
Zero
Clear selection
What can be introduced to reduce the latch-up effect?
Latch-up ring
Substrate modification
Guard Rings
None of the above
Clear selection
The number of digits required to represent a decimal number 31 in equivalent binary form are
___________
4
8
is even
is odd
Clear selection
Find out the error from the below C code:
Incorrect variable declaration
Missing return value in sum
Syntax error
Garbage value will be printed
Clear selection
The 1's complement of a binary number is obtained by changing ____________
Each 1 to a 0
Each 0 to 1
Each 1 to 0 and each 0 to 1
Adding 1 to the binary number
Clear selection
One pass transistor can be driven through the output of another.
True
False
Clear selection
The below equation represents which mode of operation of a MOS transistor?
Cut-off
Non saturation
Linear
Saturation
Clear selection
If each Successive Code differs from its preceding code by a single bit only,Then this code is called
_______
BCD code
Gray Code
Weighted Code
Binary Code
Clear selection
In inverter, during logic 1 to 0 transition, capacitance discharges at _____
Pull-up resistance
Pull-down resistance
gate
both pull-up and pull-down network
Clear selection
What will be the output of the following verilog code:
54
36
45
9
Clear selection
De Morgan’s theorem states that:
(A + B)' = A' . B' AND (A . B)' = A' . B'
(A +B)' = A' + B' AND (A . B)' = A' . B'
(A + B)' = A' . B' AND (A . B)' = A' + B'
(A + B)' = A' + B' AND (A . B)' = A' + B'
Clear selection
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