CEG 3155: Digital Systems

(Fall 2024)
Prof. Rami Abielmona
Possible Solutions Assignment #3: Sequential
Circuits Concepts

November 5, 2024

Question I
This question is concerned with the state table reduction using the method of
division of equivalence of class. Part c is question 6.18 of your textbook.

Part a
The partitions for this state table are::

Π1 = (ABCDEF GH)
Π2 = (ACDE)(BF G)(H)
Π3 = (ACDE)(BG)(F )(H)
Π4 = (ACE)(D)(BG)(F )(H)
Π5 = (ACE)(D)(BG)(F )(H)

So, we can reduce our original table from 8 to 5 states. By eliminating

the rows corresponding to the states C, E, and G, and replacing in
the columns, the states C and E with A, and G with B, we get the reduced
table shown in table 1.

Part b
The partitions for this state table are:

Π1 = (ABCDEF GH)

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 Present Next State Yield
State x=0 x=1
y2 y1 y0 Y2 Y1 Y0 Y2 Y1 Y0 x=0 x=1
A B A 0 0
B A D 1 0
D F A 0 0
F F H 1 0
H D F 1 1

Table 1: Reduced Table of Question 1a

Π2 = (ACEF H)(BDG)
Π3 = (AEF )(CH)(BG)(D)
Π4 = (AEF )(CH)(BG)(D)

So, we can reduce our original table from 8 to 4 states. By eliminating

the rows corresponding to the states E, F, H and G, and replacing in
the columns, the states E and F with A, H with C, and G with B, we
get the reduced table which is shown in table 2.

Present Next State Yield

State x=0 x=1
y1 y0 Y1 Y0 Y1 Y0
A B C 1
B D A 0
C A A 1
D A C 0

Table 2: Reduced Table of Question 1b

Part c
The partitions for this state table are:

Π1 = (ABCDEF G)
Π2 = (ADG)(BCEF )
Π3 = (AG)(D)(B)(CE)(F )
Π4 = (A)(G)(D)(B)(CE)(F )
Π5 = (A)(G)(D)(B)(CE)(F )

So, we can reduce our original table from 7 to 6 states. By eliminating

the row corresponding to the state E, and replacing in the columns,

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the state E with C, we obtain the reduced table which is shown in table
3.
Present Next State Yield
State x=0 x=1
y2 y1 y0 Y2 Y1 Y0 Y2 Y1 Y0 x=0 x=1
A B C 0 0
B D - 0 1
C F C 0 1
D B G 0 0
F C D 0 1
G F - 0 0

Table 3: Reduced Table of Question 1c

Question II
This question is concerned with the design using the FSM method. Parts a and
b are questions 6.37 and 6.38 of your textbook.

Part a
To ensure that device 3 will get the bus, the FSM must be modified
as follows (figure 1).

Part b
The entity questionIIb is encoded in VHDL as below:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY questionIIb IS
PORT (i_clock : IN STD_LOGIC;
i_resetb : IN STD_LOGIC;
i_r : IN STD_LOGIC_VECTOR(1 to 3);
o_g : OUT STD_LOGIC_VECTOR(1 to 3));
END questionIIb;

ARCHITECTURE Behavior OF questionIIb IS TYPE

stateType IS (Idle, gnt1, gnt2, gnt3);

SIGNAL int_state: stateType;

BEGIN

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 Figure 1: Arbiter FSM without famine

PROCESS (i_resetb, i_clock)

BEGIN
IF (i_resetb = ’0’) THEN
int_state <= Idle;
ELSIF (i_clock’EVENT AND i_clock = ’1’) THEN
CASE int_state IS
WHEN Idle =>
IF i_r(1) = ’1’ THEN
int_state <= gnt1;
ELSIF i_r(2) = ’1’ THEN
int_state <= gnt2;
ELSIF i_r(3) = ’1’ THEN
int_state <= gnt3;
ELSE int_state <= Idle;
END IF;
WHEN gnt1 =>
IF i_r(1) = ’1’ THEN
int_state <= gnt1;
ELSIF i_r(2) = ’1’ THEN

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 int_state <= gnt2;
ELSIF i_r(3) = ’1’ THEN
int_state <= gnt3;
ELSE int_state<= Idle;
END IF;
WHEN gnt2 =>
IF i_r(2) = ’1’ THEN
int_state <= gnt2;
ELSIF i_r(3) = ’1’ THEN
int_state <= gnt3;
ELSE int_state<= Idle;
END IF;
WHEN gnt3 =>
IF i_r(3) = ’1’ THEN
int_state <= gnt3;
ELSE int_state <= Idle;
END IF;
END CASE;
END IF;
END PROCESS;

g(1) <= ’1’ WHEN int_state = gnt1 ELSE

’0’;
g(2) <= ’1’ WHEN int_state = gnt2 ELSE
’0’;
g(3) <= ’1’ WHEN int_state = gnt3 ELSE
’0’;
END Behavior;

Part c
Let’s start by building a state diagram with the given specifications.
The diagram contains four states: A to indicate that we have not received
our first ’0’, B to indicate that we received it, C to indicate that
we have not received a second ’0’, and D indicate that we received
it. Then the state diagram can be seen in the figure 2. See that
we chose a Moore machine because we can simplify our excitement expressions.
We can convert our state diagram into a state table. The table
is shown in table 4.
Let’s try to reduce our state table using the method of dividing
equivalence of class. Our partitions are:

Π1 = (ABCD)
Π2 = (ABC)(D)
Π3 = (AB)(C)(D)

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 Figure 2: State Diagram

Present Next State Yield

Śtate x=0 x=1
A B A 1
B B C 1
C D C 1
D D D 0

Table 4: State Table to Detect ’0’ blocs

Π4 = (A)(B)(C)(D)

We realize that our table is already reduced to four states. By

following our steps of the FSM, and choosing a sequential encoding
and the following assignment: A → 00, B → 01, C → 10 and D → 11
, we can get our transition table(table 5).

Present Next State Yield

State x=0 x=1
y1 y0 Y1 Y0 Y1 Y0 z
A→ 00 01 00 1
B→ 01 01 10 1
C→ 10 11 10 1
D→ 11 11 11 0

Table 5: Transition Table of our Example

Finally, we arrive with our design equations for our next state
variable and our output from of the system. Note that since this machine

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is a Moore type, the output depends on the present variable only. Check
the figure 3 for the final circuit realized with two D-type flip-flops.

Y1 = y1 + y0 · x (1)
Y0 = x + y1 · y0 (2)
z = y1 · y0 (3)

Figure 3: Final Circuit

Question III
This question is concerned with state transition tables.

Part a
The transition table for a sequential encoding is shown in table 6
For the realization of D flip-flops, the table of excitement is
the same as table 6, while the design equations become:

Y2 = y1 · y0 · x (4)
Y1 = y2 + y1 · x + y1 · y0 · x (5)
Y0 = y2 · x + y1 · x + y2 · y0 · x (6)
z = y2 + y0 · x (7)
For the realization of S-R flip-flops, the table of excitement is
shown in table 7, then that the design equations become:

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 Present Next State Yield
State x=0 x=1
y2 y1 y0 Y2 Y1 Y0 Y2 Y1 Y0 x=0 x=1
A → 000 001 000 0 0
B → 001 000 010 1 0
C → 010 011 000 0 0
D → 011 011 100 1 0
E → 100 010 011 1 1

Table 6: Transition Table of Question 3a

Present Next State Yield

State x=0 x=1
y2 y1 y0 S2 R2 S1 R1 S0 R0 S2 R2 S1 R1 S0 R0 x=0 x=1
000 0d 0d 10 0d 0d 0d 0 0
001 0d 0d 01 0d 10 01 1 0
010 0d d0 10 0d 01 0d 0 0
011 0d d0 d0 10 01 01 1 0
100 01 10 0d 01 10 10 1 1

Table 7: Excitement Table of Question 3a (S-R Flip-flops)

S2 = y1 · y0 · x (8)
R2 = y0 (9)
S1 = y2 + y1 · y0 · x (10)
R1 = y1 · x (11)
S0 = y2 · x + y2 · y0 · x (12)
R0 = y1 · y0 + y0 · x (13)
z = y2 + y0 · x (14)

Part b
By applying the rules of contiguities, we obtain the following conditions:

Rule I (C, D), (A, C)

Rule II (A, B), (A, C), (A, D), (D, E), (C, D)
Rule III (B, D, E)

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 Present Next State Yield
State x=0 x=1
y1 y0 y2 y1 y0 Y2 Y1 Y0 Y2 Y1 Y0 x=0 x=1
y2 00 01 10 11 A → 000 001 000 0 0
0 A B - - B → 001 000 100 1 0
1 C D E - C → 100 101 000 0 0
D → 101 101 111 1 0
E → 111 100 101 1 1

Table 8: Assignment Card and Transition Table for Question 3b

Check the table 8 for the assignment card of states for this state
table, as well as the transition table.
For the realization of the D flip-flop, the design equations are:

Y2 = y2 · x + y0 · x (15)
Y1 = y2 · y1 · y0 · x (16)
Y0 = y0 · x + y1 · x + y2 · y1 · y0 (17)
z = y1 + y0 · x (18)
Finally, for the realization of a S-R flip-flop, the excitement
table is shown in table 9, and the design equations are:

Present Next State Yield

State x=0 x=1
y2 y1 y0 S2 R2 S1 R1 S0 R0 S2 R2 S1 R1 S0 R0 x=0 x=1
000 0d 0d 10 0d 0d 0d 0 0
001 0d 0d 01 10 0d 01 1 0
100 d0 0d 10 01 0d 0d 0 0
101 d0 0d d0 d0 10 d0 1 0
111 d0 01 01 d0 01 d0 1 1

Table 9: Excitement Table of Question IIIb (S-R flip-flops)

S2 = y0 · x (19)
R2 = y0 · x (20)
S1 = y2 · y1 · y0 · x (21)
R1 = y1 (22)
S0 = y0 · x (23)
R0 = y2 · y0 + y1 · x (24)
z = y2 + y0 · x (25)

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Thanks
The answers and figures related to the questions in the manual are taken from
the accompanying instructor’s manual for Fundamentals of Digital Logic with
VHDL Design by Stephen Brown and Zvonko Vranesic.
The answers to the third question are taken from the accompanying instruc-
tor’s manual for Digital Principles and Design by Donald D. Givone.

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