UNIT 4: Microprocessor

Features of Microprocessor
 It is a 16-bit Microprocessor (μp).It has 16 bits ALU
 It has 20 bit address bus can access up to 2 = 1 MB memory locations.
 It has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit
at a time. It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 Frequency range of 8086 is 6-10 MHz
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle to provide internal timing.
 It can prefetch up to 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package.
 8086 is designed to operate in two modes, Minimum mode and Maximum mode.
 The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This
is a single microprocessor configuration.
 The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This
is a multi-microprocessors configuration.

Architecture of 8086 or Functional Block diagram of 8086

 It has two blocks Bus Interface Unit (BIU) and Execution Unit (EU).
 The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
 EU executes instructions from the instruction system byte queue.
 Both units operate asynchronously to give the 8086 an overlapping instruction fetch
and execution mechanism which is called as Pipelining. This results in efficient use of
the system bus and system performance.
 BIU contains Instruction queue, Segment registers, Instruction pointer, and Address
adder.
 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,
Flag register.
BIU: It handles all transfers of data and addresses on the buses for the execution unit.
 Sends out addresses
 Fetches instructions from memory.
 Read / write data from/to ports and memory i.e. handles all transfers of data and
addresses on the busses
EU:
 Tells BIU where to fetch instructions or data from.
 Decodes instructions.
 Executes instructions
(OR)

The functions performed by the Bus interface unit are:

 The BIU is responsible for the external bus operations.
 It performs fetching, reading, writing for memory as well as I/O of data for peripheral
devices.
 The BIU also performs address generation and the population of the instruction
queue.
The Execution unit is responsible for the following work:
 The instructions are decoded and executed by it.
  The EU accepts instructions from the instruction queue and from the general purpose
registers it takes data.
 It has no relation with the system buses.
(NOTE: IN QUESTION IF IT ASKED TO EXPLAIN EACH BLOCK MEANS
WRITE TIS)

Intel 8086 is a 16 bit processor. It has 16-bit data bus and 20-bit address bus. The internal
architecture of Intel 8086 is divided into two units,

1. Bus Interface Unit (BIU)

2. Execution Unit (EU).

Bus Interface Unit (BIU)

Memory Interface: The Bus Interface Unit (BIU) generates the 20-bit physical memory
address and provides the interface with external memory (ROM/RAM). 8086 has a single
memory interface.

Instruction Byte queue: To speed up the execution, 6-bytes of instruction are fetched in
advance and kept in a 6- byte Instruction Queue while other instructions are being executed
in the Execution Unit (EU).

Segment registers: There are four 16-bit segment registers, viz., the code segment (CS), the
stack segment (SS), the extra segment (ES), and the data segment (DS). The processor uses
CS segment for all accesses to instructions referenced by instruction pointer (IP) register.

Adder: 8086's BIU produces the 20-bit physical memory address by combining a 16-bit
segment address with a 16-bit offset address using the adder circuit.

Execution Unit:

Control unit: The instructions fetched by BIU in the instruction byte queue are decoded
under the control of timing and control signals.

Arithmetic and Logic Unit (ALU): Execution unit has a 16 bit ALU, which performs
arithmetic & logic operations.

General purpose register unit: All general registers of the 8086 microprocessor can be used
for arithmetic and logic operations. The general registers are: Accumulator register AL (8
bit), AX (AL & AH for 16 bit), Base register, Count register, Data register , Stack Pointer
(SP), Base Pointer (BP), Source Index (SI), Destination Index (DI).

Flags: It is a 16-bit register containing 9 1-bit flags: Overflow Flag (OF), Direction Flag
(DF), Interrupt-enable Flag (IF), Single-step Flag (TF), Sign Flag (SF), Zero Flag (ZF),
Auxiliary carry Flag (AF), Parity Flag (PF), Carry Flag (CF).

FLAG REGISTER
Flag Register contains a group of status bits called flags that indicate the status of the CPU or
the result of arithmetic operations.
There are two types of flags:
1. The status flags which reflect the result of executing an instruction. The programmer
cannot set/reset these flags directly.
2. The control flags enable or disable certain CPU operations. The programmer can set/reset
these bits to control the CPU's operation.
Control Flags: There are three control flags
1. The Direction Flag (D): This is directional flag. This is used in string related operations.
D = 1, then the string will be accessed from higher memory address to lower memory
address, and if D = 0, it will do the reverse.
2. The Interrupt Flag (I): This is interrupt flag. If I = 1, then Microprocessor unit will
recognize the interrupts from peripherals. For I = 0, the interrupts will be ignored
3. The Trap Flag (T): This trap flag is used for on-chip debugging. When T = 1, it will work
in a single step mode. After each instruction, one internal interrupt is generated. It helps to
execute some program instruction by instruction.
Status Flags: There are six status flags
1. The Carry Flag (C): This is carry bit. If some operations are generating carry after the
operation this flag is set to 1
2. The Overflow Flag (O): The overflow flag is set to 1 when the result of a signed
operation is too large to fit.
3. The Sign Flag (S): After any operation if the MSB is 1, then it indicates that the number is
negative. And this flag is set to 1
4. The Zero Flag (Z): If the total register is zero, then only the Z flag is set
5. The Auxiliary Carry Flag (A): When some arithmetic operations generates carry after
the lower half and sends it to upper half, the AC will be 1
6. The Parity Flag (P): This is even parity flag. When result has even number of 1, it will be
set to 1, otherwise 0 for odd number of 1s

PIN DIAGRAM of 8086

Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries
4-bit address and later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.
Read (\over line {RD})
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt or
not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.
\over line {TEST}
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/\over line {MX}

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-a versa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction
of data flow through the transreceiver. When it is high, data is transmitted out and vice-a-
versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table –

QS0 QS1 STATUS

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27,
and 28. Following is the table showing their status –

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read
 1 1 0 Memory write

1 1 1 Passive

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin
29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.

SEGMENT REGISTER of 8086

Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory
locations. It also contains 1 pointer register IP, which holds the address of the next instruction
to execute by the EU.
CS − It stands for Code Segment. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.
DS − It stands for Data Segment. It consists of data used by the program and is accessed in
the data segment by an offset address or the content of other register that holds the offset
address.
SS − It stands for Stack Segment. It handles memory to store data and addresses during
execution.
ES − It stands for Extra Segment. ES is additional data segment, which is used by the string
to hold the extra destination data.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store 16bit
data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is
referred to the AX, BX, CX, and DX respectively.
 AX register − It is also known as accumulator register. It is used to store operands for
arithmetic operations.
 BX register − It is used as a base register. It is used to store the starting base address of
the memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store the loop
counter.
 DX register − This register is used to hold I/O port address for I/O instruction.
Stack pointer register: It is a 16-bit register, which holds the address from the start of the
segment to the memory location, where a word was most recently stored on the stack.

PIPELINING in 8086
 Performing different task simultaneously by different unit where output of one unit
will become the input of the next unit.
 In pipelined processor, fetch, decode and execute operation are performed
simultaneously or in parallel. When first instruction is being decoded, same time code
of the next instruction is fetched.
 When first instruction is getting executed, second one’s is decoded and third
instruction code is fetched from memory. This process is known as pipelining. It
improves speed of operation to great extent.

Advantage of Microprocessor

 High-speed processing
 Brings intelligence to the system
 Is flexible in nature
 Has a compact size
 Is easy to maintain

Disadvantage of Microprocessor

 Leads to overheating due to continuous use.

 The data size decides the performance
 Larger than microcontrollers
 Doesn’t support floating-point operations

Application of Microprocessor
 Mobile phones
 Automobiles
 CD/DVD players
 Washing machines
 Cameras
 Security alarms
 Keyboard controllers
 Microwave oven
 Watches
 Mp3 players

Evolution of Microprocessor
Microproce Year Instructio Pins Clock
ssor n per frequency
second

Intel 1971 60k 16 740KHz

4004/4040
8008 1972 50K - 500KHz
8080 1974 10times 2MHz MA
quicker XI
than 8008 MU
8085 1976 769230 40 3MHz M
8086 1978 2.5 Million 40 4.77, 8 &
10 MHz
8088 1979 2.5 Million
80186 or 1982 6MHz
80188
80286 1982 4 Million 68 8MHz
80386 1986 8 KB of 132 14X14 16 MHz to
cache PGA 33 MHz
memory
80486 1986 8 KB of 168 17X17 16MHz to
cache PGA (Pin 100 MHz
memory Grid Array)
PENTIUM 1993 Cache 237 PGA. 66 MHz
memory 8-
bit for
instruction
s 8- bit for
data
INTEL core 2 2006 64 KB of L1 1.2 GHz to
cache for 3 GHz
each core
4 MB of L2
cache
i3, i5, i7 2007, 2GHz to
2009, 3.3GHz,
2010 2.4GHz to
3.6GHz &
2.93GHz to
3.33GHz
MODE OF 8086

 In this we can connect more processors to 8086 (8087/8089).

 8086 max mode is basically for implementation of allocation of global
resources and passing bus control to other coprocessor .All processors
execute their own program.

 When MN/ MX’ = 0, 8086 works in max mode.

 Clock is provided by 8284 clock generator.

 8288 bus controller- Address form the address bus is latched into 8282 (8-
bit latch). Three such latches are required because address bus is 20 bit.

 The ALE (Address latch enable) is connected to STB (Strobe) of the

latch. The ALE for latch is given by 8288 bus controller.

 The data bus is operated through 8286 8-bit transceiver. Two such
transceivers are required, because data bus is 16-bit. The transceivers are
enabled the DEN signal, while the direction of data is controlled by the
DT/R signal. DEN is connected to OE’ and DT/ R’ is connected to T. Both
DEN and DT/ R’ are given by 8288 bus controller.
  Control signals for all operations are generated by decoding S’2, S’1 and
S’0 using 8288 bus controller.
S’2 S’1 S’0 output
0 0 0 Interrupt Acknowledge INTA’
0 0 1 Read I/O port IORC’
0 1 0 Write I/O port IOWC’ and AIOWC’
0 1 1 Halt
1 0 0 Instruction Fetch MRDC’
1 0 1 Memory read MRDC’

1 1 0 Memory write MWTC’ and AMWTC’

1 1 1 Inactive

 Bus request is done using RQ’ / GT’ lines interfaced with 8086.
RQ0/GT0 has more priority than RQ1/GT1.
 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
 In max mode, the advanced write signals get enabled one T-state in advance
as compared to normal write signals. This gives slower devices more time to
get ready to accept the data, therefore it reduces the number of cycles.

Advantages of max mode of 8086:

 It helps to interface more devices like 8087.This interface is also called

a closely coupled co-Processor configuration.

 It supports multiprocessing, increase efficiency.

Disadvantages of max mode over min mode:

It has more complex circuit than min mode

MINIMUM MODE OF 8086

 It operates in minimum mode when MN/MX’ = 1

 In minimum mode, 8086 is the only processor in the system which provides
all the control signals which are needed for memory operations and I/O
interfacing.
 Here the circuit is simple but it does not support multiprocessing.
 The other components which are transceivers, latches, 8284 clock generator,
74138 decoder, memory and I/O devices are also present in the system.
 Clock is provided by 8284 clock generator.
 8288 bus controller- Address form the address bus is latched into 8282 (8-
bit latch). Three such latches are required because address bus is 20 bit.
 They are used to separate the valid address from the multiplexed
Address/data bus by using the control signal ALE, which is connected to
strobe (STB) of 8282. The ALE is active high signal.

 8286 (8 bits) transceivers: It is a bidirectional buffers and also known as

data amplifiers. They are used to separate the valid data from multiplexed
add/data bus. Two such transceivers are needed because the data bus is 16
bits long. 8286 is connected to DT/R’ and DEN’ signals. They are enabled
through the DEN signal .The direction of data on the data bus is controlled
by the DT/R’ signal. DT/R’ is connected to T and DEN’ is connected to
OE’.
 M/IO’= 1, then I/O transfer is performed over the bus and when M/IO’ = 0,
then I/O operation is performed.
  The signals RD’ and write WR’ are used to identify whether a read bus
cycle or a write bus cycle is performing. When WR’ = 0, then it indicates
that valid output data on the data bus.
 Control signals for all operations are generated by decoding M/IO’, RD’,
WR’. They are decoded by 74138 3:8 decoder.

 INTR and INTA: When INTR = 1, then there is an interrupt to 8086 by

other devices for their service. When INTA’= 0, then it indicates that
the processor is ready to service them.
 The bus request is made by other devices using the HOLD signal and the
processor acknowledges them using the HLDA output signal.

(TWO MARK)

Physical Address: The address given by BIU is 20 bit called as physical address.
It is the actual address of the memory location accessed by the microprocessor. It is
calculated as

PA=Segment address*10H+offset address

Effective Address: Effective address or the offset address is the offset for a
memory operand. It is an unassigned 16 bit number that gives the operand's
distance in bytes from the beginning of the segment. It is calculated as

EA= Starting address of Segment + offset address

Physical Address (4 Mark)

The 8086 addresses a segmented memory. The complete physical address which is
20-bits long is generated using segment and offset registers each of the size 16-
bit.The content of a segment register also called as segment address, and content of
an offset register also called as offset address. To get total physical address, put the
lower nibble 0H to segment address and add offset address. The figure shows
formation of 20-bit physical address.

For Eg: Calculate the physical address for the given CS=3420H, IP=689AH.
PA=Segment address*10H+offset address
= 3420*10H+689A
=3AA9A

Compare 8086 and 80586 (Pentium)

Parameter 8086 Pentium 80586
Data Bus 16 bit 64bit
Address Bus 20 bit 32 bit
Physical memory 1MB 4GB
Physical memory 16 bit 32bit
Voltage required 5V 3.3V
Clock type 1x 3x
Pipelining Yes Yes

Differentiate between RISC and CISC processor

Parameter RISC CISC
Instruction Set Few instructions More Instruction
Data types Few data types More data types
Addressing modes Few addressing modes More addressing modes
Registers Large number of general Small number of general
purpose register purpose register & special
purpose register
Architecture type Load/store architecture No load/Store architecture
Operation Single cycle Multi cycle
Design Hardwired control Micro coded
Instruction set format Fixed length Variable length