90 INTERVIEW QUESTIONS

1. Tell me about yourself?

A. Self-Details:
1. Greetings ---> hi sir, thank you for giving this opportunity, I’m
very glad to introduce myself.
2. My details --> my self anil, i have 3+ of experience in STA
Domain.
3. Career --> I have started my career at wipro as a fresher and i have
worked at wipro 3 years and for further growth i have switched to
ACL.
currently I’m working in acl.
4. Projects --> i have worked on different node like 28nm, 16nm,
10nm and 7nm.
recently i have worked on 7 nm project. In this project i am main
role on BLOCK LEVEL STA.
here i have worked like, once i received the inputs from PNR team,
i have to check the inputs or valid or not?
some times netlist not able to tool read, linking issue we will see
spef naming issue, spef are not dumped properly, spef file size is
zero.
once i check the all inputs or okay... then i will start the sta run--->
after starting the sta run 15 to 20 mins, i will check the health check
like
LNK-005, LNK-006, SPEF ERRORS, ANNOTATED NUMBERS,
CONSTARINS ERRORS, LOG ERRORS... these are the things
mainly i have checked,
once this all okay.... i will proceed the sta run--> in case if i am
seeing any issue, then i will inform to pnr block onwer to give me
correct inputs.
 after that... i will check the my global timing report--> based on
violations --> i will go for analysis --> i will give feedback to the
PNR team.
last project challenge : <based on resume few points>

2. what are the challenges you faced in your project?

3. What are the inputs of STA?

 Gate Level Netlist
 SDC (Synopsys Design Constraints)
 Library file (Timing library)
 SPEF (Standard Parasitic Extraction Format)
 MMMC (Multi mode Multi Corner)
 DEF (Design Exchange Format)
 UPF (Optional)

4. What are the different stages of inputs you will get?

A. 1. Placement
2. CTS
3. Routing

5. How to define the corner name?

 By using the PVT conditions, we create corners.
 Process: Either Slow Slow or Fast Fast
 Voltage: Based on the requirement of the chip
 Temperature: -40C to +125C.
 Example: 1. P = SS, V = 0.7, T = 40C
3. P = FF, V = 0.7, T = 120C
Given by SS_0P7V_M40C
 FF_0P7V_120C
 Scenario: Func.MMM.s_o.cworst_cc worst_T

6. How to generate the spef file?

• By using Star RC tool we are generating the spef file.
• Spef file is generated after routing.
• For each and every corner spef will be created.

7. What are the inputs of Star RC?

A. Netlist and TLU+

8. .lib file format?

A. LIB file is an ASCII representation of timing and power parameter
associated with cells inside the standard cell library of a particular
technology node. Lib file is basically a timing model file which
contains cell delay, cell transition time, setup and hold time
requirement of the cell.

9. How to calculate cell delay & Net delay?

A. Cell delay:
• Cell delay is the amount of delay from input to output of a logic
gate in a path.
• In the absence of back-annotated delay information from an SDF
file.
• Prime Time calculates the cell delay from delay tables provided
in the technology library for the cell.
 Net delay:
• Net delay is the amount of delay from the output of a cell to the
input of the next cell in a timing path.
• Prime Time can calculate net delays by the following methods are
by using specific time values back-annotated from an SDF file
and by estimating delays from a wire load model.

10. How you will run STA run?

A. pt_shell

11. How can you say your SDC file is good or bad?
A. If the SDC file is fully constrained for timing analysis then we can
say that our SDC file is good.

12. What is generated clock and virtual clock?

A. Generated Clock:
 A generated clock is a clock derived from a master clock.
 A master clock is a clock defined using the create_clock
specification.
 When a new clock is generated in a design that is based on a
master clock, the new clock can be defined as a generated clock
Command: pt_shell> create_generated_clock -name<sys_clk> -
source<PLL/Y> divided_by 2 [get_pins ff/q]
Virtual Clock:
 Virtual clock can be defined as a clock without any source or in
other words a virtual clock is a clock that has been defined, but
has not been associated with any pin/port.
  It does not physically exist in the design but it does exist in the
memory.
Command: pt_shell> create_clock -name <virtual_clk>

13. What is MCP, case analysis, false path?

A. False Path: A logic path that exists in the design but should not be
analyzed.
Command: set_false_path -from < starting point > -to < ending point >

Figure: False Path

Multicycle Path: The number of clock cycles required to propagate

data from the start to the end of the path.
Command: set_multicycle_path - setup 3 – from< > - to < >
set_multicycle_path - hold 2 – from< > - to < >
 Figure: Multicycle Path

Case Analysis: set_case_analysis specifies constant value on a pin of a

cell, or on an input port. If a design has many functional modes and only
one functional mode is being analyzed, case analysis can be used to
specify the actual mode to be analyzed.
Commands: set_case_analysis 0 [get_pins UDFT/MODE_SEL]
set_case_analysis 1 [get_ports SCAN_ENABLE]

14. What is Uncertainty?

A. Uncertainty: Variations of a clock period is called Uncertainty.
The margin for uncertainty is 10 – 20 % of clock. Parameters of
Uncertainty Jitter, Margin and Skew.
Command: pt_shell> report_clock_timing -type interclock_skew -
include_uncertainty_in_skew
15. What is Latency?
A. Latency is also called the Insertion Delay.
 Latency is defined as the time delay between clock source to input
clock pins of flops or it can also be defined as the time needed for
an input change to produce an output change.
 Latency margin is 10 – 15 % of clock period.
 Latency is of two types. They are Source Latency and Network
Latency.
Source Latency: The delay from the clock root pin to clock
definition point is called source latency.
Network Latency: The delay from the clock definition point to
the sink of capture flop is called network latency.
 For Setup = Max values & For Hold = Min values.
 Here only clock inverters and clock buffers are used as cells.
Command: pt_shell> report_clock_timing -type latency

16. What is skew?

A. Difference between the arrival time of two sequential elements in
a design.
Skew = T2 – T1
There are 5 types of skew. They are
1. Positive Skew
2. Negative Skew
3. Local Skew
4. Global skew
5. Useful Skew

17. What is the Tran Limit in your design?

A. report_constraint -max_transition
18. What are DRV?
A. DRV’s are max transition, max capacitance, max fanout.

19. How to check DRV report, what is commands?

A. Command: report _constraint -max_transition -max_capacitance -
max_fanout

20. What is CRPR? Where you will see in report?

A. Clock Reconvergence Pessimism Removal (CRPR) is defined as
the delay difference along the common paths of the launching and
capturing clock paths. It is used to reduce pessimism. In clock path or
required path you will see CRPR.
pt_shell> report_crpr -from < > -to < >

Example timing report showing CRPR

21. What is check_timing?
A. grep "Information: Checking" checktiming.rpt
Information: Checking 'no_input_delay'.
Information: Checking 'no_driving_cell'.
Information: Checking 'unconstrained_endpoints'.
Information: Checking 'unexpandable_clocks'.
Information: Checking 'latch_fanout'.
Information: Checking 'no_clock'.
Information: Checking 'partial_input_delay'.
Information: Checking 'generic'.
Information: Checking 'loops'.
Information: Checking 'generated_clocks'.
Information: Checking 'pulse_clock_non_pulse_clock_merge'.
Information: Checking 'pll_configuration'.

22. In log file what and all you will check?

A. In log file we will check for errors and warnings.
Warnings means LNK – 005 & LNK – 006.
Errors means spef errors, annotated numbers, constraint errors.

23. What is Annotated number? How to get report?

 All the cells we have should be metal connected.
 Those metal information should be in the spef file.
 While reading the spef file, open nets should not be there.
 The open nets which are not connected are called Annotated
numbers.
Command: report_annotated_parasitics -check
24. What is Linking issue? Where you will check? How you will fix
that violation?
A. If the inputs defined in the netlist doesn’t match with the library file,
then linking issues will arise. LNK – 005 & LNK – 006 are the
Synopsys Prime Time codes. We will check these linking issues in log
file in sanity checks. To fix that violation we will give back these inputs
to the PNR team to give back correct inputs.

25. How to get global report?

A. report_global_timing
26. How to get in to out report?
A. For Setup:
report_timing -start_end_type in_to_out -max_paths 1000 >
setup_in2out.rpt
For Hold:

report_timing -start_end_type in_to_out -max_paths 1000 -delay_type

min > hold_in2out.rpt
27. What are the commands to get hold reports?
report_timing -start_end_type reg_to_reg -max_paths 100 -
delay_type min > hold_reg2reg.rpt
report_timing -start_end_type reg_to_out -max_paths 100 -delay_type
min > hold_reg2out.rpt
report_timing -start_end_type in_to_reg -max_paths 100 -delay_type
min > hold_in2reg.rpt
report_timing -start_end_type in_to_out -max_paths 100 -delay_type
min > hold_in2out.rpt

28. How will you analyze the report?

 Check start points and endpoints should have the same clock source
 Check path type: min or max
 Check slack – AT and RT, if slack is violating
 Check the skew number = t2-t1
 Check the logic depth (whatever the cells are present in Tcombo)
 We need to check the type of cells like LVT, HVT, SVT and drive
strength.
 Check the network latency number & CRPR & uncertainty.
 Based on the data path check the max tran value.

29. How to fix setup and hold violations?

A. To fix setup violations:
 VT swap SVT => LVT
pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX2_LVT1
 Upsizing
pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX4_LVT1
 Add high drive strength buffer
pt_shell>insert_buffer
I_CONTEXT_MEM/BINV_RR_237772/Y NBUFFX2_LVT
 Cell is added at (854.9840 585.0120).
{I_CONTEXT_MEM/eco_cell}

 pt_shell> remove_buffer I_CONTEXT_MEM/eco_cell1

To fix hold violations:

 VT swap SVT => HVT
pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX2_HVT1
 Downsizing
pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX2_HVT1
 Add buffer with more delay
pt_shell>insert_buffer
I_CONTEXT_MEM/BINV_RR_237772/Y NBUFFX2_HVT
Cell is added at (854.9840 585.0120).
{I_CONTEXT_MEM/eco_cell}

30. For setup which corner you will check? Best or worst corner?
• For checking setup the scenario is
RC_worst_slow process_high temp_low voltage.
• Slow process - variation accross chip that can slow down the
performance of both pmos and nmos.
• High temp- increase resistance
• Low voltage - increase the charging timing of output capacitance
• Both reducing the performance hence slow corner is used for
setup timing with operating mode. So, Setup corner is worst.

31. If you increase the voltage, what is the impact on cell delay?
A. If the voltage increases then the cell delay decreases.
32. If you are having 20ps capacitance violation, tran have 10ps
violation then which one you will fix?
A. First I will fix the tran violation because if we fix the max transition
then automatically it will fix the max capacitance.

33. What is WNS and TNS?

A. WNS: WNS is worst negative slack of timing path.
TNS: TNS is the total negative slack, which is the sum of all WNS in
design.

34. In your report two different clock sources are reading, what you
will do?
A. If the two different clock sources are reading in the report means it
is asynchronous clocks sources.
For asynchronous clock sources we will not check STA analysis.

35. In your report launch flop is 6ns and capture flop is 12ns, how will
you check the timing analysis?
 If the launch flop has 6ns and capture flop has 12ns in the report then
it is considered as a halfcycle path.
 Timing path that is designed to take half clock cycle for the data to
propagate from the start point to the end point.
 Both the Startpoint and Endpoint Flops should be clocked by the
same Clock.
36. What is PBA and GBA? what is the difference b/w them?
A. PBA (Path Based Analysis):
 We are using the actual slew between input pin and output
combination.
 PBA is used to fix the hold violation.
GBA (Graph Based Analysis):
 In graph based analysis we will consider the worst slew between
the input pin output combination.
 GBA is used to fix the setup violation.
Relation b/w PBA and GBA

To enable PBA & GBA and their reporting commands

set pba_derate -only_mode = True – PBA
report_timing -pba_mode (report for PBA)
set pba_derate -only_mode = False – GBA
report_timing -pba_mode exhaustive (report for GBA)
37. What is Crosstalk? What is the command?
A. Crosstalk: Unintentional coupling between two signals is called as
crosstalk.
 When there is no proper distance between the aggressive net
and the victim net then due to the coupling capacitance these
two nets get hit then the cells in the victim net gets slow. So
the propagation doesn’t take place.
 Violation appears due to the slowing of the victim net.
 The crosstalk occurs because the victim net gets slower.
Command: report_timing -crosstalk_delta

38. What is noise? What is the command?

 A. During the transition on the aggressor net causes a bump or glitch
(under shoot or over shoot) on the victim net this phenomenon is called
crosstalk noise.
Noise fixes:
 Add buffer to the victim net

Command: report_noise

39. How will you fix the crosstalk?

A. Crosstalk fixes:
 Add the buffer
 Shielding
 Re-routing
 Proper NDR rule

40. What is Min period & min pulse width? What is the commands?
How it is report?
A. Min period: When the data path has more number of cells than the
clock path then the data is not able to transfer from launch to capture
because of less number of cells at clock path, then this phenomenon is
known as min period.
Fixes:
  It can be fixed by adding a pair of clock inverter in the clock path.

Command: report_min_period

Min Pulse Width: The clock period width should be wide enough to
capture the data. If we don’t have proper rise and fall then we get min
pulse width.
Fixes:
 It can be fixed by adding a pair of clock inverter in the clock path.
Command: report_min_pulse_width

41. What is DMSA? What are the commands?

A. Distributed Multi-Scenario Analysis (DMSA) can analyze timing
and power in multi-scenario environment in parallel. To invoke prime
time in DMSA, use multi_scenario option.
pt_shell ‘-multi_scenario’
Used for
 Run multiple corners at the same time
 Tool take minimum 3 to 4 hours of runtime for a single
PVT Corner run, so it’s hard to check the design for all
corners within a specific time.
 Hence, enabling DSMA makes tool to check the design at
all corners parallelly in a mean time.

 Used to fix ECO rolling (or) ECO run (or) ECO fire
 If 100 paths are violating, it takes huge time to manually
fix each and every path.
 With the help of DMSA, all the 100 violating path
endpoints are grepped and save into a file. As is inserted
in script of ECO rolling.
 ECO rolling is done at all corners using DMSA.
42. What is ECO’s? What are the commands?
 Engineering Change Order: It will fix the timing violation.
 It will add buffer, upsize, swapping the cells.
 It will be done be done by DMSA tool.

ECO Types:
1. Logical/ Functional ECO
2. Physical ECO
3. Manual ECO
1. Logical / Functional ECO:
 It is rarely used.
 It is used when we want to add any standard cell.
 We are going to remove the filer/ space cell and will add
the logic cell.
2. Physical ECO:
 It is used to fix the timing.
3. Manual ECO:
 We need to fix this manually.

Fixes in ECO:
fix_eco_drc
fix_eco_leakage
fix_eco_power
fix_eco_timing

In prime time, there are two types of ECO commands:

1. fix_eco_drc
2. fix_eco_timing

1. To fix DRV’s and crosstalk and noise

fix_eco_drc
-type max_transition | max_capacitance | max_fanout |
noise | delta_delay | cell_em
 2. To fix timing
fix_eco_timing
-type setup | hold

43. What are the violations you will fix in ECO’s?

A. The violations you fix in ECO’s are DRV’s, SI, timing – setup and
hold.
To fix DRV’s and crosstalk and noise
fix_eco_drc
-type max_transition | max_capacitance | max_fanout | noise |
delta_delay | cell_em
To fix timing
fix_eco_timing
-type setup | hold

44. If you are running 60 corners, how many corners you will run in
ECO’s?

A. If 60 corners are there in the design then we have to run all the 60
corners. In func mode 30 corners & in shift mode 30 corners.
45. How it will be ECO output file? What is the command to get ECO
output file?

A. Fixes or changes of the path report is the output file and this report
given to the PD.

Command: write_changes <filename>

46. What is the order you will follow to fix the violation?
 1. DRVs = Max Transition, Max Capacitance, Max Fanout
2. SI = Crosstalk, Noise, Min Pulse Width, Min Period
3. Timing = Setup and Hold violations

47. Which one is more critical setup /hold, why?

A. Hold violation is more dangerous than setup violation. Because
after timing closure also we can adjust the frequency. So by that we can
avoid setup violation, but hold violation is not dependent on frequency.

48. What is para_114 warning contains?

A. If the annotation occurs in terminal nodes, it is invalid. So prime

time ignores it and shows it as para_114 warning.

49. What are the difference between AOCV & POCV?

5.In AOCV we consider the cell In POCV we consider the cell

delay and net delay. delay, net delay and cell
switching.
6. report_ocvm -type aocvm report_ocvm -type pocvm
50. What are the sanity checks you will do in STA?

A. Netlist:

Check if there are any errors while reading the Verilog file, we
need to check in the log file.

“read_verilog” command is used to read netlist.

Linking Issues: When the inputs in the netlist doesn’t match with
the library file then it is called linking issues. LNK_005 & LNK_006
are the synopsys prime time codes present in the log file if there is a
linking issue. If linking issues are present then inform to pnr team.
SDC: while reading sdc, do you have any errors check in the log
file. “read_sdc” command is used to read SDC inputs.

Check_timing >check_timing.rpt

check_timing: Shows possible timing problems for design.

grep "Information: Checking" checktiming.rpt

Information: Checking 'no_input_delay'.
Information: Checking 'no_driving_cell'.
Information: Checking 'unconstrained_endpoints'.
Information: Checking 'unexpandable_clocks'.
Information: Checking 'latch_fanout'.
Information: Checking 'no_clock'.
Information: Checking 'partial_input_delay'.
Information: Checking 'generic'.
Information: Checking 'loops'.
Information: Checking 'generated_clocks'.
Information: Checking 'pulse_clock_non_pulse_clock_merge'.
Information: Checking 'pll_configuration'.

Check_timing -verbose: This command will give the complete timing

report

SPEF: “read_parasitics” command is used to read spef input.

 All the cells we have should be metal connected.

 Those metal information should be in the spef file.
 While reading the spef file, open nets should not be there.
 The open nets which are not connected are called Annotated
numbers. “read_parasitics”
Command: report_annotated_parasitics -check
51. What are the commands used to fix the timing violation?

A. To fix setup violations:

 VT swap SVT => LVT
pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX2_LVT1
 Upsizing
pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX4_LVT1
 Add high drive strength buffer
pt_shell> insert_buffer
I_CONTEXT_MEM/BINV_RR_237772/Y NBUFFX2_LVT
Cell is added at (854.9840 585.0120).
{I_CONTEXT_MEM/eco_cell}
 pt_shell> remove_buffer I_CONTEXT_MEM/eco_cell1

To fix hold violations:

 VT swap SVT => HVT
 pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX2_HVT1
 Downsizing
pt_shell> size_cell I_RISC_CORE/BUFT_L_215029
NBUFFX2_HVT1
 Add buffer with more delay
pt_shell>insert_buffer
I_CONTEXT_MEM/BINV_RR_237772/Y NBUFFX2_HVT
Cell is added at (854.9840 585.0120).
{I_CONTEXT_MEM/eco_cell}

52. How many clocks are there in your design?

A. There are 12 clocks are there in my design.

Master_clocks: 3

Generated_clocks: 6

Virtual_clocks: 3

NOTE: if they ask this question tell the clock numbers above 10.

53. What is flat and hierarchical design?

A. Hierarchical design has blocks, subblocks and flat design has no

subblocks and it has only leaf cells.

54. What is the difference between clock inverter & buffer and normal
inverter & buffer?
A. The difference between normal buffer, normal inverter and clock
buffer, clock inverter:
 Normal inverter and normal buffer doesn’t have exact 50 –
50% rise and fall time.
 Clock inverter and clock buffer does have the exact 50 – 50%
rise and fall time for 100% sure.
  Clock inverter & clock buffer are faster while normal inverter
and normal buffer are slower.

55. How to get the start point, end point, slack, slew and logic depth?

56. What is setup and hold equation?

Tsetup = TCQ + TCOMB <= TCP –TSU –TUNC + TSKEW (T2 – T1)
Data_path clock_path

Thold = TCQ + TCOMB >= Thold + TUNC + TSKEW (T2 – T1)

Data_path clock_path

57. What is feedthrough?

A. Feedthrough blocks are the communication channels present at the
top chip level with many hierarchical blocks to ensure smooth
interaction between two or more blocks.

58. How to get macro count?

59. What is the difference b/w HVT, LVT, SVT & ULVT?
 HVT: High Threshold Voltage
 Slower in nature
 Leakage power is low
 Used to fix hold violation

LVT: Low Threshold Voltage

 Faster in nature
 Leakage power is high
 Used to fix setup violation

SVT / RVT: Standard Threshold Voltage / Regular Threshold

Voltage
 Medium speed
 Leakage power is medium
 These are not used in the time fixing

ULVT: Ultra Low Threshold Voltage(advanced)

 Instead of LVT we can use ULVT cells since it is working
similar to LVT cells.

60. What is Pre-Layout and Post-Layout STA?

A. Pre Layout STA : Synthesis

Layout STA : Physical Design
Post Layout STA : STA

61. What are Asynchronous commands?

A. The Asynchronous commands are
# Setup asynchronous clock groups
set_clock_groups -name func_asynch -asynchronous \
-group [get_clocks PCI_CLK] \
-group [get_clocks \SD*]
-group [get_clocks SYS*]
62. What is Path-Grouping with commands?
 A group of related paths, grouped either implicitly by the
create_clock command or explicitly by the group_path
command.
 By default, paths whose endpoints are clocked by the same clock
are assigned to the same path group. Path groups affect the
reporting of violations in Prime Time.
Command: create_group_path

63. What is Logical/Physical Exclusive with commands?

A. Logical Exclusive clock: These are the clocks which are
asynchronous to each other but which will be present physically at the
same time.
Command: set_clock_groups - logically_exclusive
Physically Exclusive clock: These are the clocks those are
asynchronous to each other but not be physically present together at the
same time.
Command: set_clock_groups - physically_exclusive

64. Write a format of AND gate defined in .lib file?

A. Example:
pin(Y) {
direction: output;
capacitance: 0.0;
function: "(A B)";
internal_power() {
related_pin: "A";
cell_rise(delay_template_7x7) {
index_1 ("0.04, 0.07, 0.1, 0.2, 0.5, 1.0, 2");
 index_2 ("0.006, 0.030, 0.078, 0.174, 0.366,
0.749,1.523");
values (\
"0.07, 0.09, 0.13, 0.20, 0.35, 0.64, 1.23", \
"0.08, 0.10, 0.13, 0.21, 0.35, 0.65, 1.24", \
"0.09, 0.11, 0.15, 0.22, 0.37, 0.66, 1.25", \
"0.11, 0.13, 0.17, 0.25, 0.39, 0.68, 1.28", \
"0.14, 0.17, 0.20, 0.28, 0.42, 0.72, 1.31", \
"0.18, 0.21, 0.25, 0.33, 0.47, 0.76, 1.35", \
"0.23, 0.26, 0.31, 0.39, 0.54, 0.83, 1.42");
}
(To understand the format of the lookup table, study the template of
timing characteristics template in library)

Here,
index_1 represents input net transition and
index_2 represents total output net capacitance
depending on the various values for these indexes, corresponding delay
values are looked up from the table
here, table can be any size 3 x 3, 7 x 7 etc depending upon the library
vendor.
Now, how it work lets understand with the following example
here,
- 7 x 7 indicates the size of the lookup table to be 7 rows and 7 columns
- index_1 indicates the factor for row indices
- index_2 indicates the factor for column indices

what would the cell_rise time be if the input_net_transition is 0.1 and

the total_ouptut net capacitance is 0.030?
answer: from the table, we get the value to be 0.11ps.

65. What is SDF?

A. SDF full form is Standard Delay Format.
 It is in the form of .sdf file.
 SDF file is how you represent the circuit delays.
 SDF contains timing information of all the cells in the design.
  It gives accurate delays for each component in the layout
database.

66. What is BTO & MTO? What is its difference?

A. BTO full form is Base Tape Out. In BTO we will fix clock tran,
data tran, glitch, timing - setup & hold, drc, lvs, RC violations.
MTO full form is Metal Tape Out. In MTO we will fix metal drc if
there is any.

67. What are the inputs required for ECO’s?

A. The inputs required for ECO’s are
 Gate level netlist
 SDC
 SPEF
 DEF
 Library
 MMMC
 UPF.

68. Do you know Tweaker?

A. Tweaker is the same as ECO but it is an advanced version of
ECO.
69.Linking issue is an error or warning?
A. Linking issue is a warning i.e., LNK-005 and LNK-006 are
Synopsys Prime Time Codes.

70. What is the pt – version you used?

A. R-2020.09-Sp2 for linux 64

71. How to read the input in prime time? What are the commands?
A. To read the inputs in prime time:
 For Netlist (.v)  read_verilog
  For SDC (.sdc)  read_sdc
 For SPEF (.spef)  read_parasitics
 For DEF (.def)  read_def
 For Library (.lib)  read_db
 For MMMC  source mmmc.tcl

72. Which db you will fix timing?

A. In Routing db you can fix the timing.

73. What is difference in placement, CTS & routing?

A. The difference between placement, CTS and routing are
 In placement stage, we will place the standard cells and clock is
ideal. So, only setup timing can be checked in placement.
 In CTS stage, the clock is present. So, setup and hold timing can
be checked in the CTS stage.
 In routing stage, we can get the exact RC numbers and also the
clock is present. So, setup and hold timing can be checked in the
routing stage.

74. What does Netlist contains?

A. Netlist contains the following information:
 It is in the form of .v file i.e., verilog file.
 The Verilog file contains the logic information and connectivity.
 It tells for which module which clock has to be connected.

75. Instead of generated clock why can’t we define master clock?

A. If we give master clock instead of generated clock then cost
increases due to space and power supply and define area, port.
76. What does SPEF file contains?
A. SPEF full form is Standard Parasitic Extraction Format.
 It is in the form of .spef file.
 SPEF contains RC information, cells connectivity and net
information.
 Each net information will be available here.
 Each metal has the RC numbers.
 We need corners for all spefs. For example, if we have 32 corners
then we need 32 spefs.
 It consists of R & C information for all signal, clock and power
nets.

77. What is temperature inversion?

A. In lower nodes, the delay of the cell decreases with an increase in
temperature. So, in the lower technology node, the effect of
temperature on the delay of the cell is inverted and this effect is called
the temperature inversion.

78. If you have 1000 violations how will you fix those?
 If 1000 paths are violating, it takes huge time to manually fix
each and every path.
 With the help of DMSA, all the 1000 violating path endpoints
are grepped and save into a file. As is inserted in script of ECO
rolling.
 ECO rolling is done at all corners using DMSA.

79. What is PBA Exhaustive?

A. pba_exhaustive command means to check GBA.
80. What is the command to get full clock expanded? (to see the clock
path)
A. report_min_period -path_type full_clock_expanded

81. If you have same path setup and hold violation what you will do
and how to fix that?
 It is possible to have both setup/hold violations on the same
reg2reg path: if you have big "delta delay", which is due to big
coupling capacitance on some nets in the path.
 During setup analysis, the tool add this "delta delay" to the total
path length (so you may have setup violations).
 During hold analysis the tool subtract “delta delay” from the total
path length.
 Try to minimize the coupling capacitance (increase wire spacing
or change the metal layer).

82. What is the setup and hold margin for tapeout?

A. The setup and hold margin for tapeout is 0 ps.

83. What is check-list? While tape out time?

A. Final tapeout check-list:
 Clocks
 Resets
 Interfaces
 Power supplies
 Layout
 I/O and esd.
84. What is the difference between 16nm & 10nm & 7nm? What you
observed?
A. In lower technology nodes, the complexity increases as the size
of the chip decreases and number of standard cells count increases but
in the higher technology nodes the complexity is less and also the
number of standard cells count also decreases.

85. What are clock groupings?

A. There are 4 types of clock groupings.
1. Synchronous clocks
2. Asynchronous clocks
3. Logically exclusive
4. Physically exclusive

86. What are the start and end points of a path?

A. Startpoint must be an input port or a register clock pin.
Endpoint must be a register data input pin or an output port.

87. In which path you will give fixed derate values for setup and hold?
A. SETUP: Data path – 1.05
Clock path – 0.95
HOLD: Data path – 0.95
Clock path – 1.05

88. What is clock push and clock pull?

A. Clock pulling: Add the cells in the launch clock path.
Clock pushing: Add the cells in the capture clock path.

89. What and all are there between start point and end point in report?
 Check start points and endpoints should be of same clock source.
 Check path type i.e., max for setup and min for hold.
 Check slack, if slack is violating.
 Check the skew number.
 Check the logic depth - the cells are present in Tcombo.
 Check the type of cells like LVT, HVT, SVT and drive strength in
data path.
 Check the network latency number & CRPR & uncertainty in clock
path.
 Based on the data path check the max tran value.

90. What are the 10 ways to fix setup violations?

A. 1. HVT swap means change HVT cells into SVT/RVT cells or LVT
cells.
2. Upsize the cell means to increase the drive strength.
3. Reduce the amount of buffering in the path.
4. Replace buffers with 2 inverters place farther apart.
5. Inserting buffers.
6. Inserting repeaters.
7. Adjust cell position in layout.
8. Clock skew.