COMPUTER ORGANIZATION AND

ARCHITECTURE (COA)

EET 2211
4TH SEMESTER – CSE & CSIT
CHAPTER 9,10,11; LECTURE 39
By Ms. Arya Tripathy
 William Stallings Computer
Organization and
Architecture
10th Edition

Chapters - 9,10,11

2 ARITHMETIC & LOGIC 7/16/2021

 CHAPTER 9 – THE DECIMAL SYSTEM

TOPICS TO BE COVERED
Ø The decimal system
Ø The Binary System
Ø Converting Between Binary and Decimal
Ø Hexadecimal Notation

LEARNING OBJECTIVES
Ø Understand the basic concepts and terminology of positional number
systems.
Ø Explain the techniques for converting between decimal and binary for
both integers and fractions.
Ø Explain the rationale for using hexadecimal notation.

3 ARITHMETIC & LOGIC 7/16/2021

 Decimal Number System
 Base (also called radix) = 10
 10 digits { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }
 Digit Position
2 1 0 -1 -2
 Integer & fraction
 Digit Weight 5 1 2 7 4
Position
 Weight = (Base)
100 10 1 0.1 0.01
 Magnitude
 Sum of “Digit x Weight”
 Formal Notation
500 10 2 0.7 0.04

d2*B2+d1*B1+d0*B0+d-1*B-1+d-2*B-2

(512.74)10
4 ARITHMETIC & LOGIC 7/16/2021
 Binary Number System
 Base = 2
 2 digits { 0, 1 }, called binary digits or “bits”
 Weights
Position 4 2 1 1/2 1/4
 Weight = (Base)
 Magnitude
1 0 1 0 1
 Sum of “Bit x Weight” 2 1 0 -1 -2
 Formal Notation 1 *22+0 *21+1 *20+0 *2-1+1 *2-2
 Groups of bits =(5.25)10
4 bits = Nibble
(101.01)2

5 ARITHMETIC & LOGIC 7/16/2021

 Hexadecimal Number System
 Base = 16
 16 digits { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F }
 Weights
Position 256 16 1 1/16 1/256
 Weight = (Base)
 Magnitude 1 E 5 7 A
 Sum of “Digit x Weight” 2 1 0 -1 -2
 Formal Notation 1 *162+14 *161+5 *160+7 *16-1+10 *16-2
=(485.4765625)10

(1E5.7A)16

6 ARITHMETIC & LOGIC 7/16/2021

 Decimal to Binary Conversion
 Divide the number by the ‘Base’ (=2)
 Take the remainder (either 0 or 1) as a coefficient
 Take the quotient and repeat the division

Example: (13)10 Quotient Remainder Coefficient

13 / 2 = 6 1 a0 = 1
6 /2= 3 0 a1 = 0
3 /2= 1 1 a2 = 1
1 /2= 0 1 a3 = 1
Answer: (13)10 = (a3 a2 a1 a0)2 = (1101)2

7 ARITHMETIC & LOGIC 7/16/2021

 Decimal (Fraction) to Binary Conversion
 Multiply the number by the ‘Base’ (=2)
 Take the integer (either 0 or 1) as a coefficient
 Take the resultant fraction and repeat the division

Example: (0.625)10 Integer Fraction Coefficient

0.625 * 2 = 1 . 25 a-1 = 1
0.25 * 2 = 0 . 5 a-2 = 0
0.5 *2= 1 . 0 a-3 = 1
Answer: (0.625)10 = (0.a-1 a-2 a-3)2 = (0.101)2

8 ARITHMETIC & LOGIC 7/16/2021

 REVIEW QUESTIONS

9 ARITHMETIC & LOGIC 7/16/2021

 Contd.

10 ARITHMETIC & LOGIC 7/16/2021

 CHAPTER 10 – COMPUTER ARITHMETIC
TOPICS TO BE COVERED
Ø Integer Representation
Ø Integer Arithmetic
Ø Floating-Point Representation
Ø Floating-Point Arithmetic

LEARNING OBJECTIVES
Ø Understand the distinction between the way in which numbers are represented
(the binary format) and the algorithms used for the basic arithmetic operations.
Ø Explain two’s complement representation.
Ø Understand base and exponent in the representation of floating-point numbers.
Ø Present an overview of the IEEE 754 standard for floating-point representation.

11 ARITHMETIC & LOGIC 7/16/2021

 Integer Representation

• Only have 0 & 1 to represent everything

• Positive numbers stored in binary
e.g. 41=00101001
• No minus sign
• No period
• Sign-Magnitude
• Two’s compliment

12 ARITHMETIC & LOGIC 7/16/2021

 Sign-Magnitude
• Left most bit is sign bit
• 0 means positive
• 1 means negative
+18 = 00010010
-18 = 10010010
• Problems
Need to consider both sign and magnitude in arithmetic
Two representations of zero (+0 and -0)

13 ARITHMETIC & LOGIC 7/16/2021

 Two’s Complement
•It uses the MSB as a sign bit, making it easy to test
whether an integer is positive or negative.
• +3 = 00000011
• +2 = 00000010
• +1 = 00000001
• +0 = 00000000
• -1 = 11111111
• -2 = 11111110
• -3 = 11111101

14 ARITHMETIC & LOGIC 7/16/2021

 Range of Numbers
• 8 bit 2s compliment
+127 = 01111111 = 27 -1
-128 = 10000000 = -27
• 16 bit 2s compliment
+32767 = 011111111 11111111 = 215 - 1
-32768 = 100000000 00000000 = -215

15 ARITHMETIC & LOGIC 7/16/2021

 Addition and Subtraction
• Normal binary addition

• Monitor sign bit for overflow

• Take twos compliment of substahend and add to minuend
i.e. a - b = a + (-b)

• So we only need addition and complement circuits

16 ARITHMETIC & LOGIC 7/16/2021

Hardware for Addition and Subtraction

17 ARITHMETIC & LOGIC 7/16/2021

 Multiplication
ü It is a complex operation whether performed on hardware or
software, compared with addition and subtraction.
ü Important features of multiplication are:
1. It involves the generation of partial products, one for each
digit in the multiplier.
2. The partial products are easily defined.
3. The total product is produced by summing the partial
products.
4. The multiplication of two n-bit binary integers results in a
product of up-to 2n bits in length.

18 ARITHMETIC & LOGIC 7/16/2021

 Unsigned Binary Multiplication

19 ARITHMETIC & LOGIC 7/16/2021

 Flowchart for Unsigned Binary Multiplication

20 ARITHMETIC & LOGIC 7/16/2021

 Multiplying Negative Numbers

• This does not work!

• Solution 1
Convert to positive if required
Multiply as above
If signs were different, negate answer
• Solution 2
Booth’s algorithm

21 ARITHMETIC & LOGIC 7/16/2021

 Booth’s Algorithm

22 ARITHMETIC & LOGIC 7/16/2021

 Example of Booth’s Algorithm

23 ARITHMETIC & LOGIC 7/16/2021

 Division
• More complex than multiplication
• Negative numbers are really bad!
• Based on long division

Division of Unsigned Binary Integers

24 ARITHMETIC & LOGIC 7/16/2021

Flowchart for Unsigned Binary Division

25 ARITHMETIC & LOGIC 7/16/2021

 Real Numbers
• Numbers with fractions
• Could be done in pure binary
1001.1010 = 24 + 20 +2-1 + 2-3=9.625
• Where is the binary point?
• Fixed?
Very limited
• Moving?
How do you show where it is?

26 ARITHMETIC & LOGIC 7/16/2021

 Floating Point

• +/- .significand x 2exponent

• Misnomer
• Point is actually fixed between sign bit and body of mantissa
• Exponent indicates place value (point position)

27 ARITHMETIC & LOGIC 7/16/2021

 Floating Point Examples

28 ARITHMETIC & LOGIC 7/16/2021

 Signs for Floating Point
• Mantissa is stored in 2s compliment
• Exponent is in excess or biased notation
e.g. Excess (bias) 128 means
8 bit exponent field
Pure value range 0-255
Subtract 128 to get correct value
Range -128 to +127

29 ARITHMETIC & LOGIC 7/16/2021

 Normalization
• FP numbers are usually normalized
i.e. exponent is adjusted so that leading bit (MSB) of
mantissa is 1
• Since it is always 1 there is no need to store it
(c.f. Scientific notation where numbers are normalized
to give a single digit before the decimal point
e.g. 3.123 x 103)

30 ARITHMETIC & LOGIC 7/16/2021

 FP Ranges
• For a 32 bit number
8 bit exponent
+/- 2256 1.5 x 1077
• Accuracy
The effect of changing LSB of mantissa
23 bit mantissa 2-23 1.2 x 10-7
About 6 decimal places

31 ARITHMETIC & LOGIC 7/16/2021

 Expressible Numbers

32 ARITHMETIC & LOGIC 7/16/2021

 IEEE 754
• Standard for floating point storage
• 32 and 64 bit standards
• 8 and 11 bit exponent respectively
• Extended formats (both mantissa and exponent) for
intermediate results
IEEE 754 Formats

33 ARITHMETIC & LOGIC 7/16/2021

 FP Arithmetic +/-
• Check for zeros
• Align significands (adjusting exponents)
• Add or subtract significands
• Normalize result

34 ARITHMETIC & LOGIC 7/16/2021

 FP Addition & Subtraction Flowchart

35 ARITHMETIC & LOGIC 7/16/2021

 FP Arithmetic x/÷
• Check for zero
• Add/subtract exponents
• Multiply/divide significands (watch sign)
• Normalize
• Round
• All intermediate results should be in double length
storage

36 ARITHMETIC & LOGIC 7/16/2021

 Floating Point Multiplication

37 ARITHMETIC & LOGIC 7/16/2021

 Floating Point Division

38 ARITHMETIC & LOGIC 7/16/2021

COMBINATIONAL CIRCUITS
• Combinational circuit is a circuit in which we combine the
different gates in the circuit, for example encoder, decoder,
multiplexer and demultiplexer.
• Some of the characteristics of combinational circuits are
following:
ü The output of combinational circuit at any instant of time,
depends only on the levels present at input terminals.
ü The combinational circuit do not use any memory. The
previous state of input does not have any effect on the present
state of the circuit.
ü A combinational circuit can have an n number of inputs and m
numbe of outputs.

ARITHMETIC & LOGIC 7/16/2021

39
COMBINATIONAL CIRCUITS
• Block diagram:
possible combinations of input values.

• Specific types of combinational circuits: Adders, subtractors,

multiplexers, comprators, encoder, decoder.

40 ARITHMETIC & LOGIC 7/16/2021

ANALYSIS PROCEDURE
Analysis procedure
To obtain the output Boolean functions from a logic diagram,
proceed as follows:
• Label all gate outputs that are a function of input variables
with arbitrary symbols. Determine the Boolean functions
for eachgate output.
• Label the gates that are a function of input variables and
previously labeled gates with other arbitrary symbols.
Find the Boolean functions for these gates.
• Repeat the process outlined in step 2 until the outputs of the
circuit are obtained.

41 ARITHMETIC & LOGIC 7/16/2021

DESIGN PROCEDURE

• The problem is stated.

• The number of available input variables and requiredoutput
variables is determined.
• The input and output variables are assigned lettersymbols.
• The truth table that defines the required relationship between
inputs and outputs is derived.
• The simplified Boolean function for each output is obtained.
• The logic diagram is drawn.

42 ARITHMETIC & LOGIC 7/16/2021

BINARY ADDERS
Full Adder
The full-adder adds the bits A and B and the carry from the
previous column called the carry-in Cin and outputs the sum bit
S and the carry bit called the carry-out Cout .

Fig 3: block diagram Fig 4:Truth table

43 ARITHMETIC & LOGIC 7/16/2021

PARALLEL ADDER AND SUBTRACTOR
A binary parallel adder is a digital circuit that adds two binary
numbers in parallel form and produces the arithmetic sum of
those numbers in parallel form

parallel adder

44 ARITHMETIC & LOGIC 7/16/2021

DECODER

• A binary decoder is a combinational logic circuit that converts binary

information from the n coded inputs to a maximum of 2 n unique
outputs.
• We have following types of decoders 2x4,3x8,4x16….
2x4 decoder

Fig 1: Block diagram Fig 2:Truth table

45 ARITHMETIC & LOGIC 7/16/2021

 DECODERS
Higher order decoder implementation using lower order.
Ex:4x16 decoder using 3x8 decoders

46 ARITHMETIC & LOGIC 7/16/2021

 MULTIPLEXERS
• Multiplexer is a combinational circuit that has maximum of 2n data
inputs, ‘n’ selection lines and single output line. One of these data
inputs will be connected to the output based on the values of
selection lines.
• We have different types of multiplexers 2x1,4x1,8x1,16x1,32x1……

Fig 1: Block diagram Fig 2: Truth table

47 ARITHMETIC & LOGIC 7/16/2021

 MULTIPLEXERS

Fig 3: Logic diagram

48 ARITHMETIC & LOGIC 7/16/2021

 SEQUENTIAL LOGIC CIRCUITS

Sequential logic circuit consists of a combinational circuit with

storage elements connected as a feedback to combinational circuit
• output depends on the sequence of inputs (past and present)
• stores information (state) from past inputs

Figure 1: Sequential logic circuits

49 ARITHMETIC & LOGIC 7/16/2021

FLIPFLOPS:EXCITATION FUNCTIONS
SR Flip flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

50 ARITHMETIC & LOGIC 7/16/2021

 FLIPFLOPS:EXCITATION FUNCTIONS

JK Flip flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

51 ARITHMETIC & LOGIC 7/16/2021

 FLIPFLOPS:EXCITATION FUNCTIONS

D Flip flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

52 ARITHMETIC & LOGIC 7/16/2021

 FLIPFLOPS:EXCITATION FUNCTIONS

T Flip flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

53 ARITHMETIC & LOGIC 7/16/2021

CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF SR FLIP FLOP TO JK FLIPFLOP

J and K will be given as external inputs to S and R. As shown in

the logic diagram in next slide, S and R will be the outputs of the
combinational circuit. The truth tables for the flip flop conversion
are given . The present state is represented by Qp and Qp+1 is the
next state to be obtained when the J and K inputs are applied. For
two inputs J and K, there will be eight possible combinations. For
each combination of J, K and Qp, the corresponding Qp+1 states
are found. Qp+1 simply suggests the future values to be obtained
by the JK flip flop after the value of Qp. The table is then
completed by writing the values of S and R required to get each
Qp+1 from the corresponding Qp. That is, the values of S and R
that are required to change the state of the flip flop from Qp to
54 Qp+1 are written.
ARITHMETIC & LOGIC 7/16/2021
CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

55 ARITHMETIC & LOGIC 7/16/2021

SHIFT REGISTERS
Introduction :
Shift registers are a type of sequential logic circuit, mainly for storage
of digital data. They are a group of flip-flops connected in a chain so
that the output from one flip-flop becomes the input of the next flip-
flop. Most of the registers possess no characteristic internal sequence
of states. All the flip-flops are driven by a common clock, and all are
set or reset simultaneously. Shift registers are divided into four types.
1. SISO SR (serial in – serial out shift register)
2. SIPO SR (serial in – parallel out shift register)
3. PISO SR (Parallel in – serial out shift register)
4. PIPO SR (parallel in – parallel out shift register)

56 ARITHMETIC & LOGIC 7/16/2021

PROGRAMMABLE LOGIC DEVICES
Programmable Logic Array
Ø A programmable logic array (PLA) is a type of logic device that
ca n b e p ro g ra mme d to i m p l e m e nt va r i o u s k i n d s o f
combinational logic circuits.

Ø The device has a number of AND and OR gates which are

linked together to give output or further combined with more
gates or logic circuits.

57 ARITHMETIC & LOGIC 7/16/2021

PROGRAMMABLE LOGIC ARRAY
Programmable LogicArray

Fig 1: Block diagram of PLA

58 ARITHMETIC & LOGIC 7/16/2021

PROGRAMMABLE LOGIC ARRAY
PLA
F1 =AB’+AC+A’BC’
F2 = (AC+BC)’

Fig 2: PLA with 3-inputs 4 product terms and 2

outputs

59 ARITHMETIC & LOGIC 7/16/2021

PROGRAMMABLE LOGIC ARRAY
Simplification of PLA
• Careful investigation must be undertaken in order to reduce the
number of distinct product terms, PLA has a finite number of
AND gates.

• Both the true and complement of each function should be

simplified to see which one can be expressed with fewer
product terms and which one provides product terms that are
common to other functions.

60 ARITHMETIC & LOGIC 7/16/2021

PROGRAMMABLE LOGIC ARRAY
Example
Implement the following two Boolean functions with a PLA:
F1(A, B,C) = ∑ (0, 1, 2, 4)
F2(A, B, C) = ∑ (0, 5, 6, 7)

The two functions are simplified in the maps of given figure

61 ARITHMETIC & LOGIC 7/16/2021

PROGRAMMABLE LOGIC ARRAY
PLA table by simplifying the function

• Both the true and complement of the

functions are simplified in sum of
products.
• We can find the same terms from the
group terms of the functions of F1,
F1’,F2 and F2’ which will make the
minimum terms.
F1 = (AB +AC + BC)’
F2 = AB + AC + A’B’C’
Fig 1: Solution to example

62 ARITHMETIC & LOGIC 7/16/2021

 PROGRAMMABLE LOGIC ARRAY
PLA implementation
 THANK YOU

64 ARITHMETIC & LOGIC 7/16/2021