Interrupts

Module IV

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• An interrupt is a process in which a microprocessor is asked to suspend its current
operations and execute an emergency operation.
• Interrupt is a process where an external device can get the attention of the microprocessor.
• An interrupt is a subroutine call initiated by an external device through hardware (hardware
interrupt) or the microprocessor (software interrupt).
• An interrupt is an asynchronous signal from hardware indicating the need for attention or a
synchronous event in software indicating the need for a change in the execution.
• The software interrupts are not requested by external peripheral devices.
• Interrupt request is an asynchronous event that can occur at any time during the execution
of the program.
• In response to an interrupt request, the microprocessor executes the current instruction
and then acknowledges the interrupt.
• The microprocessor saves the contents of the program counter on top of the stack and
then transfers its control to interrupt the service routine.
• The microprocessor executes (interrupt service routine) ISR to service the interrupting
device. After executing the interrupt, the microprocessor transfers its control back to the
main program.

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Advantages of Interrupts
• Interrupts provide flexibility to the user so that higher programs can
be executed out of turn.
• Interrupts do not have to be synchronized with the main program.
• Interrupts are used to ensure sufficient service response times by the
processing.
• The use of interrupts guarantees that the processor will service the
request within a specified period.

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Interrupt Systems
• Single-level or single-line interrupt system
• Multilevel or multiline Interrupts system

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 1. Single Line or Single Level Interrupt System
• In single-level or single-line interrupt configuration, the microprocessor provides
only one interrupt request input line.
• Many I/O devices are connected to this interrupt request line.
• The interrupts from many devices are ORed together and then applied to the
microprocessor. In response to an interrupt from any of the Ored devices, the
microprocessor executes the following steps:

1. Transfer the control to an interrupt processing routine called interrupt level

subroutine (ILS).
2. Determine the address of the interrupting device.
3. Transfer the control of the ISR and execute the interrupt service routine (ISR).
4. Return to the main program, enable the maskable interrupts, and resume
execution.

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2. Multilevel or Multiline Interrupt System
• In this system, the individual request lines from I/O devices are connected
to different interrupt request lines. The microprocessor can accept other
interrupt requests during the execution of an ISR.
• If the microprocessor has only one interrupt input, the interrupt control
logic resolves the priority of interrupt requests and higher priority
interrupts are services first. During the execution of the higher priority
interrupt, the lower priority interrupts are kept in waiting.
• A much higher priority interrupt is allowed during the execution of the
higher priority interrupt.

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 Classification of Interrupts
1. Edge Triggered and Level Triggered
• Edge TI are recognized on the falling or rising edge of the input signal.
• They are generally used for high-priority interrupts and an internal flip-flop is
used to latch such types of interrupts. Due to its short duration, the processor
could miss the falling edge and thus not respond to the interrupt request if the
latching is not done by the internal flip-flop. In 8086, NMI is an edge-triggered
interrupt.
• In level TI, the requesting device holds the interrupt line at a specified logic state
till the processor acknowledges the interrupt. The problem of latching is
overcome by these types of interrupts. These types of interrupts can be shared by
other devices in a wired ‘OR’ configuration, which is commonly used to support
daisy chaining and other techniques. In 8086, INTR is a level triggered interrupt.
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 2. Maskable and Non-maskable
• Maskable interrupts are those interrupts that can be masked or to which the
service can be denied.
• In 8086 INTR is a maskable interrupt, which is a level-triggered interrupt. This
interrupt can be masked by resetting the IE flag bit of the flag register.
• Once masked the signal at this pin of 8086 is not polled by the processor.
These interrupts are associated with low-priority tasks which can be ignored.
• The non-maskable interrupts are those interrupts that cannot be masked or
ignored by the processor. These are associated with high-priority tasks that
cannot be ignored. Each processor supports the non-maskable interrupt
(NMI). This interrupt has the highest priority. In 8086, NMI is the non-
maskable interrupt which is an edge-triggered interrupt.
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3. Hardware and Software Interrupts
• 8086 has 2 hardware interrupts, namely NMI and INTR, whereas, it
has 256 software interrupts which can be generated by the software
instruction INTn.

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4. Vectored and Non-Vectored Interrupts
• Vectored interrupts are those interrupts whose interrupts service
routing (ISR) addresses are stored in a predefined memory location
(IVT), whereas, non-vectored interrupts are those for which the ISR
address is provided by the interrupting devices.
• All interrupts in 8086, whether hardware or software except INTR,
are vectored interrupts.

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 Some examples of Interrupts of 8086
• An interrupt can be generated as a result of an error in the execution of an instruction.
• An example would be a divide-by-zero interrupt produced when the DIV instruction is
interpreted to have a zero divisor.
• The program execution is automatically interrupted and control is transferred to an interrupt
handler. Conditional interrupts such as these are called internal interrupts.
• An interrupt can also be generated by an external device that wants to be serviced first. The
external device signals its request on either the non-maskable interrupt (NMI) or on the INTR
interrupt input line of the microprocessor. The NMI interrupt is generally used to signal the
occurrence of a catastrophic event, such as a power failure. The INTR interrupt is used by all
other devices. An interrupt caused by a signal applied to either the NMI or INTR input is
referred to as a hardware interrupt.
• Since there is only one INTR input, and multiple devices may have an interrupt capability, an
Intel 8259A programmable interrupt controller (PIC) can be used to manage multiple
interrupt requests. The PIC receives requests from peripheral equipment, decides which
request has the highest priority, and issues an interrupt request to the microprocessor.
• Lastly, interrupts may be generated as a result of executing the INT or INT0 instructions. This
is called software interrupt.
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Whenever an interrupt is acknowledged, the processor goes through the
following sequences of events before executing the ISR.

• The flag register is pushed onto the stack.

• The INTR inputs are disabled and TF is also cleared.
• The CS register is pushed onto the stack.
• The IP register is pushed onto the stack.
• The IP and CS registers are loaded with the interrupt vector address offset
and segment address respectively.
• The ISR is executed from the address formed by the new CS and IP
registers.
• When the last instruction return from interrupt (IRET) of the ISR is
executed, the pushed registers, i.e., flag register, CS, and IP register are
popped off the stack in the reverse order. This returns the microprocessor
execution to the original process.
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Interrupt Vector/ Pointer Table
• The 8086 can service upto 256 different interrupts. The base and
offset words for all these interrupt types are grouped together in an
interrupt vector table (IVT).
• In 8086, the first 1K memory locations starting with 00000H to
003FFH are set aside for this IVT. As each ISR address consists of four
bytes containing the code segment (CS) and instruction pointer (IP) of
the first instruction in the interrupt service routine, hence this
interrupt pointer table can store the addresses of 256 different
interrupts. Each interrupt, whether hardware or software or any
other, is given a type number, 0 through 255, corresponding to its
position in the IVT.

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Find the physical address in the IVT
associated with INT13, INT8

• INT 13H=52=34H, 00034H to 00037H

• INT 8=32=20H, 00020H to 00023 H

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Interrupt Controlled I/O

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Dedicated Interrupts

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 8259
Programmable Interrupt Controller (PIC)

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Programmable Interrupt Controller 8259

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Architecture of PIC 8259

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 8255
Programmable Peripheral Interface (PPI)

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Architecture of 8255

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I/O Map of 8255
Ports A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

PA 1 0 0 0 0 0 0 0 80 H
PB 1 0 0 0 0 0 1 0 82 H
PC 1 0 0 0 0 1 0 0 84 H
CW 1 0 0 0 0 1 1 0 86 H

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1. I/O Command Word

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2. BSR Command

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For ports, I/O Addressing Modes of 8086 are used

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Data Transfer Modes of 8255

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Mode 1 Input Transfer

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Mode 1 Output Transfer

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Mode 2 Bidirectional Transfer

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Interfacing of 8086 with 8255

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 Interfacing of 4X4 Matrix
Keyboard to 8086 using 8255

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