07-06-2022

Data Path Subsystems and

Sequential Circuit Design
[ UNIT 4 ]

ADDERS
• The following types of binary adder • The simplest adder is a half- adder
circuits will be discussed: which adds two bits.
• Half Adder • A full adder adds two bits along with
• Full Adder one input carry.
• Ripple Carry Adder (RCA) • A Ripple carry adder is used to add
• Carry Look-ahead Adder (CLA) two N-bit numbers.
• Carry-skip Adder (CSKA) • A Carry Look-ahead adder is a high
• Adders are the most fundamental speed adder that does not wait for
subsystems of a digital circuit. each stage to generate carry signals.
• A binary adder adds two binary • A carry-skip adder is an
inputs and produces the SUM and implementation that improves on the
CARRY as outputs. delay of RCA with little effort
compared to other adders.

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DESIGN OF CMOS HALF ADDER CIRCUIT

• A half adder adds two bits at a time and produces SUM
and CARRY.
• Note: To get SUM output we have to implement XNOR gate.
Sum = A ⊕ B ; Carry = 𝐴 . 𝐵

DESIGN OF CMOS FULL ADDER CIRCUIT

• A Full Adder circuit has three inputs
A , B and Carry-in (Cin) and two outputs
SUM and CARRY-OUT (Cout).
• The truth table of the full adder is
shown in Fig. 1
• Boolean expressions for the SUM and COUT
are given by

• Taking 𝐶𝑂𝑈𝑇 as input, we can simplify the

expression for SUM as

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RIPPLE CARRY ADDER (RCA)

• A RCA is used to add two N-bit numbers.
• Block diagram of a 4-bit RCA is shown in figure.
• It requires N-Full Adders in its circuit for adding
two N-bit numbers.
• It is also known as N-bit parallel adder.
• Ripple Carry Adder works in different stages.
• Each full adder takes the carry-in as input and
produces carry-out and sum bit as output.
• The carry-out produced by a full adder serves as
carry-in for its next most significant full adder.
• When carry-in becomes available to the full
adder, it activates the full adder.
• Each carry bit ripples or waves into the next
stage.

RIPPLE CARRY ADDER (RCA)

DISADVANTAGES OF RCA:
• Ripple Carry Adder does not allow to use all the
full adders simultaneously.
• Each full adder has to necessarily wait until the
carry bit becomes available from its previous full
adder stage.
• Thus, nth full adder has to wait until all (n-1) full
adders have completed their operations.
• This increases the propagation time.
• Due to this reason, ripple carry adder becomes
extremely slow.
• The situation becomes worst when the value of
‘N’ becomes very large.
• This is considered to be the biggest disadvantage
of using ripple carry adder.

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CARRY LOOK-AHEAD ADDER (CLA) • So, the carry-in of any stage full adder can be
evaluated at any instant of time.
• To overcome the disadvantage of RCA, Carry • Thus, any full adder need not wait until its carry-
Look-Ahead adder is used. in is generated by its previous stage full adder.
• CLA is an improved version of the ripple carry • Let Gi = AiBi where ‘G’ is called carry generator.
adder. Pi = Ai ⊕ Bi where ‘P’ is called carry propagator.
• It generates the carry-in of each full adder • Then, re-writing the above equations, we have-
simultaneously without causing any delay.
• The working of CLA ahead adder is based on the
principle: • C1 = C0P0 + G0 ………….. (1)
The carry-in of any stage full adder is independent of
the carry bits generated during intermediate stages.
• C2 = C1P1 + G1 ………….. (2)
• The carry-in of any stage full adder depends only
on the following two parameters-
• Bits being added in the previous stages • C3 = C2P2 + G2 ………….. (3)
• Carry-in provided in the beginning
• The above two parameters are always known • C4 = C3P3 + G3 ………….. (4)
from the beginning.

CARRY LOOK-AHEAD ADDER (CLA)

• Finally, we have the following equations-
C1 = C0P0 + G0
C2 = C0P0P1 + G0P1 + G1
C3 = C0P0P1P2 + G0P1P2 + G1P2 + G2
C4 =C0P0P1P2P3 + G0P1P2P3 + G1P2P3 + G2P3 + G3
• These above equations show that the carry-in of any
stage of full adder depends only on:
• Bits being added in the previous stages
• Carry bit which was provided in the beginning
• For a n-bit CLA to evaluate all the carry bits, it
requires:
• Number of AND gates = n(n+1) / 2
• Number of OR gates = n
• The advantages of carry look ahead adder are:
• It generates the carry-in for each full adder
simultaneously.
• It reduces the propagation delay.

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Fig: Carry Skip Adder Logic

CARRY SKIP ADDER
(CSKA)
• A carry-skip adder (also known
as a carry-bypass adder) is an
adder implementation that
improves on the delay of ripple
carry adder with little effort
compared to other adders.
• The improvement of the worst-case delay is achieved
by using several carry-skip adders to form a block-
carry-skip adder
• Carry Skip Adder allows carry to skip over group of N-
bits.
• Decision is based on N-bit propagate signal.
• Unlike other fast adders, carry-skip adder performance
is increased with only some of the combinations of
input bits.
• This means, speed improvement is only probabilistic.

CARRY SKIP ADDER (CSKA) Fig: Pass Transistor Logic

Implementation of Carry Skip Adder Logic
ADVANTAGES:
• The latency of the adder is reduced through its
critical path, since the carry bit for each block can
now "skip" over blocks with a group propagate
signal set to logic 1.
• In higher bit operation the circuit response is good.
• The carry skip adder makes arithmetic
computation faster compared to RCA.
DISADVANTAGES:
• It can skip carry only when all bits are in
propagation condition.
• It has high delay, power consumption in lower bit
operation
• It is not sure that always every input bits are in
carry propagation condition.
Fig: Block level implementation of
16-Bit Carry Skip Adder.

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Fig 1: Example of Conventional Addition

CARRY SAVE ADDER (CSA) and CSA addition method.

• A carry save adder is very useful for adding more 1. Conventional Method
than two binary numbers.
• Hence it is particularly useful in a multiplier circuit,
where more than two partial products are added to
obtain the final output.
• The concept of CSA is illustrated in example of Fig 1.
• The advantage of the second approach is clear
when we add more than two number.
• Another example of adding three numbers is shown 2. CSA Method
in Fig 2. [Next Slide]
• We see that in Fig 3. the final result can be obtained
by adding the sum bits and carry bits using the
Ripple-Carry addition technique. [Next Slide]
• A CSA is used in multiplier circuits.

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Fig 2: Addition of THREE numbers using CSA.

CARRY SAVE ADDER (CSA)

• The block diagram of a 4-bit CSA is shown in fig 3.

• There are four inputs A,B,C,D of 4-bit each.
• The first three inputs A,B and C are added by the
carry-save stage1. Fig 3: Block Diagram of 4-bit CSA
• Then the carry-save stage2 adds the sum bits with
the remaining input D, along with the carry bits.
• The final result is obtained after the RCA adds the
sum and carry bits obtained through carry-save
stage2.

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MULTIPLIERS Fig 4: Multiplication example in binary

• The most basic form of multiplication consists of

forming the product of two unsigned (positive)
binary numbers.
• For example, the multiplication of two positive 6-bit
binary integers, (25)10 and (39)10 is shown in Fig 4.
• Binary multiplication is equivalent to a logical AND
operation.
Fig 5: Multiplication of a 6x6 multiplier
• Therefore, generating partial products consists of
the logical ANDing of the appropriate bits of the
multiplier and multiplicand.
• Each column of partial products must then be
added and, if necessary, any carry values passed to
the next column.
• Fig 5. illustrates the generation, shifting, and
summing of partial products in a 6 × 6-bit multiplier

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MULTIPLIER TYPES Fig 1: Unsigned and Signed number representation

• The classification of Multipliers is given in Fig 2.

• In Unsigned Multipliers there is no sign bit allotted in
the number. All the bits represent the magnitude.
• In Signed Multipliers, MSB bit is the sign bit and
remaining bits represent the magnitude. Fig 2:
• Large multiplications can be more conveniently
illustrated using dot diagrams.
• The dot diagram for a simple 16 × 16 multiplier is in
Fig 3.
• Each dot represents a place holder for a single bit
that can be a 0 or 1.
• The partial products are represented by a horizontal
boxed row of dots, shifted according to their weight. Fig 3: Dot diagram for
16x16 multiplier

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Unsigned-Array Multiplier (or) BRAUN Multiplier Fig 4: 4-bit x 4 bit Unsigned

array multiplier

• The design of an unsigned array multiplier is based

on the simple pen and paper method of
multiplication.
• The multiplication is performed by taking one bit at
a time from the multiplier.
• The partial products are generated by multiplying
each bit to the multiplicand.
• These partial products are added column-wise to
obtain the final product.
• Fig 4. shows a 4 × 4 array multiplier for unsigned
numbers using an array of CSAs.
• Each cell contains a 2-input AND gate that forms a
partial product and a full adder (CSA) to add the
partial product into the running sum.
• The critical path delay is the longest path delay
from input to output.

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BOOTH’s MULTIPLIER
BOOTH’s RECODING ( or ENCODING):
The multiplier in booth is recoded before performing
• The booth’s multiplier reduces the number of multiplication as shown below:
stages in multiplication.
Eg: Let us take Multiplier as (15)10 = ( 01111 )2
• Performs two bits of multiplication at once –
requires half the stages. (i) First add an imaginary “zero” on the LSB side
(ii) So multiplier now becomes 011110
• Each stage is slightly more complex than simple (iii) Read two bits consecutively from right to left and
multiplier, but adder/subtracter is as fast as adder. encode as follows:
• Booth algorithm gives a procedure for multiplying (11) => 0 , (10) => +1 , (01) => -1 , (00) => 0
binary integers in signed 2’s complement (iv) The multiplier 011110 is encoded as “ +1000-1”
representation in efficient way, i.e., less number of (v) If we evaluate the value of “+1000-1”, we get 15.
additions/subtractions required.
• It operates on the fact that strings of 0’s in the
multiplier require no addition but just shifting. (vi) So the value of multiplier does not change after
• Booth’s multiplier can be used for multiplying both booth’s recoding.
unsigned and signed numbers. (vii) Therefore booth’s multiplier reduces the number
of stages in multiplication.
• The multiplier is first encoded as shown next.

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BOOTH’s MULTIPLIER HARDWARE IMPLEMENTATION Fig 6: Booth’s multiplier hardware

• The booth’s multiplication algorithm implementation

in hardware is shown in fig 6.
• The BR Register is used to store the multiplicand.
• The complementer takes the 2’s complement of the
multiplicand when required.
(LSB bit)
• The parallel adder adds the multiplicand to the AC
register and stores the result back in AC register.
• The QR register initially stores the multiplier.
• The contents of [AC and QR] together are shifted by
arithmetic right shift operation.
• Qn represents the LSB bit of the QR register.
• An extra flip flop Qn+1 is appended to QR to facilitate
inspecting two bits at a time.
• The sequence counter is used to count the number of
cycles of multiplication.

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BOOTH’s MULTIPLICATION ALGORITHM Fig 7: Booth’s multiplication algorithm

• The booth’s multiplication algorithm is shown in fig 7.

• The two bits [ QnQn+1 ] are tested.
• If QnQn+1 are same i.e. 00 or 11, then perform
arithmetic right shift by 1-bit.
• If QnQn+1 = 10, perform subtraction of AC – M
(multiplicand) and then perform Arithmetic Shift
Right (ASR). [ Note: Subtraction is performed by
taking 2’s complement addition of multiplicand. ]
• If QnQn+1 = 01 , perform addition AC + M
(multiplicand) and then perform Arithmetic Shift
Right (ASR).
• The booth’s algorithm calculates the product in ‘n’ steps
where ‘n’ is the number of bits used to represent
numbers.

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BOOTH’s MULTIPLICATION EXAMPLES CASE 1: Booth’s multiplication example for 5 x 4.

Both numbers are positive.

• The booth’s multiplication

examples are presented
here for three cases:
Case (i) : First Number = POSITIVE
Second Number = POSITIVE
Case (ii) : First Number = POSITIVE
Second Number = NEGATIVE
Case (iii) : First Number = NEGATIVE
Second Number = NEGATIVE

Booth’s Operation
encoding Bits
00 Only ASR
01 ADD and ASR

10 SUB and ASR

11 Only ASR

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BOOTH’s MULTIPLICATION EXAMPLES CASE 2: Booth’s multiplication example for -5 X 4

(One +VE and One –VE number).

Booth’s Operation
encoding Bits
00 Only ASR
01 ADD and ASR

10 SUB and ASR

11 Only ASR

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BOOTH’s MULTIPLICATION EXAMPLES CASE 3: Booth’s multiplication example for -5 X -4

(Both negative numbers).

Booth’s Operation
encoding Bits
00 Only ASR
01 ADD and ASR

10 SUB and ASR

11 Only ASR

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BARREL SHIFTER A 4x4 Barrel Shifter performing rotate right operation

• A barrel shifter is a digital circuit that can shift a data

word by a specified number of bits in one clock cycle.
• It has a control input which specifies the number of
bit positions to be shifted.
• Shifting operations are widely used for:
• Arithmetic Shifting
• Logical Shifting
• Rotation
• Shifting operations are also useful in floating point
operations, multiplication by constants, data
alignment, and address generation.
• Barrel Shifter is a wire dominated circuit and hence
area is dominated by wiring.
• A 4x4 barrel shifter using NMOS transistors as
switches is shown in figure.

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BARREL SHIFTER • Another approach to design barrel shifters is by using

multiplexers.
• The realization of 4x4 barrel shifter using 2x1 Muxes is
A 4x4 Barrel Shifter using 2x1 Muxes.
shown in figure
• This barrel shifter rotates the data by different amounts.

INPUT: A3 A2 A1 A0 ; OUTPUT: Y3 Y2 Y1 Y0

K1 P3 P2 P1 P0 K0 Y3 Y2 Y1 Y0 Op
0 A3 A2 A1 A0 0 A3 A2 A1 A0 NOP
0 A3 A2 A1 A0 1 A0 A3 A2 A1 ROR
#1
1 A1 A0 A3 A2 0 A1 A0 A3 A2 ROR
#2
1 A1 A0 A3 A2 1 A2 A1 A0 A3 ROR
#3

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ONE / ZERO DETECTOR

• A one’s detector is a circuit that detects

if the input data contains ALL ONES.
• The circuit outputs = ‘1’ when input has
all ones, otherwise the output is ‘0’.
• Similarly, the zero’s detector circuit
detects whether input bits are all zeros.
• The circuit outputs = ‘1’ when input has
all zeros, otherwise the output is ‘0’.

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PARITY GENERATOR
• Parity generators are of two types:
• (1) Even Parity (2) Odd Parity
• A parity bit can be added to an N-bit word to indicate whether the
number of 1s in the word is even or odd.
• In even parity, the extra bit is the XOR of the other N bits, which
ensures the (N + 1)-bit coded word has an even number of 1s.
• Similarly in odd parity, the extra bit is the XOR of N-bits such that
(N+1) bits have odd number of 1s.

3-Bit even Parity Generator

3-Bit Odd Parity Generator

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MAGNITUDE COMPARATOR

• A magnitude comparator determines whether one

number is greater than, less than or equal to the other
number.
• To compare two unsigned numbers A and B, compute
B – A = B + A’ + 1. If there is a carry-out, then A ≤ B;
otherwise, A > B.
Unsigned Magnitude comparator
• A zero detector indicates that the numbers are equal.
• Figure shows a 4-bit unsigned comparator built from a
carry-ripple adder and two’s complementor.

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MAGNITUDE COMPARATOR

• The relative magnitude is determined from

the carry-out (C) and zero (Z) signals according
to Table.
• Comparing signed two’s complement numbers
is slightly more complicated because of the
possibility of overflow when subtracting two
numbers with different signs.
• Instead of simply examining the carry-out, we must determine if the result is negative (N, indicated by
the most significant bit of the result) and if it overflows the range of possible signed numbers.
• The overflow signal V is true if the inputs had different signs (most significant bits) and the output sign is
different from the sign of B.
• The actual sign of the difference B – A is S = N ⊕ V because overflow flips the sign.
• If this corrected sign is negative (S = 1), we know A > B.
• The other relations can be derived from the corrected sign and the Z signal.

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UNIT 4: SEQUENTIAL CIRCUIT DESIGN

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CMOS D-LATCH and D-Flip FLOP design • A D-Flip Flop can be realized by connected two
D-Latches in Master-Slave configuration.
• The master changes state on positive edge of
• The D-Latch is a level triggered circuit. the clock, and slave changes state on negative
• The D-Latch can be realized by two back-to-back edge of the clock.
connected inverters.
• Since the outputs are produced on negative
• When the CLK = 1, the value on data input ‘D’ is clock, it is negative edge triggered D-Flip Flop.
written into the Latch.
• When CLK = ‘0’, the Latch stores the value written
into it.
• A CMOS D-Latch can be realized using two
transmission gates and two inverters.

D-Latch and its truth table

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LINEAR FEEDBACK SHIFT REGISTER (LFSR) A 3-bit LFSR

• The Linear feedback shift register (LFSR) is used to

generate pseudo-random test vectors in the chip.
• The outputs at each stage of an LFSR are used as the
input of the circuit.
• The LFSR is clocked for a large number of clock cylces
and monitored.
• The bit pattern of the sequence is random in nature but
has a periodicity. Pseudo random sequence generated by 3-bit LFSR
• That is why it is called PSEUDO RANDOM SEQUENCE.
• The LFSR is constructed using D-Flip Flops and a XOR
gate as shown in figure.

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