applied

sciences
Communication
A New Control Scheme for the Buck Converter
Hsiao-Hsing Chou 1 , Jian-Yu Chen 2 , Tsung-Hu Tseng 2 , Jun-Yi Yang 2 , Xuan Yang 2 and San-Fu Wang 3, *

1 Department of Computer Science and Information Engineering, National Taichung University of Science and
Technology, Taichung 404336, Taiwan
2 Department of Communication Engineering, National Penghu University of Science and Technology, Penghu,
Magong City 880011, Taiwan
3 Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung 411030, Taiwan
* Correspondence: [email protected]; Tel.: +886-4-2392-4505-7315

Abstract: In this paper, a new control scheme for buck converters was proposed. The buck converter
utilizes the dual control loop to improve transient response and has the constant switching frequency.
The control scheme is mainly as follows: (a) The switch-ON time is regulated by the constant
frequency mechanism. (b) The switch-OFF time is regulated by the output voltage. The spec/features
of the proposed converter are listed as: (1) The buck converter has an output of 1.0–2.5 V for the
input of 3.0–3.6 V. The load current ranges from 100 mA to 500 mA. (2) The actual current sensor is
not required. (3) The simulation results show that the recovery time is less than 1.6 µs during load
changes. (4) The variation in switching frequency is smaller than 1.05% over the output range of
1.0–2.5 V. (5) This circuit can be fabricated in future by UMC 0.18 µm 1P6M CMOS processes. This
paper depicts the control scheme, theoretical analysis, and implementation.

Keywords: switched-capacitor (SC) converters; switched-inductor (SL) converters; current mode

control (CMC); voltage mode control (VMC); adaptive ON time (AOT); constant ON time (COT);
pulse width modulation (PWM); peak current mode (PCM); average current mode (ACM)

1. Introduction
In recent years, portable devices have become more widespread and even diverse,
Citation: Chou, H.-H.; Chen, J.-Y.;
such as cell phones, laptops, and tablets. All these devices require a power converter, for
Tseng, T.-H.; Yang, J.-Y.; Yang, X.;
example, artificial intelligence (AI), Internet of Things (IoT) devices, etc. [1–3]. In order to
Wang, S.-F. A New Control Scheme
extend the standby time, especially in cell phones, the efficiency of the power converter is
for the Buck Converter. Appl. Sci.
crucial. The dynamic response of power converters is more and more important.
2023, 13, 1991. https://doi.org/
10.3390/app13031991
Power converters can be broadly classified as switched-capacitor (SC) converters [4,5]
and switched-inductor (SL) converters [6–8]. The SC converters mainly consist of switches,
Academic Editor: Giovanni Petrone control circuits, and capacitors. Different from the SC converter, the SL converter uses the
Received: 14 December 2022
inductor rather than the capacitor for power conversion. From the application viewpoint,
Revised: 30 January 2023 low power converters usually use SC architectures. On the contrary, SL converters are
Accepted: 31 January 2023 available in applications that range from a fraction of a watt to a few hundred watts [5].
Published: 3 February 2023 The advantage of the SC converter is that the capacitors have a higher power density and
are easier to integrate than the inductors [9]. However, voltage regulation problems can be
present in some voltage conversion ratios [5]. In contrast, the SL converters are popular in
power conversion because of their application range, high reliability, design flexibility, and
Copyright: © 2023 by the authors. low cost.
Licensee MDPI, Basel, Switzerland. The common terms used in buck converters include power-conversion topologies,
This article is an open access article pulse width modulation, discontinuous-conduction mode, and continuous-conduction
distributed under the terms and
mode. Firstly, we briefly introduce these common terms, and then present the recent
conditions of the Creative Commons
research situation. The basic buck conversion topology is very simple; it only uses the
Attribution (CC BY) license (https://
switches (S1 , S2 ) and an inductor (L) for power conversion (Figure 1). In power conversion,
creativecommons.org/licenses/by/
the key point is the control method, which controls the switches to turn ON or OFF. In
4.0/).

Appl. Sci. 2023, 13, 1991. https://doi.org/10.3390/app13031991 https://www.mdpi.com/journal/applsci

 Appl. Sci. 2023, 13, 1991 2 of 14

FOR PEER REVIEW 3 of 14

general, common control methods include: pulse width modulation (PWM) and peak
current mode (PCM).

S1 L Vo

IL
VIN Vo
CO R1
S2
VIN + RLOAD
-
VP VN RESR R2
Virtual inductor
DRIVER current sensor

VG

controller

Figure 1. Buck topology

Figure 1. with a virtual
Buck topology inductor
with currentcurrent
a virtual inductor sensor.
sensor.

For PWM, the feature is to fix switching frequency, and then change the pulse width
S1 L Vo usually has a variable switching
to control the switches (S1 , S2 in Figure 1). However, PCM
frequency, and the switches ON/OFF will depend on the inductor current. In addition,
VP whether for PWM or PCM, if the system is in steady state, when the switch (S1 ) starts to turn
VIN + ON (Figure 1), the inductor current is zero. WeCrefer O R1
to this as discontinuous-conduction
- VN
mode. On theScontrary, when the switch (S1 ) starts to turn ON, and the inductor current
is not zero, we refer to this as continuous-conduction R
2
LOAD
mode. In addition, the feedback
stability is also an important topic that will beRdiscussed in later sections.
R2
ESR
As an overview of the SL converters, the control modes can be classified into voltage
Constant
mode control (VMC) [10] frequency
and current mode control (CMC) [11–14]. In general, since CMC
has more feedback paths than control
VMC, CMC should perform better than VMC in regard to the
DRIVER
dynamic response and the voltage regulation. This is the reason why most current control
schemes are based on CMC. In the conventional CMC, the control scheme requires a current
sensor to get information about the inductor current. Therefore, how to sense inductor
TOFF control
VG current is an important issue and is discussed in much of the literature. The related research
has been summarized and analyzed in [15]. Several control modes based on CMC have
been revealed to regulate the output voltage, such as: constant on time (COT), average
current mode (ACM), constant off time (CFT), peak current VFBmode, and adaptive on time
TON control
(AOT) [16–19]. EA
The author of [15] uses a virtual inductor current sensor VREF
to obtain the inductor current
traces instead of the real current sensor (Figure 1). The proposed scheme in [15] can greatly
reduce
Figure 2. Dual loops hardware
control effort. for
topology However, it still needs the virtual inductor current sensor. The
buck converters.
authors of [20,21] propose a control scheme that does not require the current sensor but
only senses the output voltage. In [20], the switch-ON time is regulated by the voltage
S1 difference Vbetween the inputLand output voltages (Figure Vo 2). In [21], the switch-ON time
x
(TON ) of S1 is adaptive and regulated by the output voltage (Figure 3). Different from [20]
IL
VP and [21], in this paper, the switch-ON time is regulated by the constant switching frequency
mechanism. In contrast to [22], the constant switchingCO R1
frequency mechanism consists of
VIN + onlyVaN phase frequency detector, a charge pump, and a low pass filter.
-
S2 RLOAD

RESR R2
Constant
frequency
control circuits
 controller
controller

Appl. Sci. 2023, 13, 1991 3 of 14

Figure 1. Buck topology with a virtual inductor current sensor.
Figure 1. Buck topology with a virtual inductor current sensor.

S1 L Vo
S1 L Vo
VP
VP CO R1
VIN + CO R1
VIN +- VN
- VN S2
S2 RLOAD
RLOAD
RESR R2
RESR R2
Constant
Constant
frequency
frequency
control
control
DRIVER
DRIVER

TOFF control
VG TOFF control
VG

VFB
TON control VFB
TON control EA
EA VREF
VREF

Figure 2. Dual loops control topology for buck converters.

Figure 2. Dual Figure
loops2.control topology
Dual loops for buck
control topology converters.
for buck converters.

S1 Vx L Vo
S1 Vx L Vo
I
VP ILL
VP CO R1
VIN + CO R1
VIN +- VN
- VN S2
S2 RLOAD
RLOAD
RESR R2
RESR R2
Constant
Constant
frequency
frequency
control circuits
control circuits
Driver
Driver
VSET_PUL VEA1
VSET_PUL VEA1
Vgate
Vgate

TON control VFB

TON control VCMP VFB
VCMP EA
EA VREF
VREF

Figure 3. BUCK topology

Figure 3. BUCKwithout inductor
topology without current
inductor sensor.
current sensor.
Figure 3. BUCK topology without inductor current sensor.
In this paper, a new SL buck converter with constant switching frequency will be
proposed. The importance of the topic and the practical application that the new control
scheme can be listed as (a) the practical application of the scheme is suitable for portable
devices; (b) the contribution of this solution is that it effectively reduces hardware effort
and is suitable for mass production; (c) this scheme provides an alternative solution for
buck control in industry applications.
In addition, the merits of the new control scheme are (a) the constant switching
frequency, alleviating the EMI issue in applications; (b) the actual current sensor is not
required, which makes the overall circuit design simple. In this paper, we have made some
 Appl. Sci. 2023, 13, 1991 4 of 14

changes in the conventional design where we only detect the voltage difference between the
OR PEER REVIEW 4 of 14
output and the input to obtain the variation of the inductor current. In other words, these
differences from conventional designs make the overall circuitry simpler. The organization
of this paper is as follows: Section 2 presents the proposed scheme and implementation.
Section 3 introduces the mathematical modeling and components selection. Section 4 shows
2. Proposed Controlthe
Methodology
simulation results of SIMPLIS. Finally, the conclusion is given in Section 5.
2.1. Scheme and Implementation
2. Proposed Control Methodology
Figure 4 shows2.1.the proposed
Scheme scheme. In Figure 4, we can find that (a) the actual
and Implementation
current sensor is not needed
Figure 4 shows thescheme;
in this proposed(b) the constant
scheme. In Figure 4,frequency
we can findmechanism
that (a) the actual
controls the switch-ON time;
current (c)is the
sensor switch-OFF
not needed time is(b)regulated
in this scheme; byfrequency
the constant the error amplifier
mechanism controls
the switch-ON
(EA). The error amplifier wouldtime; make(c) V
the
FBswitch-OFF time is regulated
and VREF equal. by the error
In this paper, amplifier
the ON time(EA).
of The
error amplifier would make VFB and VREF equal. In this paper, the ON time of the S1 is
the S1 is labelled as TON, and the OFF time of the S1 is labelled as TOFF.
labelled as TON , and the OFF time of the S1 is labelled as TOFF .

S1 Vx L Vo

VP
CO R1
VIN + VN
-
S2 RLOAD

RESR R2
DRIVER

VFB
Adaptive TOFF EA
control VREF

Control Logic
Adaptive TON
control VIN

Constant Frequency Mechanism

Proposed controller

Figure 4. Proposed scheme.

Figure 4. Proposed scheme.

Figure 5 shows the Figure 5 shows the implementation

implementation of the proposed of the scheme.
proposed scheme. The advantages
The advantages of of
Figure 5 are listed as: (a) The proposed controller consists of only common components
Figure 5 are listed as: (a) The proposed controller consists of only common components
such as flip-flops, comparators, and error amplifier. No special process is required for
such as flip-flops, comparators, andarchitecture
fabrication; (b) The error amplifier. No special
of the adaptive TON /TOFF process
control is required
is simple, forgreatly
which
fabrication; (b) The reduces
architecture of theeffort;
the hardware adaptive TON/Tfrom
(c) Different OFF control
[22], the is simple,
constant whichmechanism
frequency greatly can
reduces the hardware effort; (c)
be effectively Different
used from
to keep the [22], the
switching constant
frequency frequency mechanism
constant.
can be effectively used to keep the switching frequency constant.
2.2. Operation Principle
The detailed operation of the converter is listed as follows:
1. When the switch S1 is ON, and the other switch S2 is OFF.
2. The inductor (L) is in the charging state, and the ON-time of S1 is controlled by
the adaptive TON control block. In the adaptive TON control block, the ON-time is
Appl. Sci. 2023, 13, 1991 5 of 14

decided by Vramp and VCTR . The Vramp is the function of VIN and Vo , which replaces
the conventional method that requires a current sensor to sense inductor current.
3. When the switch S1 is OFF, and the other switch S2 is ON.
4. The inductor (L) is in the discharging state, and the OFF-time of S1 is controlled
by the adaptive TOFF control block. In the adaptive TOFF control block, the OFF-
time is decided by Vramp2 and VCMP , both of which are the functions of the Vo .
Since the Vo controls the OFF-time through two paths, the control scheme has good
transient response.
5. The operation of the constant frequency mechanism will make the REF_CLK and the
FB_CLK equal. The REF_CLK can be set by the user. In this paper, the REF_CLK is set
to 1 MHz.
6. The states of the switches S1 and S2 are complementary and non-overlapping. The
key waveforms in Figure 5 are drawn in Figure 6.
7. In Figure 6, the IL is the inductor current. In the steady state, we can find that the
IL is triangle wave, and the mean is Iavg . When the S1 is ON (i.e., VG is high), the
IL is linearly rising and the inductor (L) is in the charging phase. On the contrary,
Appl. Sci. 2023, 13, x FOR PEER REVIEW 5 of 14
the S1 is OFF (i.e., VG is low), the IL is linearly falling, and the inductor is in the
discharging phase.

S1
Vx L Vo
IL
VP
R1 CO
VN
VIN +
S2
-
RLOAD
R2 RESR

VFB
VCMP VCMP
DRIVER EA
VIN VIN
VREF

VO

VSET
Vramp2

CMP
C

VGB
S Q
Vb1
VG VSET R Q Q D
REF_CLK
Q S
DN
Adaptive TOFF control
VGB VRST
Q R Q CLR
VCTR CLK_IN

Control Logic VIN VCTR

C1 UP
C2 Q D
FB_CLK

R1
Vb Q CLR
VRST Vramp Vb2

Constant Frequency Mechanism

CMP
C

VG
S Q

R Q
VO

Adaptive TON control

Proposed controller

Figure 5. Circuit implementation of the proposed converter.

Figure 5. Circuit implementation of the proposed converter.

2.2. Operation Principle

The detailed operation of the converter is listed as follows:
1. When the switch S1 is ON, and the other switch S2 is OFF.
2. The inductor (L) is in the charging state, and the ON-time of S1 is controlled by the
adaptive TON control block. In the adaptive TON control block, the ON-time is decided
by Vramp and VCTR. The Vramp is the function of VIN and Vo, which replaces the
conventional method that requires a current sensor to sense inductor current.
3. When the switch S1 is OFF, and the other switch S2 is ON.
4. The inductor (L) is in the discharging state, and the OFF-time of S1 is controlled by
the adaptive TOFF control block. In the adaptive TOFF control block, the OFF-time is
decided by Vramp2 and VCMP, both of which are the functions of the V o. Since the Vo
Appl. Sci. 2023, 13, x FOR PEER REVIEW 6 of 14
Appl. Sci. 2023, 13, 1991 6 of 14

IL
Iavg
t
VG

t
VSET TON TOFF

t
VCMP
Vramp2
t

VFB
VREF
t
VRST

t
VCTR
Vramp
t

Figure6.
Figure Keywaveforms
6. Key waveformsof
ofFigure
Figure5.
5.

3. Mathematical Modeling and Components Selection

3. Mathematical Modeling and Components Selection
3.1. Mathematical Modeling
3.1. Mathematical Modeling
In order to guarantee the stability of the system, the derivation of the open-loop
In order
transfer to guarantee
function is necessary. theThestability
literatureof the
about system, the derivation
the mathematical of theisopen-loop
modeling presented
transfer function is necessary. The literature about the mathematical
in [15]. Details of the design procedure can be found in [15]. Figure 7 shows the open-loop modeling is
presented in [15]. Details of the design procedure can be found in [15].
structure of Figure 4. Similarly to [20], Equation (1) can be used to represent the open-loop Figure 7 shows the
open-loop structure
transfer function of of Figure
Figure 7. 4.The
Similarly to [20], Equation
Gp (s) expression (1) can
in Equation (2)berepresents
used to represent
the buck
the open-loop
converter. Thetransfer functionnetwork
compensation of Figure 7. The
A(s) withGthep(s) error
expression in Equation
amplifier (2) represents
(EA) is represented by
the buck converter.
Equation (3). The compensation network A(s) with the error amplifier (EA) is
represented by Equation (3). Vo (s)
T(s) = = GP (s)· A(s) (1)
Vi (s)
𝑉𝑜 (𝑠)
T(s) = = 𝐺 (𝑠) ∙ 𝐴(𝑠) (1)
VFB (s) 1 𝑉𝑖 (𝑠) 1 𝑃 R LOAD ( R ESR Co s + 1)
GP ( s ) = = · 2 · (2)
Vi (s) Ri 1 + s + s 2 ( R LOAD + R ESR )Co s + 1
Q·ω
𝑉𝐹𝐵 (𝑠) 1 1  (𝑅𝐸𝑆𝑅
𝑅𝐿𝑂𝐴𝐷  𝐶𝑜 𝑠 + 1)
ω
𝐺𝑃 (𝑠) = = ∙ 2 ∙ s (2)
𝑉𝑖 (𝑠) 𝑅𝑖 𝑠 𝑠 (𝑅 1 ++w𝑅z 𝐸𝑆𝑅 )𝐶𝑜 𝑠 + 1
𝐿𝑂𝐴𝐷
1 +Vo (s) + 2
A(s) = 𝑄 ∙ 𝜔 = 𝜔 gm · R o ·   (3)
VFB (s) 1 + wsp
𝑠
𝑉𝑜 (𝑠) 1 (1 + )
1 𝑤𝑧
𝐴(𝑠) = wz = = 𝑔𝑚, ∙w𝑅p𝑜 = ∙ 𝑠 (3)
(4)
𝑉𝐹𝐵 (𝑠)R3 ·C1 (1R+o ·C1 )
𝑤𝑝
In Equation (2), ω = Tπon and Q = π2 , Ri is the gain of the TOFF ramp generator.
1 1
𝑤𝑧 = , 𝑤𝑝 = (4)
𝑅3 ∙ 𝐶1 𝑅𝑜 ∙ 𝐶1
In Equation (2), ω = 𝜋⁄𝑇 and 𝑄 = 2⁄𝜋 , 𝑅𝑖 is the gain of the TOFF ramp generator.
𝑜𝑛
R PEER REVIEW 7 of 14
Appl. Sci. 2023, 13, 1991 7 of 14

GP(s) A(s)
S1 Vx L Vo

VP
CO R1
VIN + VN
- VFB(s)
S2 RLOAD

RESR R2
DRIVER

Adaptive TOFF control Vo(s)

Vi(s) VFB
gm
VREF
CMP
Ri
C1
Control Logic RO
R3
Adaptive TON
control VIN
EA (Error AMplifier)
Constant Frequency Mechanism

Figure 7. Open loop structure of the proposed converter.

Figure 7. Open loop structure of the proposed converter.

3.2. Components Selection

3.2. Components Selection
Based on the above mathematical model, we can find out the relevant parameters with
Based on the the
above mathematical
mathematical model, [15,20].
tools “MathCAD” we can find
Table outthethe
1 lists relevant parameters
components/parameters of
the scheme. (Figure 7)
with the mathematical tools “MathCAD” [15,20]. Table 1 lists the components/parameters
of the scheme. (Figure
Table 7)
1. Component parameters.

Components Value Unit

Table 1. Component parameters.
Co 10 µF
L 4.7 µH
Components RESR
Value 5
Unit mΩ
Co RLOAD 3.6/18 (for10
load switching) μF Ω
R1 10 MΩ
L R2 4.710 μH MΩ
RESR Ro 51 mΩ MΩ
R3 400 kΩ
RLOAD C1 3.6/18 (for load 300switching) Ω pF
R1 10 MΩ
3.3. Implementation Processes
R2 10 MΩ
The future possible implementation processes can be explained as follows: (a) using
Ro UMC 0.18 µm 1P6M CMOS processes for1 fabrication; (b) the switches (S1 , S2 )MΩ are inte-
R3 grated in the chip; (c) UMC 0.18 µm 1P6M 400
CMOS processes provide 1.8 V and 3.3kΩ V MOS
devices for selection. For simplicity, the whole circuit uses the 3.3 V MOS devices for
C1 300 pF
implementation. In the future, a combination design with 3.3 V/1.8 V MOS devices can
be considered.
3.3. Implementation Processes
4. Simulation Results
The future possible implementation
4.1. SIMPLIS Schematic processes can be explained as follows: (a) using
UMC 0.18 μm 1P6M CMOS processes
The proposed for fabrication;
converter was verified by(b) the switches
SIMPLIS. (S1, Sits
Figure 8 shows 2) are integrated
schematic.
in the chip; (c) UMC 0.18 μm 1P6M CMOS processes provide 1.8 V and 3.3 V MOS devices
for selection. For simplicity, the whole circuit uses the 3.3 V MOS devices for
implementation. In the future, a combination design with 3.3 V/1.8 V MOS devices can be
considered.
 Appl. Sci.
Appl. Sci. 2023,
2023, 13,
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1991 8 8of
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Figure 8. SIMPLIS schematic for the proposed converter.

converter.

4.2.
Figure 8. SIMPLIS 4.2. Transient
schematic Response
for the
Transient proposed converter.
Response
The same
The same measurement
measurement conditions
conditions as as in
in [20,21]
[20,21] are
are given
given below.
below. (a)
(a) The
The load
load current
current
4.2. Transient Response
transition is between 0.1 A and 0.5 A at 3.3 V/1.8 V input/output voltage. (b) The recovery
transition is between 0.1 A and 0.5 A at 3.3 V/1.8 V input/output voltage. (b) The recovery
time is
is defined
The same measurement
time defined as within
withinas
conditions
as 1%
1%inof the
the 1.8
[20,21]
of 1.8areV
V output voltage
given below.
output at
voltage(a) load
at The transition.
loadload current
transition.
transition is between 0.1Figure
A and9 shows the
0.5 Athe load
at 3.3 transient
V/1.8 response.
V input/output From Figure
voltage. 9, the transient performance
(b)9,The
Figure 9 shows load transient response. From Figure the recovery
transient performance
iswithin
time is defined asis as follows: (a)the
1% of(a) The1.8recover
V outputtimes for theatstep-up/step-down
voltage load transition. load load current transition are
as follows: The recover times for the step-up/step-down current transition are
1.57 µs and 1.34 µs, respectively. (b) The overshoot/undershoot voltages are 21 mV/21 mV,
Figure 9 shows
1.57the load1.34
μs and transient response. (b)
μs, respectively. FromTheFigure 9, the transient performance
overshoot/undershoot voltages are 21 mV/21 mV,
both within the range of 21 mV.
both recover
is as follows: (a) The within the timesrange
forofthe
21 step-up/step-down
mV. load current transition are
Figure 10 shows that the converter can operate in Vin range of 3.0–3.6 V, while output
1.57 μs and 1.34 μs,
canrespectively.
be set in the (b) Theofovershoot/undershoot
range 1.0–2.5 V. In Vin range voltages
of 3.0–3.6are 21 mV/21
V, the maximum mV,ripple voltage
both within the range
for Voofis21
2.2mV.
mV, which occurred at Vin of 3.6 V and Vo of 2.5 V.

(a) Light load to heavy load

(a) Light load to heavy load

Figure 9. Cont.
 Appl. Sci. 2023, 13, x FOR PEER REVIEW 9 of 14

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2023, 13, 1991 9 of 14 9 of 14

(b) Heavy load to light load

Figure 9. Recovery times for load current transition (100–500 mA).

Figure 10 shows that the converter can operate in Vin range of 3.0–3.6 V, while output
(b) Heavy load to light load
can be set in the range of 1.0–2.5 V. In Vin range of 3.0–3.6 V, the maximum ripple voltage
Figure 9. Recoveryfor Vo is
times for2.2 mV,
load whichtransition
current occurred(100–500
at Vin ofmA).
3.6 V and Vo of 2.5 V.
Figure 9. Recovery times for load current transition (100–500 mA).

Figure 10 shows that the converter can operate in Vin range of 3.0–3.6 V, while output
can be set in the range of 1.0–2.5 V. In Vin range of 3.0–3.6 V, the maximum ripple voltage
for Vo is 2.2 mV, which occurred at Vin of 3.6 V and Vo of 2.5 V.

(a) Output performance for input margin operation

(a) Output performance for input margin operation

(b) Zone A of (a) (c) Zone B of (a)

Figure 10. Cont.

(b) Zone A of (a) (c) Zone B of (a)

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(d) Zone C of (a) (e) Zone D of (a)

(d) Zone C of (a) (e) Zone D of (a)
Figure 10. Performance of the converter for Vin range of 3.0–3.6 V.
Figure 10.
10. Performance of the
Performance of the converter
converter for
for V
Vin range of 3.0–3.6 V.
Figure in range of 3.0–3.6 V.
4.3. Load Regulation
4.3. Load Regulation
The load regulation is defined as Equation (5). Similarly to [20,21], the specification
The load regulation is defined as Equation
Equation (5). Similarly to [20,21], the specification
specification
of the load regulation
of theisload
measured at is an input/output voltage of 3.3voltage
V/1.8 of
V 3.3
andV/1.8
a load
load regulation
regulation is measured
measured atatan
aninput/output
input/output 3.3 V/1.8 V and a load
current varying from 0.5 varying
current A to 0.1from
A. From
0.5 A the simulation
to 0.1 A. From theresults shown
simulation
simulation in Figure
results shown11,in the
Figure 11, the
load regulation is load
0.01% throughisEquation
regulation (5). Equation
0.01% through
through Equation (5).
(5).
𝑉𝑜@0.1𝐴 𝑙𝑜𝑎𝑑 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝑉 @−. 𝑉𝑜@0.5𝐴 𝑙𝑜𝑎𝑑 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝑉 @ . load current
Load
Load RegulationLoad Regulation =
= Regulation = [email protected] load current − [email protected]∙ 100% ∙ 100%
·100% (5) (5)
𝑉
𝑉𝑜@0.5𝐴 𝑙𝑜𝑎𝑑 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
[email protected]
@ . load current
where
where 𝑉𝑜@0.5𝐴 𝑙𝑜𝑎𝑑where 𝑉@
is . the
[email protected] output isvoltage
the output
at a voltage at a load
load current of current
0.5 A, ofand
0.5 A, and
𝑐𝑢𝑟𝑟𝑒𝑛𝑡 load current is the output voltage at a load current of 0.5 A, and [email protected] load current
𝑉
𝑉𝑜@0.1𝐴 𝑙𝑜𝑎𝑑 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 isis@the output
. output
the is
voltage
voltage the output
at aatload voltage
a load at
current
current a load current
of 0.1ofA.0.1 A. of 0.1 A.

Figure 11. Load regulation.

4.4. Switching Frequency Regulation

Figure 11. Load regulation.
Figure 11. Load regulation.
By using the constant frequency mechanism, the converter can keep the switching
frequency
4.4. Switching Frequency
4.4. constant.
Regulation
Switching TheRegulation
Frequency switching frequency at different output voltages (1.0–2.5 V) is
shown in Figure
By using 12. The
the constant measurement
frequencythe results in Figure
mechanism, 12 show keep
that the switching
By using the constant frequency mechanism, converterthecanconverter
keep thecan the switching
switching
frequency
frequency can be maintained
constant.frequency at around
The switching 1 MHz
frequency for different
at differentoutput voltages
output and
voltages max load
frequency constant. The switching at different output voltages (1.0–2.5 V) is(1.0–2.5 V)
current (500 mA).
is shown in Figure 12. The measurement results in Figure 12 show that the switching
shown in Figure 12. The measurement results in Figure 12 show that the switching
frequency can be maintained at around 1 MHz for different output voltages and max load
current (500 mA).
 Appl. Sci. 2023, 13, 1991 11 of 14

Appl. Sci. 2023, 13, x FOR PEER REVIEW 11 of 14

frequency can be maintained at around 1 MHz for different output voltages and max load
current (500 mA).

Figure 12. The measurements of the switching frequency.

Figure 12. The measurements of the switching frequency.

4.5.4.5. PerformanceSummary
Performance Summary
TheThe performanceof
performance ofthe
the proposed
proposed converter
converterisislisted in in
listed Table 2. As
Table 2. Table 2 shows,
As Table for for
2 shows,
thethe currenttransition
current transition between
between thethe100
100mAmAand 500500
and mA,mA, the recovery time istime
the recovery less than 1.6than
is less µs. 1.6
At the same time, the converter has good performance at an input voltage of 3.0 V–3.6 V
μs. At the same time, the converter has good performance at an input voltage of 3.0 V–3.6
and an output voltage of 1.8 V. Finally, the performance comparison with the presented
V and an output
converters voltage
is listed of 1.8
in Table 3. V. Finally, the performance comparison with the presented
converters is listed in Table 3.
The2.comparisons
Table Performance of in Table Converter.
Proposed 3 are briefly discussed as follows:
Parameter (a) For
Symbol the parameter in recovery time,
Conditions we can find
Min Typ that the proposed
Max scheme
Unit is better
Output capacitor Co than the simulation ESR: 5 mΩresults of [15,21–25]. The measurement
10 results of [11,26–28]
µF are
Inductor L worse than the proposed
DCR *: 30 mΩ scheme, and the numerical
4.7 differences are large.
µH For this
Output voltage Vo purpose, one is the measurement result,
1.0 and the other is the
2.5 simulation Vresult. This
Input supply voltage Vin is the major difference. 3.0 3.6 V
Load current (b)
Iload For the parameter in undershoot/overshoot:
100 this parameter is
500 greatly affected
mA by the
Output ripple Vpp
load conditions and the output
Vin = 3.6 V, Vo = 2.5 V
capacitor. For example, if the output
2.2
capacitor
mV
is large,
then the Loadundershoot/overshoot
current: 500 mA
is small. Or, if the load current step of the load
Switching frequency fsw 1 MHz
conditions
@ Vin =is3.3small, then Vthe undershoot/overshoot
V, Vo = 1.0–2.5 is small. Therefore, under the
Recovery time (step-up) Tstep_up
sameLoadtestcurrent:
conditions, themAperformance of the
100 mA to 500
1.57
proposed scheme is µsbetter than
@ Vin = 3.3 V, Vo = 1.8 V
[15,21,22].
Recovery time Load current: 500 mA to 100 mA
T(c)
step_dn For the parameter in switching frequency, we 1.34 can find that in most of the µs literature,
(step-down) @ Vin = 3.3 V, Vo = 1.8 V
the switching frequency is designed around 1 MHz.
Load current: 500 mA to 100 mA
Overshoot Vovshoot 21 mV
(d) For the parameter
@ Vin = 3.3 V, Vin
o =switching
1.8 V frequency variation, we can find that the discussion
Undershoot Vunshoot
on switching
Load current: frequency
100 mA to 500variation
mA is a minority21in all the comparison literature,
mV
and
@ Vin = 3.3 V, Vo = 1.8 V
only appears in [11,21,22]. The switching frequency variation of the proposed scheme
* DCR: DC resistance of inductor.
is less than 1.2%.
The comparisons in Table 3 are briefly discussed as follows:
Table 2. Performance of Proposed Converter.
(a) For the parameter in recovery time, we can find that the proposed scheme is better
Parameter Symbol Conditions
than the simulation results of [15,21–25]. The measurement Min
resultsTyp Max areUnit
of [11,26–28]
Output capacitor Coworse than the proposed scheme,
ESR: 5 mΩ and the numerical differences are
10large. For this μF
Inductor L DCR *: 30 mΩ 4.7 μH
Output voltage Vo 1.0 2.5 V
Input supply voltage Vin 3.0 3.6 V
Load current Iload 100 500 mA
Appl. Sci. 2023, 13, 1991 12 of 14

purpose, one is the measurement result, and the other is the simulation result. This is
the major difference.
(b) For the parameter in undershoot/overshoot: this parameter is greatly affected by
the load conditions and the output capacitor. For example, if the output capacitor is
large, then the undershoot/overshoot is small. Or, if the load current step of the load
conditions is small, then the undershoot/overshoot is small. Therefore, under the
same test conditions, the performance of the proposed scheme is better than [15,21,22].
(c) For the parameter in switching frequency, we can find that in most of the literature,
the switching frequency is designed around 1 MHz.
(d) For the parameter in switching frequency variation, we can find that the discussion
on switching frequency variation is a minority in all the comparison literature, and
only appears in [11,21,22]. The switching frequency variation of the proposed scheme
is less than 1.2%.

Table 3. Performance Comparisons with Reported Converters.

References 2018 [23] 2020 [24] 2021 [15] 2021 [22] 2022 [21] This Work
Results simulation simulation simulation simulation simulation simulation
Control scheme AOT AOT AOT AOT AOT AOT
Process (µm) 0.35 0.18 0.35 * 0.18 * 0.35 * 0.18 *
Input voltage (V) 12 3.3–5.0 3.0–3.6 3.0–3.6 3.0–3.6 3.0–3.6
Output voltage (V) 1.2 1.8 1.0–2.5 1.0–2.5 1.0–2.5 1.0–2.5
Inductor (µH) 1 1.5 4.7 4.7 4.7 4.7
Output Capacitor (µF) 47 20 10 10 10 10
Switching Frequency (MHz) 1 1 1 1 1 1
Switching frequency variation (%) N/A N/A N/A 1 3.5 1.2
Max. Load current (mA) 5000 2000 500 500 500 500
Load current step (mA) 4000 800 400 400 400 400
Undershoot/Overshoot (mV) 20/26 13/14 23/26 20/24 21/30 21/21
Recovery time (µs) (rise/fall) <3 6/2 1.98/1.6 1.69/1.62 1.8/1.5 1.57/1.34
References 2019 [25] 2021 [11] 2021 [26] 2021 [27] 2022 [28]
Results measurement measurement measurement measurement measurement
Current-Mode
Control scheme Hysteretic PLL COT COT AOT
Hysteretic
Process (µm) 0.065 0.35 0.13 0.18 0.18
Input voltage (V) 3.3 3.3–3.6 7–15 4.25–15 1.6–2.2
Output voltage (V) 0.6–2.0 0.9–2.5 5–7 1.1 0.4–1.2
Inductor (µH) 2.2 4.7 2.2 0.47 0.33
Output Capacitor (µF) 10 10 10 47*3 10
Switching Frequency (MHz) 1 1 2 0.5–1.25 3
Switching frequency variation (%) N/A 1 N/A 42 N/A
Max. Load current (mA) 1500 600 2000 5000 500
Load current step (mA) 900 400 2000 5000 450
Undershoot/Overshoot (mV) 106/87 30/60 85/72 30/15.7 20/20
Recovery time (µs) (rise/fall) 3.4/3.6 2.6/2.2 3/2.7 80/45 3.4/3.6
* This work is system level simulation with SIMPLIS.

5. Conclusions
In this paper, a new control scheme of the buck converter was proposed. This con-
verter uses an alternative method to control the TON , and TOFF . The converter has three
features/advantages. First, the TOFF is controlled to keep the switching frequency constant.
The constant switching frequency feature can alleviate the EMI issue in applications. In
addition, it is not difficult to implement, requiring only the PFD, charge pump, and low
pass filter. Second, the control method is based on CMC technique, but does not require
the actual current sensor, which greatly reduces the complexity of the circuit. Third, the
circuit is easy to realize and does not have special layout considerations; thus, it is suitable
for mass production. Finally, the converter was verified by SIMPLIS. From the simulation
results, the control topology has good transient performance. In future, the scheme can be
implemented with UMC 0.18 µm 1P6M CMOS processes.
Appl. Sci. 2023, 13, 1991 13 of 14

Author Contributions: Conceptualization, H.-H.C.; Data curation, J.-Y.C. and T.-H.T. and J.-Y.Y. and
X.Y.; Methodology, H.-H.C. and J.-Y.Y.; Validation, H.-H.C. and S.-F.W.; Formal analysis, J.-Y.Y. and
J.-Y.C.; Writing—original draft, J.-Y.Y. and J.-Y.C.; Writing—review & editing, H.-H.C. and S.-F.W. All
authors have read and agreed to the published version of the manuscript.
Funding: This research received no external funding.
Institutional Review Board Statement: Not Applicable.
Informed Consent Statement: Not Applicable.
Data Availability Statement: Not Applicable.
Conflicts of Interest: The authors declare no conflict of interest.

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