CHAPTER 5

The CMOS Inverter

Hydrogen, photons, and electronic inverters are indivisible units of the ele-
ments, light, and computers.

Anonymous

Logic gate electronics begins with the inverter whose simple two-transistor appearance
hides its complexity. The inverter has about a dozen important properties that are shared
by multi-input gates such as NAND and NOR gates. We will become proficient in under-
standing these electronic properties.
CMOS refers to a particular method or technology for designing and building integrated
circuits. The word complementary means that nMOS and pMOS transistor pairs are linked
to make logic gates. Originally, CMOS integrated circuits (ICs) used metal for the transistor
gate material. Then polysilicon replaced metal for many years, but new technology has
returned to metal gates. CMOS is one of several technologies with which we can build
digital circuits. It was first manufactured by the RCA Corp. in 1964. Its popularity grew
slowly, but it has been the dominant digital technology since the early 1980s.

5.1. The CMOS Inverter

The inverter is the most abundant logic gate in digital ICs. An inverter converts a logic
high input voltage, such as VDD = 1.5 V to a low logic voltage of 0 V, and converts a logic
low input voltage to a logic high voltage (i.e., 0 V to 1.5 V). VDD is the standard symbol for
CMOS power supply voltage. The inverter electronic symbol, truth table, and schematic
are shown in Figure 5-1. The logic statement is VO = V in . When Vin is a high voltage,
the nMOS transistor turns on and the pMOS transistor turns off driving the output node
to ground. A low input voltage turns the pMOS transistor on and the nMOS off driving
the output node to a high logic voltage of VDD . This on–off tandem operation guarantees
there is no current from VDD to ground (GND) when the logic values are settled. This is a
significant low power feature of CMOS.
125
126 The CMOS Inverter

VDD

Vin VO
Vin VO
Vin VO 0 1
1 0 CL

(a) (b) (c)

FIGURE 5-1.
Inverter. (a) Symbol. (b) Truth table. (c) Schematic.

Boolean values are detected in the inverter quiescent state when all signal nodes settle
to their steady state. Only one transistor is on in the steady state connecting the output
terminal VO to one of the power rails. There is no current in the circuit since the other
transistor is off, eliminating a direct current (DC) path between the rails. The capacitive
load C L shown in Figure 5-1 is unavoidable in any circuit. The capacitance is a lumped
value including transistor internal nodes, load wiring, and downstream logic gates. C L
does not affect static properties, but hinders the speed of logic transitions. We will analyze
the dynamic operation later.
VDD varies with the application and advances in circuit design. VDD may be lower than
1 V for certain leading-edge circuits or range from 1.2 V to 3.3 V for older still viable
technologies. Battery operated digital circuits use VDD values that are typically on the
order of 1.5 V. This chapter uses a range of circuit power supply voltages in its examples
to adjust our thinking to the diversity expected in real environments.
The logic gate output voltage responds to a small range of input voltages but functionally
maps into just one of the two logic states. For example, a 2.5 V power supply technology
has nominal logic levels of 2.5 V (high) and 0 V (low). When the input high ranges from
2 V to 2.5 V, the inverter output retains a stable logic low of about 0 V. An input logic-0
ranging from about 0 V to 0.5 V will deliver a stable 2.5 V output. Mapping an input
voltage range to a stable output logic state implies noise immunity in the digital circuits.
Logic circuit immunity to electronic noise is a design specification.
A third range of digital voltage levels is not mapped to any logic state and that is the volt-
age transition range that occurs during a logic change of state. Nodes voltages in the tran-
sition have no logic meaning. They are the voltages between a logic-1 and logic-0. But the
transition region is extremely important since it determines the time to change logic states.
The transistor cross section for an inverter is shown in Figure 5-2. The n-channel
transistors have a p-bulk to attract minority carriers. The p-doped bulk is called a p-well.
Notice the nMOS source is tied to the grounded p-well and the pMOS source is tied to
5.2 Voltage Transfer Curve 127

Input

Output
VDD
Gate Gate

n+ n+ P+ P+

p-well
n-substrate

FIGURE 5-2.

CMOS inverter cross section.

the substrate at VDD . The diagram sketches a p-well, but n-wells are also used with the
p-channel transistors lying in an n-well. The p-channel transistors have an n-substrate to
attract minority carriers.

5.2. Voltage Transfer Curve

The voltage transfer curve (VTC) measures the output voltage over the range of input
voltages. The VTC in Figure 5-3a shows that VO = VDD = 1.2 V when Vin = 0 V, and
that VO = 0 V when Vin = VDD = 1.2 V. The general inverted S-shape of the VTC does
not change much as VDD changes. The VDD on IC products may range from 0.8 V to 5 V.
Modern VDD values lie at the lower end. VDD = 1.2 V was chosen as a typical value in
this VTC example.

1.4 1.4
1.2 1.2
1.0 1.0
VO (V)

VO (V)

0.8 0.8
VM
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vi (V) Vi (V)
(a) (b)

FIGURE 5-3.

(a) Voltage transfer curve (VTC) of CMOS inverter. (b) VTC showing threshold logic point VM .
128 The CMOS Inverter

1.8

1.6

1.4

1.2

1
VO (V)

0.8
Region I Region II Region IV Region V
0.6

Region III
0.4

0.2

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Vin (V)

FIGURE 5-4.

VO versus Vin voltage transfer curve (VTC) with five bias states. The input voltage Vin is swept
from 0 – VDD while VO is measured.

Inverter designs often seek a symmetric static voltage transfer characteristic

(Figure 5-3a), so VO = Vin at about VDD /2. To be more exact, a plot of Vin = VO
forms a 45◦ straight line from the origin in Figure 5-3b. The voltage at which Vin = VO
is the logic threshold voltage VM . The intersection of the measured VTC and the 45◦ line
locates VM , which is VM ≈ 0.62 V for this inverter.
The intermediate points in the VTC convey much about the dynamics of the inverter
(Figure 5-3). Transistors experience the off, saturated, and nonsaturated bias states during
the sweep. At Vin = 0 V, the nMOS transistor is off and the pMOS transistor is driven fully
into the ohmic state with VG Sp = −1.2 V. As Vin increases, the nMOS transistor remains
off until Vtn is reached. At that point, the two transistors compete with each other for control
of the output voltage. As Vin increases further, the pMOS drive weakens and the nMOS
drive strengthens. The nMOS transistor now pulls the output voltage lower and eventually
to 0 V as Vin goes to 1.2 V. At this point the pMOS transistor is off since VG Sp = 0 V.
Figure 5-4 shows an inverter static voltage transfer curve partitioned into five regions
corresponding to five distinct transistor bias states. VDD = 1.8 V in this example.
These five bias regions in Figure 5-4 are as follows.

Region I. nMOS off, pMOS ohmic: This voltage range exists for Vin < Vtn . The
nMOS transistor is off, and the pMOS transistor is driven into nonsaturation since
VG Sp ≈ –VDD < VDSp + Vtp . The pMOS drain node at VO is pulled up to a logic
high VDD through the low impedance of the pMOS channel.
5.3 Noise Margins 129

Region II. nMOS saturated, pMOS ohmic: When Vin goes just above the nMOS
threshold voltage (Vin > Vtn ), the nMOS transistor barely turns on and is in satura-
tion (Vin < VO + Vtn ). Current now passes through both transistors and VO drops as
Vin increases. The pMOS transistor remains in the ohmic state, but with decreasing
gate drive.
Region III. nMOS saturated, pMOS saturated: When VO < Vin − Vtp and VO > Vin −
Vtn , the nMOS and pMOS transistors are both in saturation and the region has a straight
line. Since VO and Vin are linearly related, analog amplification occurs here. Small
changes in the input waveform are amplified by a value equal to the slope of the
straight line. MOS analog circuit designs use this property. It is also good for digital
circuits that demand rapid VO change during logic transitions of Vin . A digital goal is
to get through the transition region as quickly as possible, and what better way than
to have the circuit behave as an amplifier?
Region IV. nMOS ohmic, pMOS saturated: As Vin increases, it approaches a value
such that the difference between Vin and VDD is close to the pMOS transistor threshold
voltage. This is similar to Region II, but the transistor roles are reversed. The pMOS
transistor is in saturation and the nMOS enters nonsaturation.
Region V. nMOS ohmic, pMOS off: When Vin goes to a logic high voltage, then
Vin VO + Vtn . The nMOS transistor is in its ohmic state pulling the drain voltage
to ground, and the pMOS transistor is off.

Voltages slightly less than the logic high or slightly more than logic low voltages are
called weak logic voltages. Weak logic states are read correctly, but noise margins and gate
driving voltage strengths are compromised. The inverter switching threshold voltage (VM )
at which Vin = VO is a unique condition since the theoretical logic state changes at a point
as VO moves through VM . Inverter voltages in the linear region are not logically defined.

5.3. Noise Margins

The rectangles in Figure 5-5 represent the voltage levels and ranges for the logic high and
low as logic gate-A output drives the inputs of logic gate-B. The shaded areas represent a
range of logic high and low voltages that logic gates must recognize as valid.
Gate-A Gate-B
VOH
Gate-A Gate-B
NMH VIH

NML
VOL VIL

(a) (b)

FIGURE 5-5.

(a) Series inverters. (b) Voltage ranges mapped to logic Boolean values.
130 The CMOS Inverter

The following terms are defined:

VOL Output low voltage: maximum voltage at a gate output for a logic low to be read
correctly by a load gate.
VOH Output high voltage: minimum voltage at a gate output for a logic high to be read
correctly by a load gate.
VIL Input low voltage: maximum input voltage recognized as a logic low.
VIH Input high voltage: minimum input voltage recognized as a logic high.
These logic voltages define the noise margin or immunity needed when connecting
logic gates. The high and low noise margins (NM H , NM L ) are obtained from these four
voltage parameters and are typically specified by the manufacturer. NM H and NM L for
the high and low logic values are
NM H = VOH − VIH
(5-1)
NM L = VIL − VOL
Noise margins must be positive for proper logic operation, and the larger these values,
the better the circuit noise immunity. If an input voltage rises and makes NM H negative,
then there is risk of a noise-induced change of logic state. These parameters are an essen-
tial measurement during production testing of ICs. Board designers must know that ICs
connected to each other are within specification and interface properly.
Noise margins reflect design and manufacturing capability. It is what a manufacturer
can guarantee to a customer. Another NM definition picks the two points in the VTC
where the slope is –1. This is arbitrary but does observe that when the absolute slope is
>1, then amplification of Vin takes place, and that is not good from a noise standpoint.
It is a high-risk region when a logic signal is moved to a point where the slope is greater
than one. It is helpful to sketch the NM rectangles in Figure 5-5 and label values before
solving the problems that follow.

EXAMPLE 5-1
An IC with VDD = 1.5 V shows VOH = 1.35 V, VOL = 0.2 V, VIH = 1.2 V, and VIL = 0.3 V.
Calculate the NM L and NM H for this IC.
VOUT VIN

1.35 V
NMH 1.2 V

NML
0.3 V
0.2 V

Sketch the NM rectangles

NM H = 1.35 − 1.2 = 150 mV
NM L = 0.3 − 0.2 = 100 mV
5.4 Symmetrical Voltage Transfer Curve (VTC) 131

Self-Exercise 5-1
IC A and IC B have VDD = 2 V. IC A is sending data to IC B and their input–output (I/O)
specifications are

IC A : VIH = 1.6 V, VIL = 0.4 V, VOH = 1.5 V, and VOL = 0.3 V.

IC B : VIH = 1.6 V, VIL = 0.5 V, VOH = 1.5 V, and VOL = 0.3 V.

(a) Show calculations as to whether there is a problem.

(b) If there is a problem what should be done?

Gate-A Gate-B
VOH
NMH VIH

NML
VOL VIL

Answer: (a) The problem lies in the high voltage levels. (b) Answer intentionally not given.

Self-Exercise 5-2

(a) If VDD = 1.8 V, VOH = 1.75 V, and NM H = 130 mV, calculate VIH .
(b) If VIL = 0.35 V and NM L = 180 mV, calculate VOL .

Answers: (a) VIH = 1.62 V. (b) VOL = 170 mV

5.4. Symmetrical Voltage Transfer Curve (VTC)

The aspect ratio W p /Wn for a symmetric transfer characteristic is found by equating the
saturation current for nMOS and pMOS transistors and setting the input voltage equal
to VM = VDD /2. Eq. (5-2) gives the W p /Wn ratio for achieving a symmetrical inverter
where VM = VDD /2.

2Vtn 2
1−
Wp µn 
 VDD  
= (5-2)
Wn µp  2|Vtp | 
1−
VDD
VM = 0.5 VDD in Eq. (5-2) when the pull-up and pull-down transistor current drive strengths
are equal, but designers may need faster pull-up or pull-down in a given design situa-
tion. If VM < 0.5 VDD then the nMOS pull-down transistor is stronger than the pull-up,
132 The CMOS Inverter

and the VTC is skewed to the left. If VM > 0.5 VDD then the pMOS pull-up is stronger,
and the VTC is skewed to the right. In reality, it is difficult to make the VTC exactly
symmetrical. Mobility’s are uncertain, and W p is typically not made a small fractional
dimension relative to Wn . In our examples, we will pretend that exact symmetry can be
attained.

EXAMPLE 5-2
Compute the ratio of nMOS and pMOS transistor width to obtain a symmetric inverter for
a 0.18 µm technology in which µn = 360 cm2 /V · s, µ p = 109 cm2 /V · s,Vtn = 0.35 V,
Vtp = −0.4 V, and VDD = 1.8 V.
 
2(0.35) 2
Wp 360 cm2 /V  1−
=  1.8   = 4.0
Wn 2
109 cm /V 2|−0.4|
1−
1.8

Self-Exercise 5-3
Derive Eq. (5-2).

Self-Exercise 5-4
If µn = 360 cm2 /V · s, µ p = 109 cm2 /V · s, Vtn = 0.35 V, Vtp = −0.4 V, and VDD = 1.5 V,
what W p /Wn ratio provides the inverter with a symmetrical VTC?
Wp
Answer: = 4.31
Wn

5.5. Current Transfer Curve

The DC power supply current transfer curve (ITC) is equally important. Figure 5-6 shows
the IDD versus Vin characteristic. At Vin < Vtn in bias Region I, the nMOS transistor is
off and no current passes through the circuit. When Vin = VDD in Region V, the pMOS
transistor is off, and again no current passes from the power supply to ground. Typical
inverter current at these long channel quiescent logic levels is in the low pA’s and is
mostly drain-substrate reverse bias saturation current. Virtually no power is dissipated in
the quiescent logic states when the Off-current is this low.
The peak current near VDD /2 depends upon transistor strength (the size of the width to
length ratio, threshold voltage, and carrier mobility). Both transistors are in the saturated
state at the current peak. When an inverter changes logic state, this transient current is
wasted power. Peak total power supply currents in large microprocessor designs are many
amperes since this is the sum of the transient currents of millions of switching logic gates.
5.5 Current Transfer Curve 133

3.0e 4

2.5e 4

IDD (A) 2.0e 4

1.5e 4

1.0e 4

5.0e 5

0.0e 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Vin (V)

FIGURE 5-6.

Inverter power supply current transfer curve.

Peak current is easy to calculate. The nMOS and pMOS transistors are both in saturation
at VDD /2 for a symmetrically designed inverter. Either saturation equation for the nMOS
and pMOS transistors will solve for the peak current. Examples for symmetrical inverters
will illustrate.

EXAMPLE 5-3
If VDD = 2 V, Vtn = 0.5 V, Vtp = −0.5 V, K n = 75 µA/V2 , K p = 50 µA/V2 , (W/L)n = 2,
and (W/L) p = 3, calculate I peak .

IDD
Vin

The nMOS saturated state equation gives

µA 2
I peak = I Dn = 75 [1 − 0.5]2 = 37.5 µA
V2 1
The pMOS saturated state equation also gives
µA 3
I peak = I Dp = 50 [1 − 2 + 0.5]2 = 37.5 µA
V2 1
134 The CMOS Inverter

Self-Exercise 5-5
If VDD = 1.5 V, Vtn = 0.4 V, Vtp = −0.4 V, K n = 100 µA/V2 , and K p = 50 µA/V2 :
(a) The peak current of 35 µA occurs at 0.6 V. What is (W/L)n ?
(b) What is the (W/L) p ?

W W
Answers: (a) = 8.75, (b) = 2.8
L n L p

Self-Exercise 5-6
Given an inverter with Vtn = 0.6 V, Vtp = −0.7 V, µn = 1350 V2 /(V · s), µ p = 350 V2 /
(V · s), and W p /Wn = 9, calculate VDD for a symmetrical CMOS inverter.
Answer: VDD = 1.78 V

5.6. Graphical Analysis of VTC

5.6.1. Static Transfer Curves
Figure 5-7 relates the bias state regions with the voltage transfer function and two 45◦
lines. Eq. (5-3) is the bias boundary condition for the nMOS transistor and is a straight line
(a) when plotted on Figure 5-7. The lower unity-slope line-a defines the nMOS saturation
and nonsaturation regions. All points on the transfer curve lying above line-a represent
the nMOS transistor in either saturation or the off-state. All points below line-a represent

1.8
1.6
1.4
1.2
(b)
1
VO (V)

0.8
(a)
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Vin (V)

FIGURE 5-7.
Inverter VTC and transistor state.
5.6 Graphical Analysis of VTC 135

the nMOS transistor in the ohmic state. Vtn is located on the x-intercept.
VGS = VDS + Vtn (5-3)

or
Vin = VO + Vtn (5-4)

and
Vtn = Vin at VO = 0
A similar derivation leads to the pMOS transistor bias boundary line labeled (b) in Figure
5-7 and given in Eq. (5-4). The y-axis intercept is VO = –Vtp . The pMOS transistor is
either saturated or off for all points on the curve below line-b and is in the ohmic state above
line-b. Both transistors are in saturation in the important region between the two lines.
Vin = VO + Vtp
Vtp = −Vin at VO = 0 (5-5)

EXAMPLE 5-4
Given a simulated inverter transfer curve. Estimate Vtn and Vtp using bias line concepts.
1.6

1.4

1.2

1.0
VO (V)

0.8

0.6

0.4

0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Vi (V)

CMOS inverter voltage transfer curve.

Put a small mark on the estimated ends of the linear region and draw 45◦ lines. The threshold
values are the intercepts approximately. Vtn ≈ 0.52 V and Vtp ≈ −0.43 V.

Graphical analysis allows visualization of transistor states during logic transitions. The
maximum gain region occurs when both transistors are saturated as seen between the two
bias lines (a, b) in Figure 5-7. An example emphasizes this thinking.
136 The CMOS Inverter

EXAMPLE 5-5
When VO switches in an inverter from VDD to 0 V, estimate the fraction of VDD that the
nMOS transistor is in saturation. Let Vtn = 0.2 VDD , Vtp = −0.2 VDD , and K n = K p , where
K n = K n (W/L)n , and K p = K p (W/L) p .
We know I Dn = |I Dp | for all the points in the static curve including the point on line-a
where the nMOS transistor leaves saturation. At this point both transistors can be treated in
the saturation state. This is the transition between Regions III and IV, and we will calculate
VO at that point.

K n (VGS − Vtn )2 = K p (VGS − Vtp )2

Substitute for VGS = Vin , K n = K p , Vin = 0.2 × VDD , Vin = VO + Vtn and get

K n (Vin − Vtn )2 = K p (Vi n − VDD − Vtp )2

VO2 = VO2 − 1.2 VDD (VO ) + 0.36 VDD
2

VO = 0.3 VDD
The fraction is
VDD − VO
= 0.7 = 70%
VDD
The nMOS is in saturation for about 70% of the transition. This saturation bias is significant
when we model the inverter logic transition speed.

EXAMPLE 5-6
If K p = 55µ A, Vin = 1.0 V, and IDD = 15 µA, and the inverter is symmetrical, what is
(W/L) p ?
1.8
1.6
1.8 V
1.4
1.2
1
VO (V)

Vin Vout
0.8
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Vin (V)
5.6 Graphical Analysis of VTC 137

Use the VTC to estimate Vtp ≈ 0.6 V

15 µA = 55 µA(W/L) p (1.0 − 1.8 + 0.6)2

(W/L) p = 6.8

Self-Exercise 5-7
A CMOS inverter has transistor parameters: K n (W/L)n = 265 µA/V2 , K p (W/L) p =
200 µA/V2 , Vtn = 0.55 V, Vtp = −0.63 V, and VDD = 2.5 V. What fraction percentage of
the total output voltage swing will the nMOS transistor be in saturation?
Answer: 75.4%

Self-Exercise 5-8
The ITC and VTC are shown for an inverter. If (W/L)n = 50, estimate Vt and solve for
µε
Kn = from the data.
2Tox
800 1.4

700 A 1.2
600 1.0
IDD (nA)

0.8
VO (V)

400
0.6

200 0.4
0.2
0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vi (V) Vi (V)

Answer: K n ≈ 350 µA/V2

Self-Exercise 5-9
A CMOS inverter has transistor parameters K n (W/L)n = 265 µA/V2 , K p (W/L) p =
200 µA/V2 , Vtn = 0.55 V, Vtp = −0.63 V, and VDD = 2.5 V. What fraction of the total
output voltage swing will the pMOS transistor be in saturation?

Answer: 71.8%
138 The CMOS Inverter

Self-Exercise 5-10
Estimate the analog voltage gain for the inverter whose transfer curve is in Figure 5-7.
Answer: Av ≈ −13

5.6.2. Dynamic Transfer Curves

The voltage transfer curve of Figure 5-4 gave essential inverter information but was swept
slowly (static curve). It did not represent the circuit behavior during its rapid transition. The
input signal switching time for modern inverters can be tens of picoseconds, and parasitic
capacitance of the transistors and the external wiring load alter the phase relation between
Vi and VO . An inverter and its transfer curve phase relation are shown in Figure 5-8 for
different input speed transitions, showing that for rapid transitions the drain voltage lags
the input gate voltage changes.
The circuit model for the inverter dynamic analysis in Figure 5-8a shows two parasitic
capacitances that are important during the transition. C L represents the combined effects
of the drain diffusion region capacitance, interconnect wiring, and a load gate input ca-
pacitance. The second capacitance is the input–output capacitance (called the coupling
capacitance C coup ). It is strongly bias dependent and is the parallel overlapping gate-drain
capacitance from the nMOS and pMOS devices.
Figure 5-8b shows simulated transfer curves for static, (1) medium speed, (2) higher
speed, and (3) very high-speed input voltage transitions. These curves show hysteresis.

2.00
(3)
VDD 1.75
(2)
1.50
1.25 (1)
Vin Ccoup VO
VO (V)

1.00
Static
0.75
CL 0.50
(1)
0.25 (2)
0 (3)

0 0.25 0.50 0.75 1.00 1.25 1.50 1.75

Vin (V)
(a) (b)

FIGURE 5-8.
(a) Dynamic CMOS inverter circuit model. (b) Transfer curves for output high to low and output
low to high for different input ramp speeds.
5.6 Graphical Analysis of VTC 139

2.00
Vin
1.75
VO3
VO2
1.50
VO1
1.25
1.00
VO (V)

0.75
0.50
VO1
0.25
VO3 VO2
0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t (ns)

FIGURE 5-9.
Timing responses for different cases for a dynamic inverter transition.

The forward VTCs of VO are shown in the upper portion of Figure 5-8b, and the reverse
transition is shown in the lower portion. Curves (2) and (3) in Figure 5-8b show that the
output drain node remains at a relatively high voltage when the gate input has almost
completed its low to high transition. The same phenomenon holds when the gate input
switches rapidly from high to low. The drain remains in a low voltage state until the input
has almost completed its transition. The circuit parasitic capacitance causes this phase
relation. A slow transition of the static curve allows time for the drain nodes to exactly
follow the input gate voltage in time. Curve (1) is an intermediate case where the output is
larger than VDD /2 when the input reaches its final value, although it is far from the static
transfer curve. These curves are dominantly a function of C L and the switching speed.
Figure 5-9 plots the output voltage timing responses for different values of C L when
the input transition times are set to a constant rate of change. Curve VO3 corresponds to
a small output capacitance, and the output voltage is almost zero when the input reaches
VDD . This case is similar to the static transfer curve. As the load capacitance increases
for curve VO2 the output transition time increases. Further increase in load capacitance
slows the transition time even more (VO1 ). In all cases the output voltage initially goes
beyond VDD due to overshoot caused by the charge injected from the input through the
coupling capacitance Ccoup . During this period there is a small current from the output
node through the pMOS transistor back to the supply terminal.
For high-speed transitions the coupling capacitance Ccoup tries to maintain its initial
voltage difference between the input and the output (−VDD for a low-high input transition
and +VDD for a high-low one). But charge is delivered through Ccoup to node VO , and C L
cannot respond other than to accept new charge. The charge injection is more rapid than
140 The CMOS Inverter

C L can move charge through the transistor paths to the rails. The change in output node
voltage is dv = dq/C. This temporarily drives the output voltage beyond VDD (overshoot)
for an input rising transition and below ground for a falling edge (undershoot) (Figure 5-9).
Circuit simulators are the best tool to compute the timing waveforms.

5.7. Inverter Transition Speed Model

An exact calculation of the propagation delay of an inverter requires complex differential
equations. We will derive a simple model assuming that the transistor is an ideal current
source, i.e. the transistor is always in saturation during the transition. The current source Io
in Figure 5-10a represents the pMOS transistor in saturation since that bias state dominates
the transition rise time and C L is the load capacitance. The nMOS transistor is assumed
off for this simple model of rise time. The saturated state model for a pMOS pull-up is
µn Cox W
I O = I Dp = (VGS − Vtp )2 (5-6)
2 L
µε
where C ox =
Tox
The capacitance expression for current, voltage, and time is
dV(t)
i (t) = C L
dt
If i (t) = I O (a constant current) and we approximate dv(t)/dt = v(t)/ t, then
Io
V (t) = t (5-7)
CL

VDD VDD VO

Io
On Off

VO
VO V = VDD
CL

CL
Off On Io t
t=0

(a) (b)

FIGURE 5-10.
(a) Circuit model to estimate rise and fall delays in a CMOS inverter. (b) Capacitance voltage
response to constant current.
5.7 Inverter Transition Speed Model 141

8 8
7 7
6 6
5 5
Delay

Delay
4 4
3 3
2 2
1 1
0 0
0.5 1.5 2.5 3.5 4.5 5.5 0.0 0.5 1.0 1.5 2.0 2.5
VDD (V) Vtp
(a) (b)

FIGURE 5-11.
(a) Normalized delay versus supply voltage for a constant Vt for the model in Eq. (5-9).
(b) Normalized delay versus threshold voltage for a constant VDD for the model in Eq. (5-9).

If t is the delay or rise time τr in Figure 5-10b for the signal to rise to V (t) = VDD
then Eq. (5-7) is rewritten as
C L VDD
τr = (5-8)
Io
Substituting Eq. (5-6) into Eq. (5-8) with VGS = VDD gives

2L 1
τr = C L VDD (5-9)
W µ p Cox (−VDD − Vtp )2

Eq. (5-9) shows that time delay is asymptotically related to the difference in VDD and the
threshold voltage. Figure 5-11a plots the time delay versus VDD for C L = 20 fF, K p =
75 µA/V2 , Vtp = −0.5 V, and W /L = 2. Time delay asymptotically approaches infinity
as VDD approaches Vtp . The plot also shows a significant property when VDD |Vtp |. The
change in transition delay time is small for small variations in the power supply level. If
VDD drops from 5 V to 4.5 V, the change in delay is small. This is an important noise
protection since power supply and GND levels are noisy from clock to clock period.
The result is similar if Vt varies for a fixed VDD . Figure 5-11b is similar to Figure 5-10a,
but with time delay plotted against Vt for VDD = 2.5 V. The plots show that circuit delay
is very sensitive to the difference in VDD and Vt in certain regions of the curves.
A similar derivation for the pull-down delay or fall time τ f using the nMOS transistor
gives
2L 1
τ f = C L VDD (5-10)
W µn Cox (VDD − Vtn )2
142 The CMOS Inverter

EXAMPLE 5-7

(a) An inverter has C L = 100 fF and a current drive I O = 400 µA. What value of VDD
is required to hold the signal rise time to 300 ps?
Use Eq. (4.7)
τr × I O (300 ps)(400 µA)
VDD = = = 1.2 V
CL 100 fF
(b) If VDD = 1.5 V, what is τ r ?
(100 fF)(1.5 V)
τ= = 375 ps
400 µA

In this case, τr increased to 375 ps because the transition output voltage amplitude increased
with VDD increase. The example assumed that the drive current was constant.

EXAMPLE 5-8
Given that C L = 10 fF, µε/2Tox = 59 µA/V2 , W /L = 6, and VDD = 2.3 V, initially Vtn =
0.6 V. If Vtn is reduced to 0.2 V, what is the ratio decrease in fall time?
You can substitute the values into Eq. (5-9) and take the ratio or divide Eq. (5-9) by
itself substituting Vt = 0.6 V and Vt = 0.2 V. You get
τ f (Vt = 0.6 V) (2.3 − 0.2)2
= = 1.526
τ f (Vt = 0.2 V) (2.3 − 0.6)2

Self-Exercise 5-11
A pMOS transistor has Vtp = −0.5 V, K p = 70 µA/V2 , (W /L) p = 4, and VDD = 2 V.
Estimate the rise time delay for an inverter with a load of 100 fF.
Answer: τr = 317.5 ps

Self-Exercise 5-12
An nMOS transistor has Vtn = 0.35 V, K n = 120 µA/V2 , (W /L)n = 3, and VDD = 1 V.
Estimate the 90% fall time delay (0.9 VDD ) for an inverter with a load of 10 fF.
Answer: τf = 59.2 ps
5.8 CMOS Inverter Power 143

Self-Exercise 5-13
Transistors in a CMOS inverter have C L = 50 fF, Vtn = 0.4 V, Vtp = −0.4 V, K n =
100 µA/V2 , K p = 50 µA/V2 , and VDD = 1.5 V. What should the W /L ratios be for both
transistors if the circuit is to have equal rise and fall times of 200 ps?
W
Answer: = 3.1
L n
W
= 6.2
L p

The time delay τ is actually slower than calculated by the simple model of a single
transistor pulling the output node up or down. One reason is that the pMOS and nMOS
transistors as a pair siphon charge from each other that is intended for C L . While the pMOS
is trying to charge C L , the nMOS bleeds some of that charge to ground thus lengthening
the change of state. However, the simple model does identify the major parameters that
control logic transitions.

5.8. CMOS Inverter Power

An inverter has dynamic and static energy components. Dynamic dissipation has two
major components: (1) the charge–discharge of the logic gate load capacitance (transient
component); and (2) the short-circuit current from the supply to ground created during
the transition (Figure 5-6). Static dissipation for long channel transistors is due mainly
to reverse bias drain-substrate (well) pn junction leakage current from transistors in the
off-state. The dynamic power calculation requires computation of transient and short-
circuit components. This is typically small for a single logic gate, but it can be significant
when switching power includes millions of gates. Off-state leakage is a major concern for
modern, very short channel transistors, but that is a topic for an advanced course.

5.8.1. Transient Power

The dynamic power (Pd ) to charge and discharge a capacitance C L for a clock period Tclk
is
1 Tclk
Pd = i load (t)vo (t)dt (5-11)
Tclk 0

In one period, the output voltage changes from 0 V to VDD and then from VDD to 0 V.
Eq. (5-11) is rewritten using

dq dvload dvo
i load (t) = =C =C
dt dt dt
144 The CMOS Inverter

and
1 VDD 0
Pd = C L vo dvo + C L (VDD − vo ) dvo (5-12)
Tclk 0 VDD

giving
2
C L VDD 2
Pd = = C L VDD f clk (5-13)
Tclk
Eq. (5-13) shows that reducing the output capacitance, the supply voltage, or the operating
frequency will lower transient power. Since the power dependence on the supply voltage
is quadratic, lowering VDD is more efficient for reducing power dissipation than the other
two parameters. Notice Eq. (5-13) assumes an up and down transition in one clock period.
If a single transition occurred during one clock period, then Pd is reduced by half. A single
transition is typical for combinational logic circuits. A double transition per clock period is
typical of logic gates in the clock timing networks. Eq. (5-13) is often used as an estimate
of gross IC power despite inaccuracies as to how many gates are double transitioning, or
what fraction of the gates actually switch at all in a given clock period.
When a clock pulse drives the registers in an integrated circuit, a single switching occurs
in the combinational logic load gates. However, not every logic gate in the IC switches.
Typically, about 5–30% of the total combinational logic gates in an IC switch and draw
dynamic power in a single clock pulse. We define an activity coefficient α as the fraction
of logic gates in the IC that are expected to change state (switch) on a clock pulse. The
power equation Eq. (5-13) for a single transition period becomes
1 2
Pd = αC L VDD f clk (5-14)
2
α = 1 in a typical clock network, but some networks in the IC are intentionally gated off
from the clock to reduce power, and their activity coefficient is zero.

EXAMPLE 5-9
Given that a gated IC clock network has VDD = 1.5 V, α = 0.84, a total load capacitance
C L = 5 nF, and f clk = 2.6 GHz, what is the power dissipation in the clock network?

Pd = (1)(0.84)(5 × 10−9 )(1.52 )(2.6 × 109 ) = 24.57 W

Self-Exercise 5-14
For a combinational logic gate, α = 0.2, C L = 150 fF, VDD = 2 V, and f clk = 2 GHz.
(a) Calculate the circuit power dissipation.
(b) Calculate the power dissipation if VDD = 1.5 V.
Answer: (a) Pd = 120 µW. (b) Pd = 67.5 µW
5.8 CMOS Inverter Power 145

Self-Exercise 5-15
An IC has six combinational logic blocks driven by a clock. Each block has a 750 pF load,
VDD = 1.1 V, and f clk = 3 GHz. How many blocks must be turned off at any instant if the
total power of the IC clock network is to be less than 5 W. Use the gross assumption that
all the logic gates make either a single charge or discharge during a clock cycle.
Answer: Power per block is 1.36 W so only three blocks can be on at one time.

Self-Exercise 5-16
2
VDD goes from 1.2 V to VDD in a circuit with α = 1.
3
(a) Calculate the power dissipated in a combinational logic gate for both VDD values when
C L = 10 nF, and f clk = 1.5 GHz.
(b) Calculate the power dissipated in a clock logic gate when C L = 10 nF, VDD = 1.2 V,
and f clk = 1.5 GHz.

Answer: (a) P = 4.8 W, P = 10.8 W. (b) P = 21.6 W

5.8.2. Short-Circuit Power

Both transistors conduct when the input is changing, and the transition voltage is between
Vtn and VDD – |Vtp |. This creates a circuit current path from VDD to ground (Figure 5-6) that
may generate from 5 to 30% of the total switching power. This short-circuit power compo-
nent depends on device current strength, input transition time, and output capacitance. If
the transition time is long, then CMOS short-circuit current is active for a longer time. The
exact computation of short-circuit current is complex so we present an approximation.
Consider a symmetric inverter (i.e., K n = K p , and Vtn = −Vtp ) with no output load
and an input voltage transition having equal rise and fall times. The time interval when
both transistors conduct is from t1 to t3 in Figure 5-12. During the interval t1 − t2 the short
circuit current increases from zero to its maximum value Imax and the nMOS transistor is
saturated. Its drain current is
W
ID = Kn (Vi − Vtn )2 for 0 < I < Imax
L
Since the inverter was assumed symmetric with no load, the maximum current occurs at
Vin = VDD /2 and its shape is symmetric along the vertical axis at t = t2 . We compute a
mean current by integrating from t = 0 to t = T and dividing by the period T . There are
146 The CMOS Inverter

isc

VDD

VDD |Vtp|
Vin
VDD
Vtn
t1 t2 t3 t1 t2 t3

FIGURE 5-12.
A simplified view of the short-circuit current contribution over one clock period.

four equal area current segments to integrate in Figure 5-12 over the whole period T .

1 T 4 t2 W
Imean = I (t)dt = Kn (Vin (t) − Vtn )2 dt (5-15)
T 0 T t1 L

If the input voltage is a linear ramp of duration τ

VDD
Vin = t (5-16)
τ
t1 and t2 are given by

Vt τ
t1 = τ and t2 = (5-17)
VDD 2

Substituting Eqs. (5-16 and 5-17) into Eq. (5-15)

τ
2 2
W 1 VDD
Imean = K n t − Vtn dt (5-18)
L T τ
VT
VDD τ

This integral is of the type x 2 dx with x = (VDD /τ )t − Vt so the result is

1 W 1 τ
Imean = Kn (VDD − Vtn )3 (5-19)
6 L VDD T

Finally the power contribution is given by

Psc = VDD Imean (5-20)

5.9 Power and Power Supply Scaling 147

EXAMPLE 5-10
What is the short-circuit power in an inverter if VDD = 2 V, Vtn =−Vtp = 0.5 V, T = 500 ps,
f clk = 2 GHz, K n = 140 µA/V2 , W /L = 2, and the pulse rise and fall times are 100 ps?
1 2 1 100 ps
Imean = (140 µA) (2 − 0.5)3 = 15.75 µA
6 1 2V 500 ps
so

Psc = 2 V × 15.75 µA = 31.5 µW

Self-Exercise 5-17
The short-circuit current pulses in a CMOS inverter are modeled as rectangular pulses of
400 µA peak and 420 ps width. The clock frequency is 800 MHz and VDD = 1.2 V. Calculate
the short circuit power dissipation using Eq. (5-18).

420 ps
400 A

Isc

t
Answer: Psc = 161.3 µW

5.8.3. Quiescent Leakage Power

The current transfer curve in Figure 5-6 showed that the quiescent current at the two logic
states (0, VDD ) was quite low in the low nA range. Low leakage transistors lead to low
power ICs. However, as the transistors become smaller, other leakage mechanisms kick
in and the leakage can increase by orders of magnitude leading to ICs with DC leakages
ranging from 20 to 40 amps in high-frequency ICs such as in Internet servers. It is called
short channel leakage. Battery-operated ICs cannot stand this and use many tricks to bring
the current leakage under control. This is a huge problem and is beyond this introductory
course.

5.9. Power and Power Supply Scaling

The ratio of Vtn to VDD impacts several inverter properties. The saturated current equation is
µn ε W
ID = (VGS − Vtn )2 (5-21)
2Tox L
148 The CMOS Inverter

When VGS = VDD for logic circuits, Eq. (5-21) becomes

µn ε W
ID = (VDD − Vtn )2 (5-22)
2Tox L

When VDD decreases, several trade-offs occur:

• The voltage difference in the parenthesis (the gate overdrive) is smaller so the current
drive is less, and transistor speed is degraded. Load capacitance is charged and
discharged slower.
• As VDD drops, the the logic voltage traverses a smaller range giving a slight speed
compensating feature.
When VDD < (Vt − Vtp ) ≈ |2Vt | the transition slows, but interestingly only one transis-
tor is on at a time. There is essentially no transient current spike. Figure 5-13 shows
a transfer curve measurement at VDD = 1 V and VDD = 0.5 V for transistors with
thresholds on the order of 0.35 V. There is no current spike for the VDD = 0.5 V
measurement since VDD < Vtn + |Vtp |. The power reduction for this condition is large.

VDD 1V
1.0 1.0

0.8 0.8
IDD (mA)
VO (V)

0.6 0.6
VDD 0.5 V

0.4 0.4

0.2 0.2

0 0
0 0.2 0.4 0.6 0.8 1
Vin (V)

FIGURE 5-13.

Inverter transfer curves at two VDD values. Notice the absence of a short-circuit current spike for
VDD = 0.5 V where Vin was swept from 0.5 V to 0 V. You can understand this low power operation
if you sketch an inverter with VDD = 0.5 V. Follow both transistor’s on–off action as Vin goes from
0 V to 0.5 V.
5.9 Power and Power Supply Scaling 149

Low-power, battery-operated products such as electronic watches and medical implants

use this technique.

EXAMPLE 5-11
Vtn = 0.4 V and K n = 400 µA/V2 . What is the instantaneous peak power dissipation in a
symmetrical inverter during a switching event for (a) VDD = 2 V, and (b) VDD = 1.5 V?
2
(a) 2.0 V
I D = 400 µA − 0.4 = 144 µA
2
Psc = (1 V) (144 µA) = 144 µW
2
(b) 1.5 V
I D = 400 µA − 0.4 = 49 µA
2
Psc = (0.75 V) (49 µA) = 36.75 µW

The power and peak current show a marked reduction with decrease in VDD .

Self-Exercise 5-18
An inverter is driven by VDD = 1.0 V pulses.

(a) What is the mean drain current limit to keep power dissipation to <1 µW per pulse.
(b) If 105 inverters on a chip switch simultaneously for the values in part (a), what is the
mean current of the chip over one clock period.

Answers: (a) Imean = 1 µA. (b) Imean = 100 mA

Self-Exercise 5-19
The parameters for a symmetrical inverter are Vtn = 0.6 V, Vtp = −0.6 V, K n = 100 µA/V2 ,
K p = 50 µA/V2 , off-state leakage current is 1 pA, (W /L)n = 2, and (W /L) p = 5. Compare
peak current and peak power at

(a) VDD = 2 V
(b) VDD = 1.4 V
(c) VDD = 1.0 V

Answers: (a) I peak = 32 µA, Ppeak = 32 µW. (b) I peak = 2 µA, Ppeak = 1.4 µW.
(c) I peak = 1 pA, Ppeak = 0.5 pW
150 The CMOS Inverter

Self-Exercise 5-20
Figure 5.13 showed an inverter voltage transfer curve for VDD = 0.5 V. The curve actually
is for a reverse sweep of Vi from 0.5 V to 0 V.

(a) Draw the transfer curve if the sweep for Vi goes from 0 V to 0.5 V. Approximate this
forward sweep estimating Vtp from the 1.0 V VTC, and assume that Vtn = –Vtp .
(b) What is the width of the hysteresis zone?

Answer: (b) 0.26 V

5.10. Sizing Inverter Buffers to Drive Large Loads

A problem exists when a small logic gate must drive a large capacitive load C L . A fast
charge–discharge of a large load capacitance requires a large W /L of the driving transistors.
However, a large W /L is defeating, since its larger transistor gate area increases its own
logic input capacitance. Working backward, that would cause all preceding logic gates to
have ever larger W /L ratios. A better solution exists.
Instead, one approach for driving large loads at high speed uses successively larger
channel widths in a cascade of inverters to sufficiently increase the current drive of the last
stage. A circuit driving a large load is commonly known as a buffer, and a circuit designed
with successively larger inverters is known as a tapered buffer (Figure 5-14). When the
area of each stage increases by the same factor the circuit is called a fixed tapered buffer.
The fixed tapered buffer structure was proposed by Linholm in 1975 [1]. He used a
simple capacitance model making the W /L of a stage proportional to the size of the input
capacitance of the next stage, while the area of each inverter was proportional to the
channel width of the transistors. The overall buffer delay was optimized by minimizing
the delay of each stage.
Let each succeeding stage in the buffer in Figure 5-14 have transistor widths larger
than the previous one by a scale factor α. The first inverter is the smallest with an input

1 2 i 1 n 1

Vin Vout

i 1C
CL
Cin Ci in

FIGURE 5-14.

Tapered buffer structure.

5.10 Sizing Inverter Buffers to Drive Large Loads 151

capacitance C in , while the i-th stage has an input capacitance given by

Ci = α i−1 Cin i = 1, 2, . . . , n

The number of stages n is computed from

C L = α n Cn

then
CL
αn =
Cin
and
CL
ln
C in
n= (5-23)
ln α
α is computed by optimizing the delay. Assuming that the delay of the first stage driving
an identical one is τ 0 , the delay of the i-th stage is

tdi = ατ0 i = 1, 2, . . . , n

The global delay of the n stages is

n
td = tdi = nατ0
i =1

giving
CL α
td = ln τ0 (5-24)
Cin ln α
Differentiating (5-24) with respect to α and equating to zero, gives the optimum αopt as

αopt = e ≈ 2.7

while the optimum number of stages n opt is

CL
n opt = ln (5-25)
C in
This section seeks to impress that care must be taken in a design when a logic gate drives a
large capacitance. This occurs when an IC drives large capacitive loads such as an off-chip
board capacitance or on-chip bus lines.
152 The CMOS Inverter

EXAMPLE 5-12
How many buffer stages are need to optimally drive a 1 pF load if the driving gate has an
input capacitance of C in = 25 fF?
CL 1 pf
n = ln = ln = 3.7
Cin 25 fF
Therefore, a total of four buffer stages are needed.

Self-Exercise 5-21
An IC with a tapered buffer drives a load capacitance on a board that is 100 pF. The input
capacitance of the logic gate originating the signal is 100 fF, and that gate has W/L = 4.

(a) How many buffer gates are required to optimally drive that load using the fixed tapered
buffer model?

Answer: n = 6.9
Seven total stages are needed. We must insert five tapered stages between the original
gate and the output driver.

(b) Write the equation that predicts the W/L ratio of the final buffer in terms of the scaling
factor and the originating gate W/L
(c) What is the W /L ratio of the final output buffer driver to the board?

Answer: W/L = 1,614

Self-Exercise 5-22
A tapered buffer design has an input capacitance of 20 fF and a load capacitance of 5 pF.

(a) What is the required number of buffer stages to minimize the propagation delay?
(b) If the propagation delay of the first stage is 1.5 ns, what is the overall delay?

Answers: (a) n opt = 5.52 ⇒ 6 stages. (b) Td = 24.5 ns

5.11. Summary
This chapter examined detailed electronic properties of the inverter. The inverter properties
align with NAND, NOR, and other multi-input logic gates studied in the next chapter. Static
and dynamic transfer curves explain much of the speed and power behavior of integrated
circuits. Tapered buffers are commonly used in design to match small logic gate drive to
larger high input capacitance load gates. The next chapter expands these concepts to show
how the inverter leads to multi-input logic gates.
Exercises 153

References
[1] F. A. Linholm IEEE J. Solid State Circuits, SC-10, 2, pp. 106–109, April 1975.

Exercises
Inverter Static Voltage Characteristics 5-4. A CMOS inverter uses VDD = 0.9 V. VOH =
0.8 V, and VOL = 0.1 V. If the noise margins
5-1. A CMOS inverter has VDD = 1.2 V. VOH =
must be 20% of VDD , what are VIL and VIH ?
1.15 V, VOL = 0.15 V, VIH = 1.05 V, and
Draw the noise margin map and label.
VIL = 0.2 V. Calculate NM H , NM L , and draw
the noise margin map with appropriate labels VOUT VIN
of numbers.
VOUT VIN 0.8 V VIH
NMH
1.15 V
NMH 1.05 V
NML
VIL
0.1 V
NML
0.2 V 5-5. Graphically determine the change in logic
0.15 V threshold of the CMOS inverter transfer curve
in the figure if the curve shifts 0.2 V to the right
5-2. A logic gate noise margin parameters are in the midregion.
VIH = 1.6 V, VIL = 0.3 V, VOH = 1.7 V, and 1.8
VOL = 0.2 V. 1.6
(a) Calculate NM H .
1.4
(b) Calculate NM L .
1.2
(c) The input voltage is down to 1.7 V and a
VO (V)

1.0
negative 50 mV noise spike appears. What
0.8
happens to the circuit fidelity?
0.6
(d) The input voltage is down to 1.7 V and
0.4
a negative 150 mV noise spike appears.
What happens to the circuit fidelity? 0.2
0
5-3. Given the logic gate noise margins: NM H = 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
100 mV, NM L = 75 mV, and VDD = 2 V. Vin (V)
(a) If VIH = 1.75 V, what is VOH ?
(b) If VIL = 0.3 V, what is VOL ? 5-6. (a) Design the W p /Wn ratios of a CMOS
inverter for symmetrical static volt-
VOUT VIN age transfer characteristic. µn = 1400
cm2 /V · s, µ p = 500 cm2 /V · s, Vtn = 0.35
V, Vtp = –0.35 V, and VDD = 1.3 V.
100 mV

75 mV
154 The CMOS Inverter

(b) Redesign if Vtp = –0.45 V. VDD

VDD

5-12. Given VDD = 1.5 V, K p = 70 µA. K n =

120 µA, (W/L) p = 150, and (W/L)n = 75,
5-7. An inverter with a symmetrical voltage trans- use the ITC to calculate Vtp .
fer curve has a restriction that W p /Wn = 4.6. 600
VDD = 1.2 V, µn = 1530 cm2 /V · s, µ p = 540
cm2 /V · s, and Vtp = −0.4. What must Vtn be 500
set to satisfy this condition? 400
IDD ( A)
5-8. A CMOS inverter has transistor parameters: 300
K n (W/L)n = 100 µA/V2 , K p (W/L) p =
300 µA/V2 , Vtn = 0.7 V, Vtp = −0.75 V, and 200
VDD = 2.5 V. What fraction of the total output 100
voltage swing will the nMOS transistor be in
saturation? 0
0.0 0.3 0.5 0.8 1.0 1.3 1.5
5-9. A CMOS inverter has its nMOS transistor Vi (V)
in nonsaturation and its pMOS transistor in
saturation. Given K n = 50 µA/V2 , K p = 5-13. Given that VDD = 1.8 V, Vtn = 0.5 V, and
25 µA/V2 , Vtn = 0.5 V, Vtp = −0.6 V, K n = 100 µA/V2 , what is W /L of the nMOS
(W/L)n = 2, (W/L) p = 4, IDD = 11 µA, transistor?
and VDD = 2 V, calculate the inverter output
voltage VO .

Inverter Static Current Characteristics Vin

5-10. Given an inverter with VDD = 1.5 V, Vtn =
0.4 V, and Vtp = −0.4 V, calculate the peak
current during the transition if (W/L)n = 3,
(W/L) p = 7.5, K p = 50 µA/V2 , and K n =
3.0e 4
125 µA/V2 .
2.5e 4
5-11. An inverter has VDD = 2 V, Vtn = 0.5 V, Vtp =
–0.5 V, K n = 300 µA/V2 , K p = 200 µA/V2 , 2.0e 4
IDD (A)

(W/L)n = 2, and (W/L) p = 3. 1.5e 4

(a) If VIN = 0.8 V, what is IDD ?
1.0e 4
(b) The IDD solution in part (a) appears twice
in the current transfer curve. Use the 5.0e 5
pMOS equations to calculate the other
0.0e 0
VIN value to satisfy the current in part (a). 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Vin (V)
Exercises 155

5-14. IDD = 40 µA, (W/L)n = 2, K n = 100 µA, both transistors, what is the percent decrease
Vtn = 0.5 V, K p = 50 µA, Vtp = −0.5 V, and in speed of transition?
Vi < 1.5 V. What is Vi ?
Inverter Power
3V
5-19. Calculate the power dissipated by a cardiac
pacemaker circuit if f clk = 32.6 kHz, α =
4/1 0.1, VDD = 1.5 V, C L (per gate) = 300 fF, and
the number of logic gates = 10 k.
Vi VO
5-20. A clock network has C L = 10 nF, α = 1, and
2/1 VDD = 1.2 V. The maximum power dissipa-
tion allowed is 5 W. What is the maximum
clock frequency?
5-21. Use Figure 5-12. VDD = 0.9 V, Vtn = 0.2 V,
5-15. Given an inverter with Vtn = 0.4 V, Vtp = Vtp = −0.2 V, f clk = 3 GHz, W/L = 3, K n =
−0.35 V, K n = 200 µA/V2 , K p = 100 µA/V2 , 250 µA/V2 , and tr = t f = 40 ps. Calculate
(W/L)n = 2, and (W/L) p = 3, calculate the the mean current during the logic transition
peak drain current I peak during an in- and the average power dissipated in the chip.
verter transition for (a) VDD = 1.5 V and
(b) VDD = 1.0 V. Power Supply Scaling

Inverter Speed Property 5-22. Given an inverter with: Vtn = 0.4 V, Vtp =
–0.4 V, K n = 200 µA/V2 , K p = 100 µA/V2 ,
5-16. Use the transition time delay model where (W/L)n = 2, and (W/L) p = 3. Calculate
C L = 30 fF, VDD = 1.5 V, (W/L)n = 2, K n = the peak drain current I peak during an in-
100 µA/V2 , (W/L) p = 5, K p = 25 µA/V2 , verter transition for (a) VDD = 1.5 V and
Vtp = −0.35 V, and Vtn = 0.35 V. What is the (b) VDD = 1.0 V.
difference between rise and fall time of the
5-23. Psc must be kept under 1 W. The chip has
transition if defined between 0 V and 1.5 V?
VDD = 1.5 V, one million transistors, and
VDD α = 0.1. Assume that 106 transistors repre-
sent an equivalent 500 k inverters for analysis.
What is the mean drain current per inverter?
Sizing and Inverter Buffers
Vin VO
5-24. An output buffer has an input capacitance of
95 fF and a load capacitance of 100 pF. How
many inverters are required in a fixed tapered
CL
design to minimize the propagation delay?
5-25. A fixed tapered buffer has an input capacitance
of 1 pF. If the output stage must drive a load
5-17. If a pMOS transistor in an inverter has of 54 pF, how many stages are needed?
µε/2Tox = 28 µA/V2 , Vtp = −0.6 V, and
5-26. The number of tapered buffers in a design must
W/L = 6, what is the expected additional rise
be kept at no more than five to accommodate
time delay if the gate power supply voltage is
chip area constraints.
reduced from a normal VDD = 2.5 V to VDD =
(a) If the input gate capacitance is 50 fF, what
1.8 V with C L = 25 fF.
is the maximum load capacitance that can
5-18. A CMOS inverter has W/L = 6 for both tran- be driven?
sistors, Vtn = 0.6 V, Vtp = –0.6 V, and VDD = (b) What is the width ratio of the last inverter
2.3 V. If Vt is reduced to |Vt | = 0.2 V for W L to the first inverter in the chain Win ?