active In using THEORY: Apparatus

Required: Aim:
low. when clock pin into readandimportant field as
may this per EXPT.NO.
consideration
used memoryTheexperiment the The System To
read/writeEnable
have write specified design
in role single-port
pin the any programmable with
addresses in and
pin
triggers circuitvalue for block designing
we
is width P4 simulate
easing designa memory processor,
high, Write/Read Address
Clock Enable Input
Data dependingis diagram
the active in and
the Verilog. the gate
whilecircuit 64-bit basic depth, is Memories MEMORIES
DESIGN
high.operations is array basically ISE
write when on shown
the building
x define Xilinx
8-bit, (FPGA) using
operatior is it specifications of in the
active the the whichblocks e
thdesign 9.1i
Memory 64 8x boards. HDL.
circuit.figure memory
ishigh, is
required as
performed a
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Output Data memory defined
read in
data takes It each
hierarchy that
when
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used input a design stepspecifications. can
read/write few
and pin ofalso also
is and with
verification
perforned yourassumptions be
address common playsverifel
pin need, Then
an
dmodule
module
(single
addr_regl;
assignq= I/WThis I end Write
(posedgeclk)
I/beginalways @ reg PROGRAM:
blocks Continuous reg I/ output
/ [7:0]Declare [7:0] qinputclk,we, input
[(5: [7:0]
data,
addr,0] input
Variable
5:0]
is addr_reg<=
addr; (we) if
in the ram[addr]
data;<= addr ram[63:0]; port_ram
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assignment _reg; hold RAM
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behavior the
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returns address
memory NEW

data.
 FLOPS
EXPT.NO.
DIGITAL CIRCUIT DESIGN OF FLIP

Aim:
EDAv13.1 and to do the Transions
a) To construct the D-Flip flop in Tanner
Analysis.
And to verify the Snin
b) To analyze the response with appropriate wave forms.
Tools used:
1. Tanner Tools 1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:
1. Open S-Edit window.
2. Go to File ’ New ’ New design
3. Go to Cell>New View
4. Add libraries file to the New Cell.
Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputsand outputs by giving appropriate inputs.
Schematic Diagram:

Fig :D - Flip Flop Schematic

TnnerSpiceCode:

SPICE export by: SEDIT 13,12

Export time: FriSep 27 10:38:02 2019
Design: J1

Cell: Celll

View: view0
Export as: top-level cell
Export mode: hierarchical
Exclude .model: no
Exclude .end: no

Expand paths: yes

Wrap lines: no
Root path: C:Documents and Settings\AdministratorDesktop\J1
Exclude global pins:
Control property name: SPICE
*** Simulation Settings -General section
lib C:ADocuments and Settings\AdministratorMy Documents\Tanner EDATanner
Tools v13.1\Libraries Models\ Generic 025.lib" TT
****** *
** Subcircuits

.subckt NAND2CABOutl Out2 GndVdd

--- Devices: SPICE.ORDER < 0
*Design: LogicGates /Cell: NAND2C/View: Main/Page:
*Designed by: Tanner EDALibrary Development Team
*Organization: Tanner EDÁ- Tanner Research, Inc.
*Info: 2 Input NAND with complementary output.
*Date: 6/14/2007 1:47:11 AM
Revision: 2
 Devices: SPICEORDER >0 -------
MNI Out1 A10NMOS W=2.5uL=250n AS-2.25p PS-6.8u AD=2.25p
PD=6.8u
MN2 1BGnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD-2.25D
PD-6.8u
MN3 Out2 Outl Gnd 0NMOS W=2.5u L-250n AS=2.25p. PS=6.8u AD=2.25p
PD=6.8u
MPI Outl AVddVdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3,7511
AD=2.25p PD-6.8u
MP2 Outl BVddydd PMOS W=2.5u L=250n M-2 AS=1.5625p PS=3.75
AD=2.25p PD-6.8u
MP3 Out2 Outl Vddydd PMOS W=2.5u L=250n M-2AS=1.5625p PS=3.75u
AD=2.25p PD-6.8u
.ends

*** Simulation Settings - Parameters and SPICE Options *****

Devices: SPICE.ORDER == 0 ----

XNAND2C 1D CIk NSN 8 GndVdd NAND2C
XNAND2C 2 CIk N IN 3N 7 GndVdd NAND2C
XNAND2C 3 N 5QBar Q N 6 GndVdd NAND2C
XNAND2C 4Q N 3QBar N 4GndVdd NAND2C
XNAND2C 5 D DN IN 2 GndVdd NAND2C
*-- Devices: SPICE.ORDER>0 --
VVoltageSource 3 VddGnd DC 5
VVoltageSource_2 CIkGnd PULSE(0 5 0 5n Sn 95n 200n)
VVoltageSource_1 DGnd BIT({0100101111})
.PRINT TRAN V(D)
.PRINT TRAN V(CIk)
.PRINT TRAN V(O)
.PRINT TRAN V(QBar)
 b******* Simulation Settings - Analysis section
tran350ns500ns

.dclinsource VVoltageSource_2050.5
Gnd)
.printdev(Q.
****** Simulation Settings - Additional SPICE commands *********

.end

Outputresponses:

D-Flipflop waveforms
Layout Diagram:

Gnd
Tbdt

Layout Net list:

13.00/Extract Version 13.00
Circuit Extracted by Tanner Research's L-Edit Version
TDB File: Layoutl
Cell: Core Version 1.01
Extract Definition File: lights.ext

include lights.md
* NODE NAMEALIASES
1=UINAND2C 5/0ut2 (78, 54)
2=U1/NAND2C_4/Out2 (44, 54)
3 = U1/NAND2C_3/Out2(10, 54)
6= q(100, 12.5)
6= U1/NAND2C_3/0ut1 (2.52)
6= UI/NAND2C_4/A (20, 70)
7=Vdd (-101,4)
7=U1NAND2C I/Vdd (-51,86)
7=U1NAND2C_2/Vdd (-17,86)
7=UINAND2C_3/Vdd (-17,86)
7=U1NAND2C 4/Vdd (S1,86)
7=U1NAND2C_5/Vdd
8= d(-101, 106.5)
(85,86)
8=U1NAND2C_1/
8
= A
U1/NAND2C_5/A (-82,
(54,
70)
70)
8=UINAND2C 5/B (62,63)
9
9= =U1/NAND2C_1/Outl
UI/NAND2C 3/A
(-66, 52)
(-14,70)
10 =U1NAND2C
2/0utl(-32, 52)
10 = UlNAND2C 4/B (28,63)
1| =Ul/NAND2C _2/B (-40,63)
11 =U1/NAND2C _S/Outl (70, 52)
12 = clk-101,4.5)
12= U1NAND2C 1/B(-74,63)
12 =U1/NAND2C 2/A (48,70)
13= UI/NAND2C 2/0ut2 (-24, 54)
14 = U1/NAND2C 1/Out2 (-58, 54)
17 = Gnd (92,4)
17=U1NAND2C 1/Gnd (-S1,28)
17=UiNAND2C 2/Gnd (-17,28)
17 =U1NAND2C 3/Gnd (-17, 28)
17 =U1/NAND2C 4/Gnd (51,28)
17 =U1NAND2C 5/Gnd (85,28)
18 = gbar (100. 98.5)
18 = UINAND2C 3/B (-6,63)
18=U1/NAND2C 4/Outl (36,52)
 MI Vdd dUi/NAND2C 2/B Vdd PMOS L=2u W
W=28u AD=84p PD=34)
AS=84p PS=34u
M2 U1/NAND2C 2/B d VddVdd PMOS L=2u W=28u
A
AD=84p PD=34u
AS=144p PS-68u
M3 UI/NAND2C S/Out2 U1/NAND2C 2/B VddVdd PMOSS L=2u W=28u
AD=148p PD=68u AS=84p PS-34u
M4 Vdd UINAND2C 2/Outl qbarVdd PMOS L=2u W-28u AD=84p PD=34
AS=84p PS=34u
M5 qbar q VddVdd PMOSL2u W=28u AD-84p PD=34u AS=144p
M6U1NAND2C 4/0ut2 gbarVddVdd PMOS L=2u W=28u AD=148p
PS=68u
AS=84p PS=34u PD=68u
M7Vddgbar q Vdd PMOS L=2u W-28u AD=84p PD=34u AS=84p PS=341
M8 U1/NAND2C 3/Out2 q VddVdd PMOS L=2u W=28u AD=148p PD=68u
AS=84p PS=34u
M9 Gndd SGnd NMOS L=2u W-28u AD-122p PD=47u AS-28p PS=30u
M105d U1/NAND2C 2/BGnd NMOS L=2u W=28u AD-28p PD=30u
AS=148p PS-68u
MI1 U/NAND2C_ 5/Out2 U1/NAND2C_2/B GndGnd NMOS L=2u W-28u
AD=148p PD-68u AS=122p PS-47u
M12 Gnd U1/NAND2C 2/0ut1 4 Gnd NMOS L=2u W=28uAD=122p PD=47u
AS=28p PS=30u
M13 4q qbarGnd NMOS L=2u W=28u AD-28p PD=30u AS=148p PS=68u
M14UI/NAND2C 4/Out2 qbarGndGnd NMOS L=2u W=28u AD=148p
PD-68uAS=122p PS=47u
M1SUI/NAND2C 3/Out2 qGndGnd NMOS L=2u W=28uAD=148p PD=68u
AS=122p PS=47u
M16 q U1NAND2C_1/0ut l VddVdd PMOS L=2u W=28u AD=84p PD-34u
AS=144p PS-68u
M17 Vdd U1/NAND2C 2/B U1/NAND2C 2/Outl Vdd PMOS L=2u W=28u
AD=84p PD=34u AS=84p PS=34u
M18 U1NAND2C_2/Outl clkVddVdd PMOS L=2u W=28uAD=84p PD=340
AS=144p PS-68u
 S19U1NAND2C_2/
W=28u. 0ut2 U1/NAND2C
AD=148p PD=68u
AS=84p
2/Outl VddV dd
PMOS L=2u
w20 Vddclk PS=34u
U1/NAND2C_1/Outl
AS=84p PS=34u Vdd PMOS L=2u W-28u
AD=84p PD=34u
M21
UI/NAND2C_1/Outl
AS=144p PS-68u
d VddVdd
PMOS L=2u W=28u AD=84p
PD=34u
M22UINAND2C_1/ Out2AS=84p
W-28u AD=148p PD=68u U1/NAND2C 1/Out1 VddVdd PMOS L=2u
PS=34u
M23 Gndqbar 19 Gnd
NMOSL=2u W=28u AD=122p
M24 19 PD=47u AS=28p PS=30u
AS=148p PS-68uU1NAND2C_1/Outl
q Gnd
NMOSL=2u W=28u AD=28p PD=30u
M25 Gnd
AS=28p PS=30u
U1/NAND2C 2/B 16 Gnd NMOS L=2u
W=28u AD=122p PD=47u
M26 16 clk
U1/NAND2C 2/0utl Gnd NMOS L-2u W=28u AD=28p
AS=148p PS=68u PD=30u
M27 U1/NAND2C 2/0ut2
U1/NAND2C 2/Out1 GndGnd NMOS L=2u
W=28u AD=148p PD-68u AS=122p
M28 Gndclk 15 Gnd NMOS L=2u
PS=47u
W=28u
M29 15 dUINAND2C 1/Out1 Gnd AD=122p PD=47u AS-28p PS=30u
NMOS L=2u W=28u AD=28p PD=30u
AS=148p PS-68u
M30 U1/NAND2C
1/Out2U1/NAND2C 1/0utl GndGnd
W=28u AD=148p PD=68u NMOSL=2u
AS=122p PS=47u
*Total Nodes: 19
* Total Elements:30
*Total Number of Shorted Elements not written to the
SPICE file: 10
*Output Generation Elapsed Time: 0.000 sec
*Total Extract Elapsed Time: 1.875 sec
END
Result:
The D-Flip flop is constructed in Tanner EDA v13.1, the
nd waveforms are spice code is generateE
verified.
 EXPT.NO. DESIGN AND SIMULATE BASIC COMMON SOURCE,
COMMON GATE AND COMMON DRAIN
AMPLIFIERS
COMMON SOURCE AMPLIFIER
Aim:
To simulate the schematic of the common source and
common drain amplifier, and
Aen to perform the physical verification for the layout of the same.
TOOL REQUIRED:
Cadence Tool
cOMMON SOURCE AMPLIFIER:
Inelectronics, a common-source amplifier is one of three basic single-stage field
stect transistor (FET) amplifier topologies, typically used as a voltage or transconductance
smplifier. The easiest way to tellifa FET is common source, common drain, or common
examine where the signal enters and leaves. The remaining terminal is what is
inown as "common". In this example, the signal enters the gate, and exits the drain. The
nly terminal remaining is the source. This is acommon-source FET circuit. The analogous
lipolar junctiontransistor circuit is the common-emitter amplifier.
The common-source (CS) amplifier may be viewed as a transconductance amplifier
rasa voltage amplifier. (See clasification of amplifiers). Asa transconductance amplifier,
the inputvoitage is seen as modulating the current going to the load. Asa voltage amplifier,
Input voltage modulates the amount of current flowing through the FET, changing the
voltage across the output resistance according to Ohm's law. However, the FET device's
output resistance typically is not high enough for a reasonable transconductance amplifier
ideally infinite), nor low enough for adecent voltage amplifier (ideally zero). Another
najor drawback is the amplifier's limited high-frequency response.
CIRCUIT DIAGRAM:
Vdd

Vbias

Vout

Vin

Vss
1. Circuit diagram in schematic entry

nmo

2. Design entry for the test circuit

Library name Cellview name Properties/Comments
myDesugnLib cs amplifier Symbol
analogLib vin Define pulse specification as Ac
Magnitude = 1; DC oltage =0; Ofset
Voltage = 0; Amnplitude = 5 m;
Frequency = 1K
analogLib vdd, vss, gnd vdd = 2.5, vss =2.5;
vbias =-2.5

3.Output
IResr,onsp

10

-425

-4594

109 105 10 196

 COMMON GATE AMPLIFIER
This configuration is used less often than the
useful in, for example, CMOS RF common source or source follower. It
is
frequency.limitations ofthe FETs; it is receivers, especially when operating near the
and potentially has lower desirable because of the ease of impedancee matching
noise. Gray and Meyer provide a general reference for this
circuit. Although the MOS transistor is most famous for its use
in digital circuits, it can
alsobe used,as anamplifying device. Common Gate
outputiterminals shareethe "Gate of the
amplifier simply meansthe input and
amplifying transistor.
Vop
lo
ptoVout
D

COMMON DRAIN AMPLIFIER:

Vin
Common drain amnplifier is a source follower or buffer amplifier circuit using a
MOSFET. The output is simply equal to the input minus about 2.2V. The advantage of
this circuit is that the MOSFET can provide current and power gain; the
MOSFET
draws no current from the input. It provides low output impedance to any circit using
the output of the follower, meaning that the output will not drop under load.
Its output impedance is not as low as that of an emitter follower using a bipolar
transistor (as you can verify by connecting a resistor from the output to -15V), but it has
the advantage that the input impedance is infinite. The MOSFET is in saturation, so the
current across it is determined by the gate-source voltage. Since a current source keeps
the current constant, the gate-source voltage is also constant.
CIRCUIT DIAGRAM:
1.Cirçuit diagram in schematicentry
2. Design entry for the test circuit Properties/Comments
Cellview name
|Library name
cd amplifier Symbol
myDesugnLib
vsin
Define pulse specification as AC
analogLib Magnitude = 1; DC Voltage = 0:
Offset Voltage =0; Amplitude = 5 m:
Frequency = 1K

vdd, vss, gnd vdd = 2.5: vss =-2.5;

analogLib
3.Test circuit

cdo

-
frec-k

4. Output

15

RESULT:
a.The schematicfor the common source and
common drain amplifier is drawn au
verified the following: DCAnalysis, DC Analysis,
b. The Layout for the common Transient Analysis.
source and common drain amplifier is drawn au
verified the DRC,LVS, RC Extraction.
SIMULATED OUPUT:

eceoeceoeoeoeeo

91:/rery_single