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The document discusses the verification process of an RTL design with 15 features, each requiring 4 to 7 specific stimulus combinations for activation. It highlights the complexity of tracking stimulus combinations and emphasizes the importance of coverage analysis to ensure features are verified before manufacturing. Additionally, it introduces Universal Verification Methodology (UVM) as a set of classes and methods in SystemVerilog for structured verification.

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Ruturaj Nakum
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7 views2 pages

Session Offline Ya Offline Viewing A Stripped

The document discusses the verification process of an RTL design with 15 features, each requiring 4 to 7 specific stimulus combinations for activation. It highlights the complexity of tracking stimulus combinations and emphasizes the importance of coverage analysis to ensure features are verified before manufacturing. Additionally, it introduces Universal Verification Methodology (UVM) as a set of classes and methods in SystemVerilog for structured verification.

Uploaded by

Ruturaj Nakum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Session15

27 January 2025 16:05

We have an RTL design which has 15 features associated with it.


Each one of these features requires specific combination 4 to 7 different set of stimulus to activate it.
As a verification engineer
Any unchecked feature is a potential bug.
Digital engineer team 25 people
Single Deign Architect
4 to 5 design engineer
12 to 15 dv engineer
Embedded
FPGA

Each and every feature is verified to perfection before chip is gone further in manufacturing flow.
Keeping track of each and every stimulus combination and corresponding feature is complicated thing to do manually

80 keys keyboard, out of these let's say 50 are verified 50/80 x100 = 62.5 % coverage is done
How to track if a particular feature is working fine with the same eda tool simulating the conde?
Feature1 required 5 specific stimulus: in the monitor of my testbench, I can see the tx driven to the dut.
If this tx corresponds to specific stimulus required for feature1 I can conclude feature1 is verified.
Coverage only analyses if the feature is verified or not. It doesn't analyse if feature is working fine or not.
Coverage analysis gives percentage of verification completed by the testbench. This allows tracking of the project progress.
Coverage is not part of pre written constructs. It has to be written separately for each RTL depending on the features.

Coverage class
It instantiates covergroups
Represent a particular group of features
Covergroups instantiate coverpoints
Represent single feature or part of a feature
Coverpoints instantiate bins
Represent specific logic that needs to be followed for the analysis
Coverage class has a method to call covergroup analysis which ultimately gives final % coverage
Sample method is a pre written method which starts the analysis of covergroup calling it.

Read about coverage and try and practice it.

What is UVM ?
Universal Verification Methodology
$display("message format_specifier", variables); // display method
`uvm_info("ID", "message",VERBOSITY)
`uvm_info("ID", $psprintf("message format_specifier", variables),VERBOSITY)
Uvm is set of classes, methods, macros written in sv
Difference in SV and UVM is only the agenda with which you should go thru it.

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