Evaluation of Dual Mode Logic in 28nm FD-SOI

Technology
Ramiro Taco Itamar Levi Marco Lanuzza Alexander Fish
University of Calabria, Bar-Ilan University, University of Calabria, Bar-Ilan University,
Rende (CS), Italy. Ramat-Gan, Israel. Rende (CS), Italy. Ramat-Gan, Israel.

Abstract— For the first time, the Dual Mode Logic (DML) Ultra-thin box and body (UTBB) fully-depleted silicon-on-
technique is evaluated in 28 nm UTBB FD-SOI technology, with insulator (FD-SOI), is an emerging technology that leverages
the goal of improving energy efficiency for wide supply voltage the planar bulk CMOS process while keeping up the pace with
operation range. By combining the operating characteristics of the efficiency improvements projected by Moore’s law [4, 5].
the DML and the extended body bias capability of the Because it is a relatively simple technological evolution from
technology, energy efficient digital circuits that can effectively conventional CMOS process, the UTBB FD-SOI technology
benefit from adaptive voltage and frequency scaling techniques assures reduced die size and power consumption along with
can be defined. This manuscript reports evaluations of the DML increased performance and functionality, without the need for
against conventional static and dynamic CMOS logics for two
radical complex manufacturing steps. Devices belonging to
benchmarks in the 0.3V-1V supply voltage range. First, a NAND–
the ST 28 nm UTBB FD-SOI technology are planar CMOS
NOR chain was considered. Simulation results showed that the
DML approach assures roughly the 40% savings in terms of transistors fabricated in a 7 nm layer of silicon placed over a
energy consumption with respect to the static CMOS 25 nm buried oxide (BOX). The ultra-thin silicon ¿lm ensures
implementation and improves the speed about 20% in that all electrical paths between source and drain are con¿ned
comparison to the dynamic CMOS design. Second, a 16-bit Carry to the gate region, leading to improved sub-threshold slope
Skip Adder was considered. Due to the unique capability of the and drain-induced barrier lowering (DIBL) [4]. Moreover, the
DML to switch on-the-fly between static and dynamic modes of fully depleted channel of devices avoids the issue of random
operation, an improvement of more than 20% in terms of EDP dopant fluctuation, thus reducing device variability. Since the
was obtained in comparison to the conventional CMOS adder BOX constitutes a dielectric isolator of the source and drain
design. from the underlying n/p-well, the possible body bias range is
extended in comparison to standard bulk CMOS technologies,
Keywords— Dual mode logic (DML), low power. making body biasing a key feature of the UTBB FD-SOI
technology. Note that, the enlarged body bias range enables
both high performance and low power for increased energy
I. INTRODUCTION
efficiency [6].
The dual mode logic (DML) family was proposed by our In this manuscript, the DML technique is evaluated in 28
research group to provide low-granularity energy-delay nm STM UTBB FD-SOI technology targeting energy efficient
optimization down to the gate level [1-3]. As its main feature, designs with a wide supply voltage operation range. The
DML allows on-the-Ày change of the operation of the logic dependence of power dissipation (and performance) on the
gates between two working modes. In the static mode, DML supply voltage motivates the design of circuits with dynamic
exhibits very low energy consumption at the cost of reduced voltage and frequency scaling capability [7-9], where the
performance, as compared to standard CMOS logic. voltage (and frequency) can change as a function of the
Alternatively, DML gates can operate in the dynamic mode workload requirements. Clearly, achieving higher speed at
with significantly increased performance at the expense of lower supply voltages for some portion of the design may be
larger energy consumption. From a topological point of view, crucial when targeting high-speed, yet energy-efficient
a DML gate consists of a conventional CMOS gate with an systems. As shown below, the combination of DML properties
additional pre\dis-charge device to allow dynamic operation. and the extended body bias capability of the technology,
In the static mode, the clocked transistors are disabled and the makes it possible to design highly energy efficient digital
generic DML gate operates as its standard CMOS counterpart. systems which can effectively benefit from adaptive voltage
In the dynamic mode, the clocked transistors are turned “on” and frequency scaling (AVFS) techniques [8, 9].
or “off” governed by the logic level of the clock signal. In this
operation mode, speed comparable to that of conventional II. DML DESIGN OPTIMIZATION IN UTBB FD-SOI
dynamic logic gates is achieved along with higher robustness TECHNOLOGY
and better noise margins [1]. A detailed description of the This section focuses on design optimization and related
DML technique as well as an accurate comparison with properties of the DML primitives in UTBB FD-SOI
respect to its CMOS static and dynamic counterparts is technology. The DML technique is here compared in terms of
provided in [1-2], with reference to conventional bulk CMOS energy, delay and sensitivity to process variations against
technologies. conventional static and dynamic CMOS logic designs.

978-1-4673-6853-7/17/$31.00 ©2017 IEEE

 for the CMOS dynamic gates. To prevent charge loss and to
improve the noise tolerance, a weak keeper transistor was used
for the CMOS dynamic gates. A similar approach is not
required for DML gates where an inherent keeper (formed by
a transistor network complementary to the evaluation network)
already exists [1]. The static CMOS gates were sized for
symmetrical switching delay at 0.6V, where the strength of the
pull-down network was set to be equivalent to a single NMOS
sized with W= 240 nm. The strength of the evaluation network
of both DML and CMOS dynamic gates was set to be
equivalent to the corresponding transistor network of the static
CMOS gates. By contrast, in the case of DML design, the
transistors of the complementary network were sized with
W=120 nm to reduce intrinsic capacitances. As a
consequence, during the dynamic operation mode, the fast
transition is used for evaluation while the slow transition is
used for precharge. Note that fast evaluation is benefical for
the performance of the circuit (which is determined by the
length of the critical path during evaluation). On the contrary,
a slower transition is possible in precharge, as the precharge is
itself a parallel process. Obviously, this considerably favors
the speed in the dynamic operation mode at the expense of
Fig. 1. DML gate design strategy in UTBB FD-SOI technology: (a) Type increased delay in the static mode. Finally, the pre-
A un-footed, (b) Type B un-footed, (c) Type A footed, (d) Type B footed, charge/discharge transistors (of both DML and conventional
and (e) cross section. dynamic logic gates) were sized for the same strength of a
NMOS sized with W= 120 nm.
A. Design optimization Fig. 2 shows the comparative energy-delay results,
Fig. 1 illustrates the proposed design strategy for (a) Type obtained from the simulation setup discussed above. Here,
A un-footed, (b) Type B un-footed, (c) Type A footed and (d) data are provided for VDD ranging from 0.3V to 1V. Due to the
Type B footed DML gates, respectively. In UTBB FDSOI asymmetric transistor sizing, when operating in the static
there are two Well topologies, named Conventional Well mode, the DML design exhibits lower energy consumption (-
(CW) for Regular Voltage Threshold (RVT) devices, and Flip- 37%, on average) than its static CMOS counterpart, while
Well (FW) for Low Voltage Threshold (LVT) transistors. suffering from a larger delay (+64%, on average). When
With the CW, the Reverse Body Bias (RBB) range can be switching in the dynamic mode, the DML design achieves a
extended down to í3 V whereas for FW, the Forward Body 3.2 X frequency boost on average, with an energy
Bias (FBB) can be up to 3 V [8]. As shown in Fig. 1 (a-d), we consumption increase of about 1.9 X, on average. In the
considered the FW configuration to fully exploit the powerful dynamic mode, the DML chain is faster (20%, on average)
knob (not available in nanoscale bulk CMOS technologies) than the np-CMOS design while also consuming less energy
provided by the FBB to compensate for variations and/or to (20% energy consumption saved, on average) thanks to the
boost performances in a wide power supply operating range avoided keeper transistor (and the additional driving inverter).
[10]. Below, we only consider symmetrical back biasing with The main utilization of FDSOI technology in the context
Vbb=GND in the static operation mode, and three options in of this research has to do with the extended back-biasing. This
the dynamic operation mode (Vbb=GND/VDD/2*VDD). Our feature enables energy-delay space extension of a DML
physical design assures that for the considered back bias 150f
voltages, all the parasitic diodes associated with the devices 50f
0.6V CMOS stat.
CMOS dyn.
are always maintained in reverse mode (see Fig. 1(e)). 125f
DML stat. mode
Energy/Cycle (J)

40f DML dyn. mode

0.6V 0.5V
0.6V
Energy/Cycle (J)

30f
B. Performance and robustness analysis 100f 0.5V
0.5V 0.4V
20f +1.8X
The DML approach was compared to its CMOS static and 0.6V 0.4V
0.4V
75f
dynamic counterparts for a wide power supply range (VDD:
0.5V
10f
- 3.3X 0.4V

0.3V-1V). As the first benchmark, a test chain composed of 20 1n

Delay (s)
10n

50f
fan-out of four (FO4) interleaved NAND–NOR gates (1 1V
CMOS stat.
footed/headed gate each 5 gates to reasonably confine the 0.3V
25f CMOS dyn.
short circuit energy [1]) was considered. The NOR gates were DML stat. mode
implemented in the A topology whereas the NANDs were 0 DML dyn. mode
implemented in the B topology, constructing a structure
100p 1n 10n 100n
similar to a np-CMOS\NORA design. This way, the
Delay (s)
evaluation in the dynamic operation mode is performed by
parallel-connected transistors (i.e. to achieve higher speed). Fig. 2. Energy-Delay of the NAND-NOR chains for different power
For the sake of a fair comparison, the same choice was made supply voltages.
 200f
DML stat. mode (Vbb=GND) CMOS stat. (Vbb = GND)
15

[σ/μ]Delay(%)
DML dyn. mode (Vbb=GND) CMOS dyn. (Vbb = VDD)

100f FBB DML dyn. mode (Vbb=VDD) DML stat. mode (Vbb = GND)
10 DML dyn. mode (Vbb = VDD)
DML dyn. mode (Vbb=2*VDD)
Energy/Cycle (J)

0.9V 5
- 40% (a)

CMOS stat. (Vbb = GND)

0.5V 1V 100n

[μ+3σ]Delay(s)
CMOS dyn. (Vbb = VDD)
DML stat. mode (Vbb = GND)
0.3V
10n DML dyn. mode (Vbb = VDD)

10f
1n
(b)

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

200p 1n 10n 100n VDD (V)
Delay (s) Fig. 4. Impact of process variations on (a) delay variability and (b) 3-
sigma delay.
Fig. 3. Effect of the Forward Body Bias for the DML NAND-NOR chain.
four 4-bit Ripple Carry Adder (RCA) blocks (where the carry
design. This is illustrated in Fig. 3, where three different Vbb propagation path is designed in DML as explicitly indicated in
voltage levels are considered in the dynamic operation mode. Fig.5 (b)), and the DML-based skip logic. Only the ¿nal XOR
The strong body effect (~60-80mV/V) of the considered gates which produce the sum bits (Si =Pi XOR Ci) of each
technology makes it possible to effectively trade off energy for RCA are designed with standard CMOS logic.
performance at a given VDD. On the other hand, a combination The DML CSA was comparatively analyzed against its
of dynamic body bias and voltage scaling can be exploited for static CMOS counterpart for power supply voltage ranging
energy saving. For example, the same operating frequency from 0.3V to 1V. Due to the low noise tolerance and the larger
obtained in the static mode by the DML chain for VDD= 0.9V delay variability in the low voltage domain (as discussed in
can be achieved in the dynamic mode by operating at VDD=0.5 the previous section), the CMOS dynamic logic was not
with Vbb=1V. In this way, ~40% energy can be saved. considered in this analysis. Fig. 6 illustrates the obtained
To analyze the effects of process variations on the delay of the energy-delay simulation results. The energy was averaged
compared circuits, Monte Carlo (MC) simulations on 10,000 over 10K input combinations, whereas the delay refers to the
runs were performed. The results are shown in Fig. 4, which critical path delay. In this test, FBB influence was not
reports delay variability (defined as ı/μ, where μ and ı are the considered (i.e. Vbb=GND). However, it should be considered
mean and the standard deviation of the delay) and 3-sigma for future work since as it is an important design knob with
delay (defined as μ + 3ı). Dynamic CMOS logic presents a UTBB-SOI technology (as also confirmed by our examination
significantly higher delay variability (especially at lower reported in Section II).
VDDs) than that of the static CMOS. This is very likely due to When operating in the static mode, the DML CSA assures
the positive feedback associated with the keeper transistor, the lowest average energy consumption in the whole
which not only degrades the speed performance of dynamic considered power supply range. Moreover, the DML design
logic (because of the current contention with the evaluation achieves the lowest delay as it switches in the dynamic
network) but also increases the delay variability [11]. As
specified above, this positive feedback is not required for A[0:3] B[0:3] A[4:7] B[4:7] A[n-4:n-1] B[n-4:n-1]

DML gates, with a favourable impact on delay variability in CLK

the dynamic operation mode. Fig. 4(a) shows that delay Cin

4 bit
A 4 bit A
Co[7]
... 4 bit A
Cout

variability of the DML design (in both static and dynamic RCA DML RCA DML
RCA DML
B B B
P[0] P[1] P[2] P[3] P[0] P[1] P[2] P[3] P[0] P[1] P[2] P[3]

operating modes) is always under 7% over the whole Sel Sel Sel

considered VDD range. The MC results given in Fig. 4(b), S[0:3] S[4:7] S[n-4:n-1]
DML
demonstrate that as expected, the DML chain operating in the DML DML

static mode has the largest 3-sigma delay. By contrast, the (a)

DML design exhibits the lowest 3-sigma delay when operating CLK TYPE A FOOTED DML GATES

in the dynamic mode. Note that the 3-sigma delay of the

A[0] B[0] A[1] B[1] A[2] B[2] A[3] B[3]

CLK CLK
TYPE A

dynamic CMOS chain quickly degrades for lower power Cin Co[0] Co[1] Co[2] Co[3]

supply voltages (due to the larger variability) becoming about CLK

CARRY CARRY
GENERATOR CLK
CARRY
GENERATOR
CARRY
GENERATOR
GENERATOR
2 X than that of the dynamic DML design for VDD=0.3 V.
CLK CLK

Even (TYPE A) Odd (TYPE B) Even (TYPE A) Odd (TYPE B)

CLK CLK CLK CLK

III. CASE STUDY: 16-BIT CARRY SKIP ADDER

TYPE B TYPE B TYPE B TYPE B
Co[0] Co[2]
DML GATES

Static CMOS
A 16-bit Carry Skip Adder (CSA) was chosen as a second S [2] P[2] S [3] P[3]
Gates

(and more complex) benchmark to demonstrate and evaluate

S [0] P[0] S [1] P[1]

(b)

the characteristics of the DML design approach in FDSOI Fig. 5. 16-bit DML Carry Skip Adder: (a) top level architecture and (b)
schematic of the 4-bit Ripple Carry Adder block.
technology. As shown in Fig. 5(a), the circuit is composed of
 300f 25 % delay reduction
CMOS stat.
% energy reduction
DML stat. mode
Avg. Energy/Cycle (J)

% EDP reduction
DML dyn. mode 20
100f
15

0.5 V 10
- 35%
5

10f - 15%

100p 1n 10n 100n 0.3 0.6 1

VDD (V)
Delay (s)
Fig. 6. Comparative Energy/Delay results for the 16-bit Carry Skip Fig. 7. Delay, energy and energy-delay product improvements achieved
Adder. on the 16-bit DML Carry Skip Adder.

operation mode. For example, at VDD=0.5 V the DML CSA in in terms of EDP is achieved in comparison to the standard
the static operation mode reduces the average energy of about CMOS design.
35% in comparison to its static CMOS counterpart. At the
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