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Go to the Canvas front page.

Choose “Week 2” from the QUICKLINKS at the top.

WARMUP Scroll down to today’s date and look for the pdf

Represent the decimal number 625 in BCD and XS-3

Bonus: Represent the characters 625 in ASCII

What’s a warm up? I frequently give a question or a problem for you to think about during the few minutes before class
begins. It’s usually either a reminder of what we did last class, or a preview of where we’re going next. Doing them will
help you with comprehension and retention. If it’s a look back, I’ll give the answer before we begin but in general don’t
spend additional class time on it unless there’s an issue. If it’s a look ahead, you’ll see more about it during class.

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Upcoming ECE events
ECE Tailgates (3 hrs before kickoff)
Dietrick Lawn
• Sep 7
• Oct 17
• Nov 9 2
CMOS Logic
“Complementary” comes from having both n-channel and p-channel MOS transistors in networks that
are duals of each other.

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n-channel MOS: Switch Models
Ideally, the transistors are voltage-controlled switches that are either open (Z = ∞) or closed (Z = 0).

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p-channel MOS: Switch Models
Ideally, the transistors are voltage-controlled switches that are either open (Z = ∞) or closed (Z = 0).

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CMOS Logic: What’s going on?

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CMOS Logic: The Inverter

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CMOS Logic: Switch Models
Ideally, the transistors are voltage-controlled switches that are either open (Z = ∞) or closed (Z = 0).

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CMOS Logic: Switch Models
Using alternative transistor symbols highlights this “switch model” behavior.

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CMOS Logic: More Gates
We can make other logic gates with CMOS by connecting transistors in series/parallel combinations.
In general:
◦ The n-transistors provide pathways from logic-0 to the output.
◦ The p-transistors provide pathways from logic-1 to the output.
◦ Transistors in series represent AND branches
◦ Transistors in parallel represent OR branches.
◦ The pathways are duals of each other. (If one is a series connection, then the other is a parallel
connection.)
◦ No static path exists between VDD and ground.

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CMOS Logic: What’s going on?

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CMOS Logic: The NAND gate

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CMOS Logic: What’s going on?

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CMOS Logic: The NOR gate

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CMOS Logic: Other Examples

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CMOS Logic: Other Examples

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CMOS Logic: Other Examples

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CMOS Logic: Other Examples
Why not make an AND gate? It takes more transistors!

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Functional Completeness (NAND)
Preview: How many transistors are
required to build this circuit?

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QUICK THINK: Design a CMOS circuit that implements the following truth tables:
Reminder: Use pmos transistors in the PUN (pull up network) and nmos transistors in the PDN (pull down
network)

X Y F X Y F
0 0 1 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 1

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Summary
Logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR
Functional Completeness
CMOS Logic Gates

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ECE 2544: Fundamentals of
Digital Systems
SECTION 3: THE VERILOG HARDWARE DESCRIPTION
LANGUAGE – STRUCTURAL MODELS
Why Use a Language for Circuits?

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Why Use a Language for Circuits?

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Why Use a Language for Circuits?

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Why Use a Language
for Circuits?

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Why Use a Language for Circuits?

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Why Use a Language for Circuits?
Schematics quickly become tedious. Schematics often lack an obvious hierarchy, and contain complex
wiring and symbols.
Using a language provides a better means for exchanging information among designers within an
organization, or with a customer.
Physical prototyping is expensive and slow. Using a language allows a designer to model and simulate the
design before prototyping.
Using a language allows a designer to re-use previously design components.
Using a language (along with the associated tools) allows the designer toautomatically synthesize
working hardware from a description of the hardware.

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Popular Hardware Description Languages
VHDL – VHSIC Hardware Description Language
◦ Developed in 1987 for the Department of Defense as a documentation language.
◦ Inspired by the Ada programming language.
◦ Synthesis & simulation capabilities were added later.
Verilog
◦ Developed in 1984 by Phil Moorby as a simulation language.
◦ Development was driven by hardware design & ASIC industry.
◦ Synthesis capabilities were added later.
Recent developments
◦ SystemC
◦ SystemVerilog
◦ Analog extensions to VHDL & Verilog (mixed-signal)

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Hardware Description Languages
HDLs look like software, but they are used to model hardware.
◦ Similarities: Structured code that can be divided into sub-modules
◦ Differences: Timing is explicit in HDL, execution is concurrent rather than serial
HDLs support concurrency: more than one thing going on in the hardware at a time, many signals
changing simultaneously
HDLs support modeling at more than one level of abstraction
◦ Gates
◦ Boolean equations
◦ Register transfer
◦ Algorithms (we won’t use this in our course)
Verilog uses three types of models:
◦ Structural: Interconnections of components (gates, modules)
◦ Dataflow: Operations performed on signals
◦ Procedural: Algorithmic representation of circuit (we won’t use this either)

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Basic Ideas in Verilog
Hardware is captured in modules big_circuit
• Modules must be defined and instantiated instance instance
• Modules have a type circuit_A circuit_B
• Modules can be hierarchical

definition instance instance

circuit_A circuit_A circuit_B
AND AND … NOT …

OR OR instance instance
…
circuit_A circuit_B

definition
circuit_B
instance instance
AND AND … NOT … circuit_A circuit_B

OR OR …

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 Example

module mylogic(q, a, b, c); mylogic

input a, b, c; n1
keywords output q; a INV1
AND1 q
wire n1, n2;
instance
not INV1(n1, a);
names n2
or OR1(n2, b, c);
and AND1(q, n1, n2); b
OR1
endmodule c

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Ports

module mylogic(q, a, b, c); mylogic

input a, b, c; n1
output q; a INV1
AND1 q
wire n1, n2;
instance
not INV1(n1, a);
names n2
or OR1(n2, b, c);
and AND1(q, n1, n2); b
OR1
endmodule c

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Port Direction

module mylogic(q, a, b, c); mylogic

input a, b, c; n1
output q; a INV1
AND1 q
wire n1, n2;
instance
not INV1(n1, a);
names n2
or OR1(n2, b, c);
and AND1(q, n1, n2); b
OR1
endmodule c

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Internal Wires

module mylogic(q, a, b, c); mylogic

input a, b, c; n1
output q; a INV1
AND1 q
wire n1, n2;
instance
not INV1(n1, a);
names n2
or OR1(n2, b, c);
and AND1(q, n1, n2); b
OR1
endmodule c

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Submodule Instantiation

module mylogic(q, a, b, c); mylogic

input a, b, c; n1
output q; a INV1
AND1 q
wire n1, n2;
instance
not INV1(n1, a);
names n2
or OR1(n2, b, c);
and AND1(q, n1, n2); b
OR1
endmodule c

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 module mylogic(q, a, b, c);
input a, b, c;
output q;
wire n1, n2;

Submodule Instantiation
not INV1(n1, a);
or OR1(n2, b, c);
and AND1(q, n1, n2);
endmodule

module bigger_circuit
bigger_circuit

W a
X b q F
Y c

a
b q G

Z c

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 module mylogic(q, a, b, c);
input a, b, c;
output q;
wire n1, n2;

Submodule Instantiation
not INV1(n1, a);
or OR1(n2, b, c);
and AND1(q, n1, n2);
endmodule

module bigger_circuit (F,G,W,X,Y,Z);

input W,X,Y,Z; bigger_circuit
output F,G;
W a
mylogic BLOCK1 (F,W,X,Y); X b q F
mylogic BLOCK2 (G,F,Y,Z);
Y c

endmodule a
b q G

Z c

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Basic Concepts
Verilog is case-sensitive. It has similarities to the C programming language. Both of these are reasons to
be careful!
All Verilog keywords are lower-case.
List elements are comma-separated.
Statements are semicolon-terminated.

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