Characterization of Resistive Switching in

Nb:SrTiO3 Interface Memristors

First examiner:
Author:
prof. Tamalika BANERJEE
Tarek JABER
Second examiner :
(s4640330)
prof. Richard H ILDNER

Bachelor’s Thesis
To fulfill the requirements for the degree of
Bachelor of Science in Physics
at the University of Groningen

November 20, 2024

2

Contents
Page

Abstract 3

Acknowledgements 4

1 Introduction 5
1.1 Memristors and Neuromorphic Computing . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Research Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Theoretical Background 7
2.1 Semiconductor Junctions: Schottky Barriers . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Fermi Level Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Degenerate Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Charge transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.1 Thermionic Emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.2 Field Emission & Thermionic Field Emission . . . . . . . . . . . . . . . . . 12
2.6 Nb:STO and perovskite structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6.1 Interface states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Resistive Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Experimental Setup 15
3.1 Co/Nb:STO contact and device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Tools and Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 Keysight B1500A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2 Keithley 2400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Results & Discussion 18

4.1 I-V sweeps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Schottky Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 State Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Conclusion 24
5.1 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Bibliography 26

Appendices 29
A Time retention protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
B Richardson Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
C IV sweeps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
 3

Abstract
As transistors begin to reach a physical limit in their functionality with downsizing, the world of com-
puting is urging a new approach to assist and potentially replace transistors. Memristors are devices
that can retain certain information even after the power is turned off, opening the doors to neuromor-
phic computing architectures beyond von Neumann. The research presented here aims to study the
electrical properties of Nb:SrTiO3 interface-type memristors. The Keysight B1500A Semiconductor
Device Analyzer and the Keithley 2400 Graphical SMU are used to read the current and resistance
changes in the device at a given applied voltage. This report demonstrates the resistive switching in
Co/Nb:SrTiO3 contacts exploiting its I-V characteristic and further proving the possibility of multi-
level switching. Moreover, the charge transport mechanisms across the created Schottky barrier in the
metal/semiconductor interface is studied. These findings are explained using the migration of oxygen
vacancies within the device and the trapping/de-trapping of charges at the interface. Further research
on such properties will result in a better understanding of the fundamental physics that drives resistive
switching and better control of it.
4

Acknowledgments
I would like to express my sincerest gratitude to Prof. Dr. Tamalika Banejee for giving me the
chance to conduct this research as part of your group. Your continuous and unconditional support
has helped me develop my research, academic writing, and presentation skills throughout this project
while teaching me a very interesting and applicable topic in Physics.

I would also like to thank my PhD supervisor Walter Quiñonez. You taught me how to use the instru-
mentation and the theoretical concepts needed to conduct this research wonderfully. Your enthusiasm
and humor inspired me to continue working hard on this project.

Many thanks to the rest of the participants in the TAMSPIN research group. Ishitro Bhaduri,
Azminul Jaman, and Konstantinos Panagiotis Rompotis you have all made me feel so welcome
at TAMSPIN. I deeply appreciate your constant support in answering my questions and helping me
solve certain problems.

I am glad I chose to do my research in this group, and I wish you all the utmost success in your
respective projects and as a team.

Finally, I would like to thank my family and friends for the constant emotional and mental support
they have provided throughout the project. I couldn’t have done it without you guys!
Chapter 1 INTRODUCTION 5

1 Introduction
1.1 Memristors and Neuromorphic Computing
Over the past century, technology and computer devices have become increasingly capable, energy
efficient, and necessary for our daily lives. One electrical component, the transistor, is the main driver
of this fast evolution. Since their creation in 1947, transistors have been getting smaller and more
efficient, allowing them to be compiled in a dense array to generate high computing power. This
marked the start of Moore’s law [1], which predicts that the number of transistors on a microchip
will double about every two years, leading to a significant increase in computing power and perfor-
mance. Nevertheless, transistors can only get so small, and one can only fit so many of them on a
chip. Moreover, modern computational systems such as artificial intelligence, large neural networks,
and machine learning algorithms require faster and more efficient computational outputs. This urges
a new electrical component to aid or potentially replace transistors.

Until the 1970s, there were three fundamental electrical devices: the resistor, the inductor, and the
capacitor. These components established mathematical relations between charge, electrical flux, volt-
age, and current. While most of these were successfully connected with the three devices above, there
was a missing link between electrical flux and charge. In 1971, Professor Leon O. Chua proposed a
fourth component to create this link called the memristor [2], forming a basis for designing any elec-
trical circuit. These components and the relations they form between properties are shown in Figure 1.
Memristors are two-terminal devices that can be thought of as resistors with a memory, which means
that a memristor can remember the electrical state it was in after being switched off. This suggests
that memory operations and electrical computations are inherently correlated [3]. Unlike resistors,
memristors do not admit a constant resistance but instead regulate the flow of charges based on the
amount of current previously flowing through them.

Figure 1: The four fundamental electrical components [4]

6 Chapter 1 INTRODUCTION

Today, computers have separate random-access memory (RAM) and processing devices, which need
to continuously communicate with one another to process information. This separation is known as
von Neumann architecture, and while it has worked for decades, it lacks efficiency. On the other hand,
the memory and processing units in the brain are co-located within the synapse, making it much faster
and energy efficient than a computer. The human brain operates at 1 exaflop (1018 ) calculations per
second, consuming 25 W of energy. In contrast, a supercomputer operates at 200 petaflops, consum-
ing 10 MW of energy for equivalent computations [5].

In spite of this large discrepancy, memristors aim to model synaptic functionality in electrical devices
in what is known as neuromorphic computing architectures, which are based on memristive devices.
This research will focus on a device that, when put in contact with certain metals, achieves such func-
tionality: Niobium-doped Strontium Titanate (Nb:STO). The former is used to create an interface-type
metal/oxide Schottky structure memristor and has attracted considerable attention over filament-type
devices [6]. Nb:STO is a device of interest in Resistive Random Access Memory (ReRAM) because
of its high switching speeds, high power efficiency, and simple device integration [7, 8].

1.2 Research Questions

This research will study the electrical properties of Nb:STO and evaluate its endurance.
To summarize, this report focuses on the following problems:

Q1. What do current-voltage measurements on Nb:STO look like after three years of use?
Has the device degredated?

Q2. What are the different mechanisms that drive resistive switching in Nb:STO?

Q3. What charge transport mechanisms affect current conduction in Nb:STO?

1.3 Thesis Outline

This paper will first present a theoretical outline of semiconductors, Schottky junctions, and the vari-
ous mechanisms that give rise to resistive switching. Then, the experimental setup and methods used
to collect data are presented in detail. The results will then be presented and discussed before the
paper is concluded and the research questions answered.
Chapter 2 THEORETICAL BACKGROUND 7

2 Theoretical Background
Semiconductors are electrical compounds that show conductivity intermediate between metals and
insulators. The variation of conductivity as a function of temperature is a good criterion for differ-
entiation between metals and semiconductors. While the former’s conductivity remains constant, the
latter admits an increase in conductivity as a function of temperature. Semiconductors can be classi-
fied as intrinsic (identified by a ”perfect” crystal structure) or extrinsic, containing foreign atoms in
the form of impurities or defects. By this definition, Nb:STO is an extrinsic degenerate semiconductor
(Degeneracy is discussed in Section 2.2).

2.1 Semiconductor Junctions: Schottky Barriers

A p − n junction is one of the most fundamental junctions in solid-state electronics and circuitry. It
has many potential applications in lasers, LEDs, solar cells, detectors, waveform shapers, etc. These
junctions are formed by combining p− (containing an excess of holes) and n− (containing an excess
of electrons) type semiconductors. Upon combination, these two materials create a structure with
a uniform Fermi level and no net current (assuming no bias is applied), forcing the valence and
conduction bands to bend in energy space. The resulting p − n junction can be seen in Figure 2

Figure 2: p − n junction formation. Figure adapted from U.Mishra and J.Dingh [9].
8 Chapter 2 THEORETICAL BACKGROUND

A Schottky barrier is a metal-semiconductor junction that is more relevant to this study. This structure
carries the unique property of having a non-linear diode characteristic, resulting in a much faster
response given unipolar carrier transport [9]. The workings of the Schottky diode depend on its
response to external bias, allowing for the control of charge transport. Its band diagram is given in
Figure 3 where EFm and EFs are the Fermi energy levels of the metal and semiconductor, respectively.
Upon contact, the electrons move from the semiconductor to the metal side, leaving behind positively
charged dopants. Since the concentration of these dopants is much less than that of the electron in the
metal, the bands are bent upwards in a depletion region (W ) expressed in equation 1
s
2εs
W= φbi (1)
qND
where φbi is the built-in potential given by:
Ec −EF,n
φbi = φm − χs − q

The work functions (φ) refer to the minimum energy needed to extract an electron from the system,
and χs is the electron affinity. In the ideal case (no bandgap defects), the Schottky barrier height is
an important parameter defined as the difference in energies between the semiconductor’s conduction
band and the metal’s Fermi level as indicated in equation 2

φb = φm − χ s (2)

(a) Metal and n-type semiconductor before contact (b) Resulting structure upon contact

(c) Metal-semiconductor inter-

face

Figure 3: Band diagram of Schottky structures with an n-type semiconductor [9]

The Schottky barrier plays an important role in the resistive switching process. More precisely, the
change in Schottky barrier height/width under voltages of different polarities is responsible for the
different resistive states. More on this in section 2.3.
Chapter 2 THEORETICAL BACKGROUND 9

2.1.1 Fermi Level Pinning

While experimental evidence shows that Schottky barrier height is independent of the metal employed
under certain circumstances [9, 10], surface defects can lead to a distribution of electronic states
within the bandgap at the interface. As a result, the Fermi level will always tend towards a region
with a large surface state density, independent of other material properties. Therefore, the Fermi level
is said to be pinned and aligned with the semiconductor’s bandgap. If this is the case, then the barrier
height is no longer dependent on φm and is given by equation 3
1
φb ≈ Ebg (3)
2
where Ebg is the bandgap of the semiconductor. This is referred to as the Bardeen limit [11].

2.2 Degenerate Semiconductors

The electrical conductivity of a semiconductor can be changed by many orders of magnitude by dop-
ing. Interestingly, when the dopant density is greater than 1019 cm−3 , the semiconductor is referred to
as degenerate, with changes to its fundamental structure and properties. Regarding a band diagram,
the Fermi level is very close to or even slightly past the conduction band for n-type doping, as shown
on the right in Figure 4 (The dashed red area here represents a window in which the Fermi level
could be). As a result, heavy doping can lead to bandgap narrowing, changes in carrier concentra-
tion, mobility, and lifetime, and forming a band tail. More precisely, as large densities of impurity
ions are introduced, they form an impurity band that merges with the conduction band at high doping
concentrations. This forms a Fermi gas where conduction and donor electrons interact. This consid-
erably influences the density of states of the unperturbed material, making it very difficult to model
the carrier interactions in degenerate semiconductors [12].

n-type semiconductor Vacuum energy

n-type degenerate semiconductor

φs χs φs χs

Ec EF Ec
EF

Ev Ev

Figure 4: Band diagram of a (non-) degenerate semiconductor. Source: own image.

2.3 Biasing
Electrically biasing the metal/n-type semiconductor system directly induces a change in the Schottky
barrier height as demonstrated in Figure 5. When a forward (reverse) bias is applied, the electric field
at the interface changes, which reduces (increases) the potential difference at the barrier, reducing
10 Chapter 2 THEORETICAL BACKGROUND

(increasing) the band bending and leading to a smaller (larger) effective Schottky barrier height. Con-
sequently, different charge tranport mechanisms dominate depending on the bias applied. In forward
bias, the smaller barrier height facilitates conduction by overcoming the barrier (i.e., thermionic emis-
sion), while other transport mechanisms are less relevant. In reverse bias, the barrier height increases,
meaning electrons are less likely to have sufficient thermal energy to overcome the barrier. FE and
TFE are the leading transport mechanisms in this regime. Charge transport mechanisms are discussed
in detail in Section 2.5.

Forward Bias Reverse Bias

Metal n-type semiconductor Vacuum energy

Metal n-type semiconductor

φs χs
φm φm φbr χs
φs
φb f Ec
EFS
EFM EFM
Ec
EFS
Defects (interface states) within bandgap

Ev

Ev

Figure 5: Schottky Barrier band diagram in forward (left) and reverse (right) bias (φb f < φbr ).
Source: own image.

2.4 Doping
Doping is the process of introducing excess electrons or holes into the system to create mobile charge
carriers. Donors (Acceptors) are dopants that donate (accept) an electron to the conduction band
(from the valence band, creating a hole). Such impurities create a bound energy level near the con-
duction/valence band edge. Traditional doping mechanisms face some challenges when downscaling
due to the difficulty of precisely placing dopant atoms. Nevertheless, research shows that this can
be done by forming a monolayer of dopant-containing molecules, which acts as a template for accu-
rately positioning dopants [13]. Annealing is used further to ease the transition of dopants into the
semiconductor.
The role of doping in this research is to vary the amount and type of charge carriers in STO and modify
its band structure by introducing/altering energy levels in the bandgap. When Nb is introduced, Nb
atoms replace some Ti atoms in the lattice, donating an extra electron as seen in Figure 6. Doing so
drastically increases the concentration of electrons in the conduction band, directly influencing the
material’s conductive properties. As a result, STO goes from insulating to n-type semiconducting
Nb:STO. The doping concentration in the sample studied here is 0.1 wt%, which means that 1 in
every 1000 Titanium atoms in the structure is replaced with Niobium. Figure 6 depicts this doping
effect.
Moreover, higher doping concentrations may further alter the material’s properties and, in some cases,
induce metal-like conduction properties. Rana et al. [14] have shown that heavily doped Nb:STO
Chapter 2 THEORETICAL BACKGROUND 11

admits metal-like electrical resistivity curves. Doping also directly affects the band structure of STO
by increasing both the thermal and electrical conductivity of the system [15].

O Ti O Ti O Ti

Sr O Sr O Sr O

O Ti O Nb
Ti O Ti

Sr O Sr O Sr O

O Ti O Ti O Ti

Sr O Sr O Sr O

Figure 6: Nb-doped SrTiO3 . A Niobium atom replaces a Titanium atom, donating an electron to the
structure.

2.5 Charge transport

If the Schottky barrier is subject to a potential bias, the Fermi levels will shift, resulting in a flow
of electrons from the semiconductor (metal) side to the metal (semiconductor) side in the forward
(reverse) bias. Depending on the Schottky barrier height and profile, this flow of charge carriers can
happen through various transportation techniques presented below.

2.5.1 Thermionic Emission

This mechanism requires charge carriers to have sufficient (kinetic) energy to overcome the barrier
height in a Schottky interface. Here, we assume that all electrons in the semiconductor with kinetic
energy greater than the applied bias voltage Vbi can surmount the barrier. Hence, the barrier height is
the more significant parameter, while the barrier profile (width) is irrelevant. At thermal equilibrium
(no thermionic emission), the current flow from metal to semiconductor Jm→s and from semiconductor
to metal Js→m cancel each other out, resulting in no net current. For higher temperatures and low field
strengths, the flow of current via transmission over the barrier dominates and is described by the
temperature dependence of the distribution function [16]. First developed by Bethe [17], thermionic
emission theory is based off three assumptions [18]:

• The barrier height φB is much larger than KB T .

• Thermal equilibrium is established at the plane that determines the emission.
• The existence of a net current does not affect equilibrium (i.e., the thermionic process can be
described as a sum of two independent processes; the current flow from semiconductor to metal
Is→m and the current flow from metal to semiconductor Im→s .

The currents mentioned in the third assumption are given by equations 4 and 5
−qφb qV
Is→m = A∗ AT 2 exp( ) exp( ) (4)
KB T KB T
12 Chapter 2 THEORETICAL BACKGROUND

−qφb
Im→s = −A∗ AT 2 exp( ) (5)
KB T
where A∗ is the Richardson [19] constant (= 156Åcm−2 K −2 for Nb:STO [20]), A is the device area,
φB is Schottky barrier height, q is the elementary charge, and the rest have their usual meaning. The
Richardson constant here encapsulates all material-related emission properties. This includes the
effective mass me of electrons in the material, which defines how easily an electron can be emitted
by the material1 . Summation of equations 4 and 5 yields the net current across the Schottky Barrier
according to thermionic emission theory:
−qφb qV
I = A∗ AT 2 exp(
)[exp( ) − 1] (6)
KB T nKB T
where n is the ideality factor, an ideality factor of one means the charge transport is ideal (purely
thermionic), while values greater than one demonstrate non-ideal behavior. Equation 6 can be used
as a fit to determine the ideality factor and the Schottky barrier height when studying the charge
transport mechanisms across a junction. While most electrons have sufficient energy to overcome the
barrier in thermionic emission, other emission processes may contribute to the current flow, leading
to a deviation from n = 1. Such processes are discussed next.

2.5.2 Field Emission & Thermionic Field Emission

Field emission is the process by which an electron is released from a material due to a strong electric
field despite having a lower energy than the barrier. This process is responsible for any additional
current flow in either reverse or forward bias in Schottky barriers resulting from a strong electric
field. As electrons admit particle-wave duality, their wavefunction may extend across the barrier,
allowing them to tunnel through it rather than overcoming it at energies close to the Fermi level. Field
emission is especially dominant in low-temperature conditions.
Thermionic field emission is a combination of thermionic and field emission processes. In this case,
higher temperatures aid the electrons in moving higher ”up” the barrier, allowing them to tunnel
through an effectively thinner profile, which is more probable. These tunneling processes strongly
depend on the barrier profile and are more significant at lower doping levels, making them difficult to
quantify in a mathematical expression [21].
1 The full mathematical expression for the Richardson constant is given in Equation 8 of Appendix B
Chapter 2 THEORETICAL BACKGROUND 13

Metal n-type semiconductor

TE

TAFE

φbr
FE
Ec

EFM

Figure 7: Band diagram representation of charge transport mechanisms. Thermionic Emission

(TE), Field Emission (FE), and Thermally Assisted Field Emission (TAFE). Source: own image.

2.6 Nb:STO and perovskite structures

Perovskites are ABO3 ternary oxides, where A and B are metallic cations and O−2 is the anion.
The ideal perovskite structure is cubic, and charge neutrality is achieved using different A− and
B−site ion valences. In SrTiO3 , Strontium and Titanium play the role of ion valences, balancing out
the charges. These structures admit many special functional properties, most of which stem from
their non-reconstructive phase transitions [20]. One property relevant to this study is perovskite’s
ability to accommodate a large density of crystal defects/impurities while maintaining the same crystal
structure, the most common of which are oxygen vacancies. These defects can form due to high
annealing temperatures or during various fabrication processes.

Sr

Ti

Figure 8: STO perovskite crystal structure. Source: own image.

Nb:STO is a perovskite-structured oxide where a small fraction of Ti atoms is replaced with Nb.
It is important to distinguish between Nb-doped SrTiO3 (Nb:STO) and conventional, Silion-based
semiconductors. The dielectric permittivity constant of Strontium Titanate is relatively large (≈ 300)
14 Chapter 2 THEORETICAL BACKGROUND

and strongly dependent on the electric field. As a result, careful control of these electric fields allows
for manipulating the barrier height and width to facilitate resistive switching behavior.

2.6.1 Interface states

Many of the unique properties of Nb:STO are consequences of the presence of interface states at the
metal/oxide junction as seen in Figure 5. These states may arise due to chemical bonding differences,
structural defects, or electronic structure mismatches between the two materials. Consequently, as
the current flows from metal to semiconductor or vice versa, the charge carriers may get trapped in
these states, hindering the current flow. In addition, if both electrons and holes are trapped in interface
states, they may undergo recombination, reducing charge carrier transport efficiency. As a result, the
Schottky barrier height is altered, directly influencing electrical properties [22].

2.7 Resistive Switching

Resistive switching refers to the ability of a material to switch between resistance states under an
external electric field. This mechanism can occur due to the formation & rupture of conductive
filaments connecting electrodes within the bulk of a material (filamentary switching) or the device’s
active areal region (interface-type switching). The latter is the more relevant mechanism in Nb:STO.
More precisely, the resistive switching effect is driven by the migration of oxygen vacancies and the
trapping/de-trapping of charges at the metal/oxide interface, both of which affect the Schottky barrier
height and profile. These changes in the Schottky barrier are responsible for the switching effect.
When a voltage bias is applied, the oxide switches between two resistance states that can be in-
terpreted as the two states of binary code: a low resistance state (LRS) and a high resistance state
(HRS). These can be modeled as a ”1” or ON and ”0” or OFF, respectively. The switch from HRS to
LRS is called ”SET”, and the switch from LRS to HRS is called ”RESET”.
Chapter 3 EXPERIMENTAL SETUP 15

3 Experimental Setup
3.1 Co/Nb:STO contact and device
The sample used for all the measurements in this research is a DGO3—Co (20 nm)/Nb:STO (0.1 wt%)
contact device. The sample is represented in Figure 9, and the specific device studied is highlighted in
blue. A two-probe configuration is used for measurements. Here, a metal probe makes contact with
the Cobalt metal, and a variable voltage is supplied through it. The Nb:STO substrate is grounded
and thus held at zero potential. The 2 × 2 device in Figure 9 was not chosen arbitrarily. Appendix 20
presents I-V sweeps conducted for all the devices in the second row of the matrix. The characteristic
with the least noise (i.e., the 2 × 2 device) was selected from the three.
Cobalt was chosen as a metal primarily because of the large mismatch between its work function and
the electron affinity of Nb:STO, which creates an effectively larger Schottky barrier. Moreover, the
migration of oxygen vacancies and charge trapping/de-trapping events at the interface are facilitated
in Cobalt compared to other metals with similar work functions [23].

Figure 9: Device selection and Co/Nb:STO contact Source: own image.

The device is assumed to be a circle with a diameter of 51 µm following the images in Figure 10

Figure 10: Microscopic images of device & size

16 Chapter 3 EXPERIMENTAL SETUP

3.2 Tools and Technologies

This research uses two different instruments to conduct measurements: the Keysight B1500A Semi-
conductor Device Parameter Analyzer and the Keithley 2400 Graphical Series Source Measurement
Unit (SMU). The former was used to conduct current-voltage sweeps, and the latter was used for time
retention measurements. All measurements were made at room temperature in ambient conditions.

3.2.1 Keysight B1500A

The Keysight instrument was used to obtain the I-V characteristic of the device used. As seen in
Figure 11, two probes are connected to the device on one end and the Keysight unit on the other. Two
different SMUs are used to make readings of the device’s currents and voltages.

Triaxial cable Triaxial cable

Force SMU 1 Out 1
SMU

Sense WGFMU 1
Keysight B1500A

Triaxial cable
Force
SMU

Triaxial cable
Sense
SMU 2 Out 2
WGFMU

Channel 1
WGFMU 2
Channel 2

Figure 11: Keysight B1500A Semiconductor Device Analyzer Setup. The probe in contact with the
silver (GND) was connected to SMU2, and the probe in contact with the sample was connected to
SMU1. Source: own image, adapted from A. S. Goossens [21].

The Keysight instrument allows for a careful setup of parameters to conduct measurements. Here, the
voltage sweeps were taken at many different intervals with a compliance of 100 mA to prevent high
currents from passing through the device as it may harm it. Sweeps were taken with 30 mV − 50 mV
steps depending on the sweep range. Regarding timing, all measurements were done with a delay
of 10 ms. This instrument is useful for I-V sweeps because one can integrate any function into the
system to personalize results. Here, the absolute value of the current is relevant to the study, and the
equation is implemented, yielding the absolute value as an output. The current-voltage sweeps were
performed 30 − 50 times per measurement using the repeated sweep function of the Keysight. This
ensures a more accurate set of results.
Chapter 3 EXPERIMENTAL SETUP 17

3.2.2 Keithley 2400

The Keithley instrument was used for time retention measurements. Figure 12 shows the exact cir-
cuitry used to conduct measurements. As in the previous setup, the probe in contact with the silver
is connected to the FORCE LO input on the instrument, and the other probe is connected to FORCE
HI. These inputs allow the device to emit and read currents and voltages. It is important to note that a
biaxial switching matrix was used here, simplifying the change from connected to disconnected (free)
circuits.
rix
at
m
h
itc
w
ls
ia
ax
Bi

Keithely 2400

Probe station
Figure 12: Keithley 2400 Graphical Series SMU Setup. The probe in contact with the Silver (GND)
is connected to the FORCE LO input through the switching matrix, and the probe in contact with the
substrate is connected to the FORCE HI input. Source: own image, probe station adapted from A. S.
Goossens [21].

This instrument allows for easy implementation of self-made voltage pulse protocols and directly
plots the resulting resistance as a function of time. The protocol used for these measurements can be
found in Appendix A, where 3 V is used as an initial condition to RESET the device in a HRS, the
readings are done at 0.3 V, and the writing at −0.5 V. The five pulses at said voltage ensure the device
settles in that state. Consequent reading events were done at a low voltage to prevent changing the
electrical conditions of the device. Finally, the writing events aim to reset the device in preparation
for consequent readings.

The following section will present and discuss all the relevant results obtained using this experimental
setup and methods.
18 Chapter 4 RESULTS & DISCUSSION

4 Results & Discussion

4.1 I-V sweeps
4.1.1 Results
Figure 19 shows fifty consecutive current-voltage sweeps carried out using a two-probe configuration
as seen in Figure 9. Using the Keysight B1500A instrument, the voltage sweep protocol used was
VSET → VRESET → VSET with different SET and RESET voltages. Figure 13 shows the full I-V sweep
of the 2 × 2 device.

Figure 13: Full I-V sweep. Protocol: +2V (SET) → −3V (RESET) → +2V (SET).

The sweep admits four areas represented by arrows following the sweeping direction. The device
starts in an LRS at a SET voltage of +2 V, as represented by arrow 1. The system remains in this
state as the voltage applies a negative bias (arrow 2) but switches to an HRS once the sweep reaches
−3 V. Following arrow 3, the device remains in the HRS until it completes an entire cycle, arriving
at +2 V. The sweep admits current transport in forward and reverse bias regimes, indicating apparent
hysteretic and resistive switching behavior. Furthermore, the resulting rectifying behavior and ex-
ponential I-V curves in the forward-bias region indicate the formation of a Schottky junction at the
Co/Nb:STO interface. The I-V curves were nearly invariant upon multiple measurements, indicat-
ing that the junction and materials were not undergoing any irreversible chemical or microstructural
changes throughout several sweeps.
The graph admits a noisy area in the HRS’ ∼ −1.5 V →∼ +0.5 V region due to limitations in the
Keysight instrument’s ability to detect low currents (at the nanoampere scale).
Chapter 4 RESULTS & DISCUSSION 19

Moreover, to demonstrate multi-level switching, I-V sweeps were performed at the same SET voltage
of +1 V and varying RESET voltages of −4 V, −3 V, −2 V, and − 1 V as shown in Figure 14

Figure 14: Multi-level switching. I-V sweep at a SET voltage of +1 V and varying RESET voltages
of −4 V (Black line), −3 V (Red line), −2 V (Blue line), and −1 V (Green line).

The resistance of the LRS remains constant with different sweeps since the SET voltage does not
change. On the other hand, the HRS resistance varies with varying RESET voltages, as expected. As
a result, Figure 14 shows that various resistance states can be attained by solely varying the RESET
voltage. These different states can be analogous to multi-level data storage systems for memory
applications.

4.1.2 Analysis
This section reports the differences in the device’s I-V characteristics after three years of usage (at
different periods, not continuously). Figure 15 shows a full sweep taken today next to the same sweep
taken three years ago. It is important to note that the size is not exactly the same, which may be a
reason for minor differences. The device’s stability, performance, and reliability over the three years
can be assessed by examining the data from both I-V sweeps. This can provide valuable insights
into the long-term behavior and degradation of the device. As a first general observation, we can
see that today’s I-V characteristic on the left is shifted downwards vertically by about one order of
magnitude. This lower output current indicates a slight degradation in the device’s ability to conduct
current, which may be caused by physical damage to the device after many uses or intrinsic damage
to electrical properties upon repetitive exposure to a bias. As we progress through the characteristic
curve, we see both graphs admit similar shapes along the forward bias (2 V → 0 V). This is expected
20 Chapter 4 RESULTS & DISCUSSION

as the dominant transport mechanism in the forward bias regime is thermionic transport, which is
generally more consistent than quantum tunneling mechanisms. However, the older characteristic
reaches higher current values for the same voltage range under reverse bias in the LRS (0 V → −3 V).
For example, at −1 V, the older characteristic reaches a current value of about 10−4 A while the newer
one remains at about 10−6 A. This large discrepancy of 2 orders of magnitude further justifies that
the device has degraded over time. Furthermore, the HRS in reverse bias admits similar effects in that
the current drops faster in the newer measurement. One can conclude that the Schottky barrier height
and profile have changed over time, giving the device less ability to conduct current throughout the
sweep.
Furthermore, the newer characteristic admits a much noisier progression (−1.5 V → 0.5 V), which
could be caused by field emission effects and the physical limitation of detecting small currents of
the measuring instrument. These cause many fluctuations in the current as the charge carriers tunnel
through the barrier.

(a) Today (b) 3 years ago. Source: A. S. Goossens [24]

Figure 15: Comparison of I-V on the same device, three years apart.

The results in Figure 14 reveal the feasibility of multi-level resistance switching in Nb-doped SrTiO3
through modulation of the RESET voltage. When a negative bias is applied, the oxygen defects
move toward the cathode, increasing the resistance of the material and leading to a transition to the
HRS. The extent of resistance depends on the magnitude of the applied RESET voltage. In addition,
charge carriers can become trapped at defect sites. This increases the resistance value by reducing the
number of charge carriers available for conduction. As a result, various distinct HRS were achieved.
Another notable observation from this result is the stability of the LRS despite different RESET
voltages. When a positive voltage is applied, oxygen vacancies will likely move toward the anode
(Co), forming regions with a high density of oxygen vacancies. These areas remain stable because of
the strong electrostatic interaction between the oxygen vacancies, even when the RESET voltage is
varied. This movement of oxygen vacancies is depicted in Figure 16.
The ability to attain higher resistance states by controlling the RESET voltage demonstrates the tun-
ability of the resistive switching behavior. Multi-level data storage systems involve storing multiple
bits of information in a single cell by distinguishing more than two states. Multi-level switching is
analogous to such a system and is hence an important requirement for applications in multi-level cell
memory devices, non-volatile memory, and neuromorphic computing [25, 26].
Chapter 4 RESULTS & DISCUSSION 21

Figure 16: Distribution of oxygen vacancies in Low (left) and High (right) Resistance States
Source: own image.

4.2 Schottky Barrier

The Schottky barrier height and ideality factor were extracted from the I-V sweeps to further study
the specific charge transport mechanism. Using equation 7, we can evaluate the expected Schottky
barrier height of Co/Nb:STO given that the work function of Cobalt is 5 eV [27] and the electron
affinity of Nb:STO is about 4 eV [28, 29] This yields an (average) Schottky barrier height of:

φb (Co/Nb:STO) = φm (Co) − χs (Nb:STO)

= 5 eV − 4 eV = 1 eV (7)

Thermionic emission is the dominant transport mechanism in the forward bias regime as a result of
the small barrier height. Figure 17 represents the thermionic formula given in equation 6 fitted on one
of the full I-V sweeps performed. Multiple charge transport mechanisms may contribute to the curve,
so a small range of 0.70 V → 0.95 V was chosen where the current was stable, and the transport was
largely dominated by thermionic emission. This range also yielded the most linear progression of the
I-V characteristic in the forward bias regime in Figure 13, indicating thermionic-dominant transport.
22 Chapter 4 RESULTS & DISCUSSION

Figure 17: Thermionic fit to I-V sweep. The black line represents the sweep in the HRS, and the red
line represents the thermionic fit from equation 6. The parameters in the top-left were derived using
the plotting software and a fitting function.

As a result, the fit yielded values for the Schottky barrier of φB = 0.7457 ± 0.0186 eV and ideality
factor n = 2.29723 ± 0.10175. The error here is related to the fitting of the function onto the data
points. The deviation of the parameters from ideal values (φB = 1 eV, n = 1) can be attributed to
the presence of an interface layer and/or interface states (leading to Fermi level pinning), tunneling
current contributions, and the voltage dependence of the barrier height [30, 31]. Discrepancies in the
value of the Richardson constant may also contribute to this deviation. While the former has been
studied experimentally on Nb:STO, research shows that there may be device-to-device inhomogeneity
in its value [32]. Moreover, the ambient temperature was assumed to be 300K, while the actual room
temperature during the measurements may have differed. Along with the device size, these three
parameters change the structure of Equation 6, directly influencing the Schottky barrier height and
ideality factor values.

4.3 State Retention Characteristics

This section will study the 2 × 2 device’s retention characteristics, which refers to how long it can
maintain its electrical state. Voltage pulses were used to achieve this, followed by 20 subsequent
reads at +0.3 V, as seen in the protocol in Appendix A. Figure 18 is a graph of the current readings
as a function of time. Each data point here is associated with a reading event2 .
2 The
data points for the initial condition SET voltage of +3 V, the first set of reads, and the writing events at −0.5 V
have been omitted.
Chapter 4 RESULTS & DISCUSSION 23

Figure 18: Retention characteristics. Measurements were taken with a read voltage of +0.3 V after
a set voltage of +3 V (HRS). The writing events were done at −0.5 V.

The currents here admit a gradual approach to an intermediate level, indicating that the current sta-
bilizes moderately between the high and low resistance states as a function of time. Figure 18 only
contains data points for the currents in the HRS as the initial condition of the time protocol was set
at +3 V. LRS data points would show similar behavior but progress from a higher current value to a
lower one. Thus, the distinction between HRS and LRS diminishes until it reaches a stable value. The
relaxation of states may be associated with the migration of oxygen vacancies. Right after the writing
events, the oxygen vacancies in the device are close to the interfacial layer. As time progresses, these
vacancies diffuse within the material, leading to a relaxation in the current values. Oxygen vacancy
sites can also trap electrons, and the de-trapping of these electrons may lead to the decaying com-
ponent in the current trend [33]. While the time scale in this report is only 80 seconds, research has
shown that the device can admit two distinguishable states for hours and that the retention time is
tunable using different stimuli [24]. This behavior further justifies the reliability of the memristive
device for memory storage and computing applications.
24 Chapter 5 CONCLUSION

5 Conclusion
Niobium-doped Strontium Titanate has proven to be an efficient and reliable memristive device that
admits resistive switching. This paper has unraveled some of its most useful properties. The current-
voltage measurements have shown clear hysteretic behavior and the creation of two distinct resistive
states. In addition, multiple resistive states were achieved with constant SET voltage and varying RE-
SET voltages. Moreover, a thermionic fit on the I-V sweep indicated that thermionic emission is the
main charge transport mechanism in the forward bias regime. However, contributions from tunneling
currents may affect the extrapolated Schottky barrier height and ideality factor.

In brief, the research questions posed in Section 1.2 are adressed as follows:

A1. Upon examining the I-V sweeps of the studied device, a clear discrepancy in its ability
to conduct current was observed. More precisely, the newer characteristic demonstrated
that the device is less capable of conducting current than the older characteristic. This
indicates that the Schottky barrier height and profile have changed in the device over
time, which may be caused by physical damage to the device after repetitive use or
intrinsic damage to electrical properties upon exposure to bias.

A2. The hysteretic behavior of the I-V sweeps indicates that the device admits resistive
switching properties. Further examination of what drives resistive switching concluded
that the movement of oxygen vacancies and the trapping/de-trapping of charge carriers
in defect sites at the Co/Nb:STO interface are the mechanisms responsible for it.

A3. The current equation from thermionic emission theory was fitted to a small range of
the I-V sweep yielding values for the effective Schottky barrier height and ideality fac-
tor. These parameters reveal that the dominant transport mechanism in the forward bias
regime is indeed thermionic emission, as expected. Nevertheless, the large ideality factor
indicates that field emission contributions and trapping events contribute to the current
conduction process and are non-negligible.

While memristors are still in their early years of development, some companies such as Hewlett-
Packard (HP) and Hynix have already made collaborations in hopes of large-scale manufacturing
and the industry applicability of memristors for data storage applications [34]. Other companies are
still investigating the memristive behavior for applications in neuromorphic computing in hopes of
achieving synaptic-like functionality on a microchip [35].

5.1 Outlook
The study of Nb:STO has unveiled some significant properties and behaviors that show promise for
future applications in computing. Moving forward, several areas warrant further investigation to
develop the application of memristors:

• Material optimization: Further research on doping and defect engineering could enhance the
reliability and control of memristive devices. Investigating alternative dopants and their impact
on resistive switching could yield a more scalable memristor. Further studies on the interface
states can also improve the stability and predictability of memristors.
Chapter 5 CONCLUSION 25

• Charge transport mechanisms: While thermionic emission is a well-understood mode of

transport, advanced characterization techniques are needed to fully understand contributions
from field emissions and tunneling currents. This would require the development of a reliable
and accurate mathematical expression for such emission techniques.

• Scaling and integration: Many studies have been done on the electrical properties of Nb:STO.
However, developing scalable fabrication techniques to integrate these devices into existing
semiconductor technology is crucial.
26 BIBLIOGRAPHY

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APPENDICES 29

Appendices
A Time retention protocol
The protocol used for time retention measurements is given below. The reading events at +0.3 V were
performed 20 times after each writing event. For the sake of space, the sample below only shows a
few of the readings.

3
3
3
3
3
0.3
0.3
0.3
...
-0.5
0.3
0.3
0.3
...
-0.5
0.3
...

B Richardson Constant
Equation 8 shows the mathematical expression for the Richardson constant, which is estimated to be
= 156Å cm−2 K−2 for Nb:STO [20]

4πeme ∗ k2
A∗ = (8)
h3
Where me ∗ is the effective electron mass, h is the Planck constant, and k is the Boltzmann constant.

C IV sweeps
30 APPENDICES

(a) [−1V − +1V ] (b) [−2 − +2V ]

(c) [−2V − +3V ] (d) [+1V − −2V ]

(e) [+1V − −3V ] (f) [+1V − −4V ]

Figure 19: I-V sweeps at different voltage ranges for 2x2 device
APPENDICES 31

(a) −2V − +3V , [1 × 2] device (b) −2V − +3V , [2 × 2] device

(c) −2V − +3V , [3 × 2] device

Figure 20: I-V sweeps for all devices in the second row of the matrix of the device (as in figure 9)