IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

Design and Implementation of Izhikevich Spiking

Neuron Model on FPGA
Shanmukha Murali, Juneeth Kumar, Jayanth Kumar, Ramesh Bhakthavatchalu

Abstract—The elementary processing units in brain are Knowing the biological plausibility of a single neuron through
neurons which are connected to each other in many shapes and Hodgkin and Huxley [6] model, this work models Izhikevich
sizes. A typical neuron can be divided into functionally three spiking model [7] which is a mathematical model.
distinct parts called Dendrites, Soma and Axon. Dendrites play
the role of input device that collect signals from other neurons and
Over the past few years there is drastic change in the lifestyle
transmits them to soma. Soma performs a Non-linear operation, of humans which made them prone to many irregular
i.e. if input exceeds a certain threshold, an output signal is functionalities of brain. The study of neurons is helpful to
generated. This output signal is taken over by an output device, know what is happening inside the brain which would help us
the Axon, which delivers the signal to other neurons. This is the implementing the spiking neuron models. The input to these
basic function of a biological neuron. A biological neuron model models is current (I) which is in order of nA. The work is to
which is also known as Spiking Neuron Model is a mathematical
description of properties of neuron that is to be designed design and implement 20 neuro-computational properties
accurately to describe and predict the biological processes. So developed by Eugene M. Izhikevich, using‖Bit Optimization‖
there comes the concept of modelling and analysis of neurons. technique.
Modelling and analysis of neurons was performed by different
researchers on First, Second and Third generation of neurons. II. BACKGROUND STUDY AND WORKING OF
The Third generation of neurons are also called as spiking BIOLOGICAL NEURON
neurons. The focus of this work is to present different types of
spiking neurons developed by Izhikevich which mathematically There are two types of potentials generated by a neuron 1.
supports the properties and resembles the biological neuron. Resting potential 2. Action potential. The natural neuron has a
These mathematical model simulations are done in MATLAB. resting potential known as built in potential around -70 mV
These spiking neurons are modelled using digital logic circuits in
Verilog Hardware Description Language (HDL) and simulated in
when in equilibrium (at resting state) [4]. If the neuron is in
ModelSIM RTL simulator. resting potential then there will not be any message
The design is then implemented in Xilinx FPGA and checked for transmission. The action potentials are responsible for the
the functionality. message transmission. An action potential is a very rapid
change in membrane potential that occurs when a nerve cell
Keywords-Spiking Neurons, Bit Optimization, Verilog, FPGA, membrane is stimulated. Specifically, the membrane potential
MATLAB, ModelSIM. goes from the resting potential (typically -70 mV) to some
positive value (typically about +30 mV) in a very short period
I. INTRODUCTION
of time (just a few milliseconds). Hodgkin & Huxley
Neurons are specialized cells that transmit electrical and developed a biological model by mapping the working of the
chemical signals to facilitate communication between brain and neurons into different parameters and mathematical equations.
body. Neurons play the most vital role in our metabolism. Izhikevich proposed a mathematical model in which the
Assuming biological neuron as a system (Dendrites as input, parameters does not have any relation with biological
Soma as processing unit, Axon as output), Spiking Neuron parameters of neuron and yet produce spikes as biological
model means developing a system which mathematically neurons. The below figures are one of the 20 neuro-
mimics the biological neuron. Spiking Neurons consider the computational properties known as Phasic Spiking which are
timing of information, mimicking biological neurons [1] [2] [3] being implemented in MATLAB using both Hodgkin-Huxley
more closely. Biological neurons generate action potentials & Izhikevich models.
also known as spikes, whose electrical pulses last an average of
one millisecond (1ms) [4]-[5]. The variations in neuron
generations lead to increase of realism in a neuron simulation.
Spiking neuron falls into the third generation of neuron
network models. In Spiking Neuron the communication
happens in the form of pulses or spikes. Our brain is a network
of neurons.
ShanmukhaMurali, Dept. of Electronics and Communication
Engineering,Amrita School of Engineering,Amritapuri,Amrita
Vishwavidyapeetam,Amrita University, India
Juneeth Kumar , Dept. of Electronics and Communication Engineering,Amrita
School of Engineering,Amritapuri,Amrita Vishwavidyapeetam,Amrita
University, India
Jayanth Kumar, Dept. of Electronics and Communication Engineering, Amrita
School of Engineering,Amritapuri,Amrita Vishwavidyapeetam,Amrita Fig.1: MATLAB plot of Hodgkin-Huxley Model
University, India,[email protected]
Ramesh Bhakthavatchalu, Dept. of Electronics and Communication
Engineering,Amrita School of Engineering,Amritapuri,Amrita
Vishwavidyapeetam,Amrita University, India, [email protected]

Authorized licensed use limited to: Amrita School Of Engineering - Kollam. Downloaded on December 17,2024 at 11:00:00 UTC from IEEE Xplore. Restrictions apply.
978-1-5090-0774-5/16/$31.00 © 2016 IEEE
946
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

All excitatory neurons are classified into four types: 1 .Regular

Spiking 2.Intrinsically Bursting 3.Chattering 4.Cortical
Excitatory [8] [12]. Both type of neurons have their respective
parameter values. By changing parameters and input currents
according to the kind of neuron results in different properties.
In this way Izhikevich modelled 20 properties of neuron [13]
[14].

Fig. 2: MATLAB plot of Izhikevich Model A. MATLAB Implementation

By comparing the above figures, both of them follow the same The above equations are implemented in Mat lab using the
shape and same peak voltage of 30mV. Even though one is a typical values used by Izhikevich and the output is found. The
Biological model and the other is a mathematical model, both range of values for each parameter are those, uptil which each
are producing the same plots. Hodgkin-Huxley model can one of the 20 neuro-computational plots are exhibiting same
describe the activity of a neuron accurately, the complexity of properties as Izhikevich plots as in fig 4. The plots in this
the model makes it hard to perform the intuitive analysis when figure are generated by using the typical values used by
compared to the Izhikevich model. The purpose for us to Izhikevich Model. The parametric values of all the 20 models
choose Izhikevich model is because it is computationally are varied to see to which extent the plots remain the same. The
simple and can fire patterns as that of biological neurons. first order differential equations modelled by Izhikevich are
solved using Euler‘s method of solving ordinary differential
III. IZHIKEVICH SPIKING MODEL equations. The MATLAB plots in fig-4 are generated with
input given as DC pulses with variable ‗I‘. By varying the
In this project the simulation results of the 20 parameters in (1) and (2) can produce the following matlab
neurocomputational properties are done using Mat lab which plots.

V‘(t) = 0.04V (t) 2+5V (t) +140− U (t) + I (t)(1) (1) (1)
U‘ (t) = a (b*V(t) − U (t)) (2)
If V(t) ≥ 30mV
V (t) = c (3)
U U(t)(t)
=U =U
(t)(t)
+ d+ d(4)
(4)
are referred from [8]. The Izhikevich model equation is

where ‗V(t)‘ represents the membrane potential of the neuron

and ‗U(t)‘ represents a membrane recovery variable, which
(3)
accounts for the activation of potassium(K+) ionic current and
inactivation of sodium(Na+) ionic current[6]. The constant ‗a‘
gives the decay rate of the spike. The constant ‗c‘ gives the
minimum value of the spike that have to reach after reaching
the maximum value. The constant ‗b‘ gives the sensitivity of Fig. 4: MATLAB plots of Izhikevich Model
the spike. The constant ‗d‘ gives the after-spike reset of the
recovery variable ‗U (t)‘. The input DC pulses are injected via
No model other than Izhikevich model can exhibit all the 20
variable ‗I‘.
neuron properties.

B. Bit Length Assignment

The neuron properties plotted in MATLAB are to be
implemented in Verilog. Firstly, for doing so each parameter in
the mathematical model has to be allocated with bit length to
implement the two equations. The decision for bit length for
each parameter is taken as follows. The fixed point
representation[15] is used in which fixed number of fractional
Fig. 3: Variation of parameters a, b, c and d, [8]
bits are present. Suppose, define the time scale parameter as
a=0.02. The ‗a‘ value is converted to its binary equivalent and
is reconstructed back to its original value. When this is done an
Neocortical neurons in mammalian cortex are classified into error is occurred between the original value and the
several types according to the pattern of their spiking and reconstructed value. Among the bit lengths with error less than
bursting. There are two kind of neurons. 1. Inhibitory Neurons 1%, the minimum bit length is considered.
2.Excitatory Neurons. All inhibitory neurons are classified into
Fast Spiking and Low Threshold spiking Neurons [9][10] [11].

947 on December 17,2024 at 11:00:00 UTC from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: Amrita School Of Engineering - Kollam. Downloaded
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

The table-I shows different values of parameter ‘a‘ and its error much are be truncated in order to save power and area for
representation in various bits lengths and its corresponding the circuit.
percentage of errors. One of the applications of Bit Optimization is shown in Table
TABLE I III which is used in Communication systems for transmitting
BIT LENGTH DECISIONS BASED ON ERROR % the data. The number of bits are truncated from 17 to 8 which
results in reduction of transmission power and hardware
a values Bitlength implementation.
The hardware implementation of the first order differential
a 11 12 13 14 15 equations (1) and (2) is shown in Fig.5 are solved using Euler‘s
method.
0.01 2.3438 2.3438 1.1230 0.5127 0.2074
TABLE III
0.02 2.3438 1.1230 0.5127 0.2075 0.0549 APPLICATION OF BIT OPTIMIZATION TECHNIQUE

0.03 0.7161 0.7161 0.3092 0.1058 0.0041 Value Binary Decimal Fractional Error (%)
value length length
0.04 1.1230 0.5127 0.2075 0.0549 0.0549
0.371 00.01011110 2 8 1.027

0.05 0.3096 0.3096 0.1465 0.0244 0.0244

2.57 010.10010 3 5 0.2918

0.371*2.57 0000.1111010000010 4 13 0.0106

It is understood from table-I that if the bit length is increased
the error percentage is reduced. Similarly, the bit lengths for
‗b‘, ‗c‘, ‗d‘, ‗V‘, ‗u‘, ‗tau‘ for the first iteration are found and 0.371*2.57 00.111101 2 6 0.0362
shown in table-II. (optimized)

TABLE II Fig.5 is the proposed architecture for the implementation of

PARAMETERS AND THEIR BIT LENGTHS FOR FIRST ITERATION first order equation (1) & (2) which are solved by using Euler's
method. The Multipliers, adders and Sub tractors implemented
Parameters total bits in the architecture are parameterized, which takes two inputs
and generates an output. The final output is again given as
a 13 feedback to the adder with the help of flip-flop.

b 12

c 9

d 7

V 9

u 11

Tau 8

C. Bit Optimisation
After implementing multiplication for one iteration in the
equation (2)a 34 bit result is obtained for U (t). When the
iteration is continued, the bit length keeps on increasing. Since
there is a feedback of the variable ‗U‘ to ‗V‘ and ‗V‘ to ‗U‘
there is an overflow of bits throughout the iterative process. So,
the revised bit length for the complete process is fixed using bit
optimization and shown in table-IV.
Fig. 5. Architecture
Bit Optimization is the method of truncating the bit length
with a minimum error change in the original value(approx. less In fig-6 the bit length of each stage is checked and
than 1%). The bits which upon truncating does not change the optimized. So after truncating bits in each stage the final bit

948 on December 17,2024 at 11:00:00 UTC from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: Amrita School Of Engineering - Kollam. Downloaded
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

lengths of all the parameters are found to be in the following bits for the first iteration alone whereas with bit optimization
(n,k) representation where n= decimal bits k= fractional bits the bit length of U(t) is 15 bits. The process of bit optimization
All these bit lengths are defined keeping in mind the error saves 19 bits. Now simultaneously equation (5) is implemented
by above process and the obtained result is truncated to (13, 3)
bits.
TABLE IV
PARAMETERS AND THEIR OPTIMISED BITLENGTH

Parameters decimal bits(n) fractional bits(k) total bits

a 2 13 15
b 2 9 11
c 13 3 16
d 5 10 15
V 13 3 16
U 5 10 15
Tau 2 4 6
Percentage of each stage less than 1%. Fixed point
representation is used where the MSB is the signed bit. By
Euler‘s method the differential equations 1 and 2 are modified
as 5 and 6.For the 1st iteration the values of V and U are
constant. The above equations are implemented in Verilog for
which equation (6) is used and in that (b*V) is implemented
using multiplier block. After finding the individual bit lengths
of each parameter from the above table the output of the
multiplier block. After finding the individual bit lengths of
each parameter from the above table the output of the
multiplier block is truncated to (7, 6) bits. From the output
obtained, U (i) is subtracted from multiplier block. The
obtained result istruncated to (7, 7) bits. The output is

Parameters Inputs to Matlab Inputs to Verilog

Fig. 6: Block Diagram
a 0.02 00.0000010100011
TABLE V
b 0.2 00.01000000000000
VERILOG AND MATLAB INPUTS

c -65 1000001000001.000

d 7 00110.0000000000 V (i) = c (9)

V -70 1000001000110.000 U (i) = U (i) + d (10)

U -14 11110.0000000000

Tau 0.7 00.101100000000

The present value should be given as a feedback to second
V (i+1) = V (i) + (tau (0.04V (i) 2+5V (i) +140 iteration. The D-flipflop is used to store the value and send the
feedback. The process is continued for the provided time span.
−U (i)+I (i))) (5)
Once if V (i + 1) ≥ 30mV, then for next iteration, and the
U (i +1) = U (i) + (tau (a (b*V (i) − U (i))))(6) process continues.

The obtained output values in Verilog are with an error of 5%

IfV (i +1) ≥ 30mV then for next iteration
with mat lab results. The error is due to the bit optimization
which is acceptable. Since fixed point representation is used the
V (i) = c (7)
obtained output will contain both decimal part and also
U (i) = U (i) + d (8) fractional part. So, the Normalized output values are plotted in
Verilog.
IV. RESULTS
multiplied with parameter ‘a‘ and truncated to (2, 12) bits. This
value is multiplied with ‘tau‘ and the output is (2, 13) bits. This The Izhikevichmodel for 20 neuro computational properties
output is added with U (i) and truncated to (5, 10) bits. With are implemented in both MATLAB and Verilog. The
this, U (i+1) is implemented and the output is truncated to (5, comparison to Phasic Spiking, a neuro computational property,
10) bits. Without bit optimization the variable‗U(t)‘ takes 34 is explained below.

949 on December 17,2024 at 11:00:00 UTC from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: Amrita School Of Engineering - Kollam. Downloaded
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

The Top module is synthesized using Xilinx ISE for a Virtex5

FPGA and the corresponding target device configuration is
xc5vlx110t-1ff1136.

Fig. 7. Matlab plot for Phasic spiking

TABLE VI
RESOURCES USED BY VIRTEX 5 FPGA

Slice logic used available utilization

utilization percent Fig. 9: Top Level Module Diagram
number 31 69120 1
of slice
Fig.9 is the module level diagram obtained from Xilinx ISE
registers
by synthesizing the Verilog modules. In that figure the first
number of 31 - - module (u_top) is the implementation of (6) and second
flip-flops module (v_out) is the implementation of (5). In that figure the
number of 771 69120 1 output of u_top is given as input to second module and the
slice LUT’s output of v_out is given as input to first module.
number 768 69120 1
used as The Synthesis table along with the power
logic
analysis is shown in TABLE VI.
Total Dynamic Quiescent=1.042 Total=1.043
Power(W) =0.001 V. CONCLUSION
The purpose of this work is to model 20 neuro-
computational properties developed by Izhikevich, which
mathematically supports the properties and resembles the
biological neuron. These neuro-computational properties are
simulated in MATLAB. These are then digitally modelled
using Verilog Hardware Description Language (HDL) and
simulated in ModelSIM RTL simulator. The major part of this
work deals with allocation of bit width for each parameter of
each property in the model and optimizing the bit length and
finally implementing the feedback loop. The model is then
implemented in Xilinx Virtex5 FPGA for area and power
analysis and checked for the functionality. The results shown
above are the action potentials (spikes) of a single neuron
which is basic block of a neuron network. Generally neuron
networks are represented as a system of neurons interconnected
with each other to exchange information. Knowing the
functionality of a single neuron the work can further be
extended to build neuron networks [16] [17] which are
extensively used in neuroscience for replicating the central
nervous system.
REFERENCES

[1] H. Paugam-Moisy and S. Bohte, ―Computing with spiking neuron

Fig. 8. Verilog simulation for phasic spiking networks,‖ in Handbook of Natural Computing. 1st Edition,
G.Rozenberg, T.Back, andJ.N.Kok, Eds.Heidelberg, Germany: Springer-
Verlag, 2010, vol. 1, pp. 1-47.
[2] S.Ghosh-Dastidar and H. Adeli, ―Spiking neural networks,‖ International
Journal of Neural Systems, vol. 19, no. 04, pp. 295-308, 2009.

950 on December 17,2024 at 11:00:00 UTC from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: Amrita School Of Engineering - Kollam. Downloaded
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

[3] W. Maass, ―Networks of spiking neurons: the third generation of neural

network models,‖ IEEE Trans. Neural Networks, vol. 10, no. 9, pp.
16591671, 1997.
[4] E. R. Kandel, J. H. Schwartz, and T. M. Jessel, Principles of Neural
Science. 4th Ed. New York, NY: McGrail-Hill Health Prof. Division,
2000.
[5] W. Gerstner and W. M. Kistler, Spiking Neuron Models: Single
Neurons, Populations, Plasticity. Cambridge University Press, 2002.
[6] H. Soleimani, A. Ahmadi, and M. Bavandpour,‖Biologically inspired
spiking neurons: Piecewise linear models and digital implementation,‖
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2991-3004,
2012
[7] E. M. Izhikevich, ―Simple model of spiking neurons,‖ IEEE Trans.
Neural Networks, vol. 14, pp. 15691572, Nov. 2003.
[8] E. M. Izhikevich, Dynamical Systems in Neuroscience: The Geometry of
Excitability and Bursting, 2007.
[9] B. W. Connors and M. J. Gutnick, ―Intrinsic firing patterns of diverse
neocortical neurons,‖ Trends in Neurosci, vol. 13, pp. 99-104, 1990.
[10] C. M. Gray and D. A. McCormick, ―Chattering cells: Superficial
pyramidal neurons contributing to the generation of synchronous
oscillations in the visual cortex,‖ Science, vol. 274, no. 5284, pp. 109-
113, 1996.
[11] A. L. Hodgkin, ―The local electric changes associated with repetitive
action in a nonmedulated axon,‖ J. Physiol., vol. 107, pp. 165-181, 1948.
[12] E. M. Izhikevich, ―Neural excitability, spiking, and bursting,‖ Int. J.
Bifurc. Chaos, vol. 10, pp. 11711266, 2000.
[13] J. Rinzel and G. B. Ermentrout, ―Analysis of neural excitability and
oscillations,‖ in Methods in Neuronal Modelling, C. Koch and I. Segev,
Eds. Cambridge, MA: MIT Press, 1989.
[14] E. M. Izhikevich, N. S. Desai, E. C. Walcott, and F. C. Hoppensteadt,
―Bursts as a unit of neural information: Selective communication via
resonance,‖ Trends Neurosci., vol. 26, pp. 161-167, 2003.
[15] Michael parker, Digital Signal Processing– Everything you need to know
to get started,2010
[16] .A.Savran and S.Ünsal, ―Hardware implementation of a feed forward
neural network using FPGAs‘,‖ Ege, Department of Electrical and
Electronics Engineering, 2003.
[17] EsraaZeki Mohammed and Haitham Kareem Ali, ―Hardware
Implementation of Artificial Neural Network Using Field Programmable
Gate Array‖ International Journal of Computer Theory and Engineering,
Vol. 5, No. 5, October 2013.

951 on December 17,2024 at 11:00:00 UTC from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: Amrita School Of Engineering - Kollam. Downloaded