Unit 2 - CPU Organization

Introduction – General Register Organization – Stack Organization –

Instruction Formats – Addressing Modes –Program Control –RISC -
CISC

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Three types of CPU Organization

1. Single Accumulator CPU Organization

2. General Registers CPU Organization
3. Stack CPU Organization

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Single Accumulator Organization

Computers having a single-

processor register i.e. accumulator
AC , where any ALU operation is
performed with the memory
operand and the content of AC. The
result is destined to AC.

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General Registers Organization

Bus organization for seven CPU

registers is shown in Fig. The
output of each register is
connected to two multiplexers
(MUX) to form the two buses A
and B . The A and B buses form
the inputs to arithmetic logic
unit (ALU).

The operation selected in the

ALU determines the arithmetic
or logic operation that is to be
performed. The result of the
operation is available for
output data and also can be
stored into the registers.

GeneralCORegisters
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 General Registers Organization

For example, to perform the operation : R1 <--R2 - R3

the control must provide binary selection variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A .
2 . MUX B selector (SELB): to place the content o f R3 into bus B .
3 . ALU operation selector (OPR): to provide the arithmetic SUB for A - B .
4. Decoder destination selector (SELD): to transfer the content o f the
output bus into R1

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Stack Organization
A stack can be organized as a collection
of a finite number of registers or memory
words. Figure shows the organization of a
64-word stack. The stack pointer register
SP consists of address of top of the stack
(TOS).

To insert a new item, the stack is pushed

by incrementing SP and writing a word in
the next-higher location in the stack.
Three items are pushed in to the stack: A,
B, and C, in that order. Item C is on top of
the stack so that the content of SP is now
address 3.

To remove the top item, the stack is

popped by reading the memory word at
address 3 and decrementing the content
of SP . Item B is now on top of the stack
since SP holds address 2. .

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Register Stack Organization

Push operation is implemented with the following sequence of microoperations;

SP  SP + 1 Increment stack pointer

M [SP]  DR Write item on top of the stack

Pop operation is implemented with the following sequence of microoperations;

DR  M [SP] Read item from top of the stack

SP  SP – 1 Decrement stack pointer

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The Polish mathematician Lukasiewicz showed that arithmetic expressions can be
represented in prefix notation, often referred to as Polish notation, which places
the operator before the operands. The postfix notation, referred to as reverse
Polish notation (RPN), places the operator after the operands. The following
examples demonstrate the three representations:

A+B Infix Notation

+ AB Prefix or Polish Notation
AB + Postfix or Reverse Polish Notation

The reverse Polish notation is in a form suitable for stack manipulation in Stack
organization.
The expression
(A * B) + (C * D)
is written in reverse Polish notation as
AB * CD * +

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Instruction Format

The most common fields found in instruction formats are:

1. An operation code field that specifies the operation to be performed

2. An operand address field that designates a memory address or register

where the operand is available

3. A mode field that specifies the way the operand or the effective address
is determined.

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The number of address fields in the instruction format of a computer
depends on the internal organization of its registers inside the CPU. Most
computers fall into one of three types of CPU organizations:

1. Single accumulator organization

2. General register organization
3. Stack organization

The four types of Instruction formats pertaining to the three different

types of CPU organizations are listed as :

1. One address instruction format for Single accumulator organization

2. Two address instruction format for General register organization
3. Three address instruction format for General register organization
4. Zero address instruction format for Stack organization

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One Address Instruction (Single Accumulator Organization) :
ADD X
where X is the address of the operand. The ADD instruction in this case results in
the operation AC  AC + M [X]. AC is the accumulator register and M [X]
symbolizes the memory word located at address X.

Two / Three Address instruction (General Register Organization) :

ADD R1 , R2 , R3
denotes the operation R1  R2 + R3 . The number of address fields in the
instruction can be reduced from three to two if the destination register is the same
as one of the source registers.
ADD R2 , R3
Thus the instruction would denote the operation R2  R2 + R3

Zero Address Instruction (Stack Organization) :

ADD
This operation has the effect of popping the two top most numbers from the stack,
adding the numbers, and pushing the sum into the stack. There is no need to
specify operands with an address field since all operands are implied to be in the
stack.

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Evaluation of expression X = (A + B) * (C + D) using different address instructions

Three address instruction Two address instruction

One address instruction Zero address instruction

Postfix notation : A B + C D + *

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Addressing Mode
It specifies the way the operands are to be accessed. The Addressing mode
offers the following advantages

1. It gives programming versatility to the user by providing facilities like

pointers to memory, counters for loop control, indexing of data, and
program relocation.

2. It reduces the number of bits in the addressing field of the instruction.

The effective address is defined to be the address of operand obtained

from the computation specified by the given addressing mode.

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Implied Mode: In this mode the operands are specified implicitly in the
instruction. For example, the instruction "complement accumulator“ is an
implied-mode instruction because the operand in the accumulator register is
implied in the definition of the instruction.

Immediate Mode: In this mode the operand is specified in the instruction itself.
In other words, an immediate-mode instruction has an operand field rather than
an address of operand.

Direct Address Mode: In this mode the effective address of operand is specified
in the address part of the instruction.

Indirect Address Mode: In this mode the address field contains address of
address of the operand.

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Register Direct Mode: In this mode the operands are in registers that reside
within the CPU.

Register Indirect Mode: In this mode the instruction specifies a register in the
CPU whose contents give the address of the operand in memory. In other
words, the selected register contains the address of the operand rather than
the operand itself.

Auto-increment Mode: This is similar to the register indirect mode except

that the register is incremented after or before its value is used to access
memory.

Auto-decrement Mode: This is another kind of register indirect mode where

the register is decremented after 0r before its value is used to access the
memory

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A few addressing modes require that the address field of the instruction be
added to the content of a specific register in the CPU. The CPU register
used in the computation may be the program counter, an index register, or
a base register. The effective address in these modes is obtained from the
following computation:
Effective address = Address part of instruction + Content of CPU register

Relative Address Mode: In this mode the content of the program counter is
added to the address part of the instruction in order to obtain the effective
address.

Indexed Addressing Mode: In this mode the content of an index register is

added to the address part of the instruction to obtain the effective address.

Base Addressing Mode: In this mode the content of a base register is

added to the address part of the instruction to obtain the effective address.
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Mem -Addr Effective Acc Reg
Mode Address content
Direct 500 800
Immediate ___ 500
800 300
Indexed 600 900
Relative 701 325
Register ___ 400
Reg-Indirect 400 700
Auto Inc 401 750
Auto Dec 399 450

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PROGRAM CONTROL
Program control instruction, when executed, may change the
address value in the program counter and cause the flow of
execution control to be altered.

In other words, program control instructions specify conditions for

altering the content of the program counter and this altered PC
value causes a break in the sequence flow of instruction execution.

This is an important feature in digital computers, as it provides

capability for branching to different program segments.

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PROGRAM CONTROL - PSW (Program Status Word)
ALU circuit in the CPU is supplemented with a status register
where status bits can be stored for further analysis. Status bits are
also called condition-code bits or flag bits.

The four status bits are symbolized by C. S, Z, and V. The bits are
set or cleared as a result of an operation performed in the ALU.

1. Carry bit is set if end carry becomes 1 after Addition.

2. Sign bit is set if the MSB bit becomes 1 after Arithmetic
operation
3. Zero bit is set if the result of arithmetic logic operation is all
zeros
4. Overflow bit is set if the last two carry bits become 1 after
divide and multiply arithmetic operations
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PROGRAM CONTROL (Conditional & Unconditional Branching)

Branch (jump) instructions may be either conditional or

unconditional.

An unconditional branch instruction causes a branch to the

specified address without any conditions.

The conditional branch instruction specifies a condition such as

branch if positive or branch if zero.

If the condition is met, the program counter is loaded with the

branch address. If the condition is not met, the program counter is
not changed and the next instruction is executed in sequence.

E.g. Branch if Zero (BZ & BNZ)

Branch if carry (BC & BNC)
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PROGRAM CONTROL – Subroutine Call and Return
A Subroutine call instruction consists of an operation code
together with an address that specifies the beginning address of
the subroutine. The instruction is executed by performing two
operations:
(1) The address of the next instruction available in the program
counter (the return address) is stored in a temporary location so
the subroutine knows where to return, and (2) control is transferred
to the beginning of the subroutine
SP <- SP - 1
M [SP] <-PC
PC <- subroutine effective address

The last instruction of every subroutine, commonly called

return instruction, transfers the return address from the temporary
location into the program counter.
PC <-M [SP]
SP <- SP + 1
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PROGRAM CONTROL – Interrupts
Program interrupt refers to the transfer of program control from a currently
running program to another service program as a result of an external or internal
generated request. Control returns to the original program after the service
program is executed. The last instruction in the service program is a return
instruction from interrupt service routine (ISR).

1. External interrupts – IO devices

2. Internal interrupts – CPU services
3. Software interrupts - Program Reset

SP <- SP - 1
M [SP] <-PC
PC <- Interrupt vector address

The last instruction of every ISR, commonly called return instruction, transfers
the return address from the temporary location into the program counter.

PC <-M [SP]
SP <- SP + 1
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RISC Vs CISC
Computers with large number of instructions as well as
complex instruction formats is classified as a complex
instruction set computer, abbreviated CISC.

CISC instructions can get executed relatively slower since

they tend to access memory often

Computers with fewer instructions as well as simple

instruction formats is classified as a reduced instruction
set computer or RISC.

RISC instructions can be executed much faster within the

CPU without having to access memory as often.
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CISC Characteristics

1. A large number of instructions-typically from 100 to 250

instructions

2. Some instructions perform specialized tasks and are used

infrequently

3. A large variety of addressing modes-typically from 5 to 20

different modes

4. Variable-length instruction formats

5. Instructions that manipulate operands in memory

6. Microprogrammed control
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RISC Characteristics

1. Relatively few instructions

2. Relatively few addressing modes

3. Memory access limited to load and store instructions

4. All operations done within the registers of the CPU

5. Fixed-length, easily decoded instruction format

6. Single-cycle instruction execution

7. Hardwired control

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