Implementing constant 0s and 1s

The PLA can be programmed to give an output of constant 0 or 1. Figure 20.1.

All the four inputs and their complements are shown connected to the first AND gate.
The product term generated by the AND gate is 0. P1 = 0 . The P1 product term is
connected to the input of first OR gate. Thus the output of OR gate is 0. The inputs to the
second AND gate are disconnected, thus the product term generated by the AND gate is a
1. P2 = 1 . The P2 term is connected to the input of the second OR gate, therefore the
output of the second OR gate is a 1. No product term is connected to the input of the third
OR gate, therefore the output of the third OR gate is 0.

Figure 20.1 4 x 3 PLA Device programmed for 0, 1 and 0 output

Implementing Odd-Prime Number Function

The Odd-Prime Number generator can be implemented by programming the 4 x 3
PLA. Due to the limitations of the PLA which only has six product term (six AND gates),
only the first six Odd-Prime numbers 1, 3, 5, 7, 11 and 13 can be detected. Additional
two outputs are programmed to detect Odd-Prime multiples of 15 and 39 respectively.
The six product terms represented by P1, P2, P3, P4, P5 and P6 are minterms 1, 3, 5, 7,

Digital Logic Design: Combinational Logic with PLDs Page 1 of 10

11 and 13. The first OR gate sums the six minterms (product terms) to give an output of 1
when any one of the first six Odd-Prime numbers is applied at the inputs I1, I2, I3 and I4
of the PLA respectively. The second OR gate sums the minterms 1, 3 and 5. Thus the
output of the second OR gate is a 1 when any of the three minterms is applied at the PLA
inputs. Similarly, the third OR gate sums the minterms 1, 3 and 13 and the output is set to
logic 1 when any one of the three inputs are detected at the input of the PLA. Figure 20.2.

Figure 20.2 4 x 3 PLA Device programmed to Detect Odd-Prime Numbers

Digital Logic Design: Combinational Logic with PLDs Page 2 of 10

GAL Operation
The GAL has a reprogrammable AND gate array and a fixed OR array. GAL can
be reprogrammed as instead of fuses E2CMOS logic is used which can be programmed to
connect a column with a row. The E2CMOS logic at each column–row intersection is
known as a cell. Figure 20.3. The E2CMOS cell in the ‘on’ state connects the column
with the row and a cell in the ‘off’ state disconnects the column and row. Appropriate
cells are programmed to the ‘on’ state to allow appropriate literals to be connected to the
AND gates which generate product terms. The simplified GAL structure shows the
implementation of an SOP function. Figure 20.4

A A B B

E2CMOS E2CMOS E2CMOS E2CMOS

E2CMOS E2CMOS E2CMOS E2CMOS

E2CMOS E2CMOS E2CMOS E2CMOS

E2CMOS E2CMOS E2CMOS E2CMOS

E2CMOS E2CMOS E2CMOS E2CMOS

E2CMOS E2CMOS E2CMOS E2CMOS

Figure 20.3 Simplified E2CMOS array structure of GAL

A typical Gal has eight or more inputs to the reprogrammable AND array and 8 or
more input/outputs from its ‘Output Logic Macro Cells’ OLMCs. The OLMCs can be
programmed to Combinational Logic or Registered Logic. Combinational Logic is used
for combinational circuits, where as Registered Logic is based on Sequential circuits.
Figure 20.5

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 A A B B

ON OFF OFF OFF

OFF OFF OFF ON

OFF ON OFF OFF

OFF OFF ON OFF

AB + AB + AB
ON OFF OFF OFF

OFF OFF ON OFF

Figure 20.4 GAL implementation of an SOP function

Input 1
OLMC Input/
Output 1
Input 2 E2CMOS
Programmable Input/
AND array OLMC
Output 2

Input/
Input n OLMC
Output m

Figure 20.5 Block diagram of a GAL

Digital Logic Design: Combinational Logic with PLDs Page 4 of 10

 GALs are also available in a variety of configurations. GALs are identified by a
prefix GAL followed by a 2-digt number indicating the number of inputs which is
followed by V indicating variable output configuration followed by a number which
indicates the number of outputs. Figure 20.6

G A L 16 V 8

Generic array Logic Eight Outputs

Sixteen Inputs Variable output Configuration

Figure 20.6 Standard GAL Numbering

Programming of PLDs
PLDs are programmed with the help of computer which runs the programming
software. The computer is connected to a programmer socket in which the PLD is
inserted for programming. PLDs can also be programmed when they are installed on a
circuit board.

The programming of a PLD device involves entering the logic function in the
form of a Boolean equation, truth table or a state diagram. Any errors during the entry
process are corrected. The software compiler processes the information in the input file
and translates it into a suitable format. The complier also minimizes the logic. The
minimized logic is then tested by using a set of hypothetical inputs known as test vectors.
The testing verifies the design of the logic circuit before committing it to the PLD. If any
flaws are detected during the testing process the design must be debugged and submitted
for recompilation. Once the design has been finalized a documentation file is produced
along with a fuse map file which is downloaded to the programmer which programs the
PLD device inserted in the programmer socket.

PLDs have In-System Programming (ISP) capability that allows the PLDs to be
programmed after they have been installed on a circuit board. A standard 4-wire interface
is used for programming the In-System PLD. ISP capability allows systems to be
upgraded by reprogramming the PLD.

The GAL22V10
The GAL22V10 is a popular GAL device having twelve inputs and ten
inputs/outputs. The device is available as low-voltage 3.3v version. It is also available as
an ISP version. The device has ten OLMCs that can be programmed to different output
modes. The ten OLMCs receive different number of inputs from the programmable AND
gate array. Figure 20.7. Of the ten OLMCs, two have eight inputs, two have ten inputs,
two have twelve inputs, two have fourteen and two have sixteen inputs. Each OLMC can
be programmed for active-high, active-low output or it can be programmed as an input.

Digital Logic Design: Combinational Logic with PLDs Page 5 of 10

 Figure 20.7 Block diagram of the GAL22V10

The circuit diagram of an OLMC is shown in figure 20.8. The OLMC consists of
a flip-flop which is a sequential logic device which stores the information at the output of
the OR gate. Flip-flops will be discussed latter. The output and the complemented output
of the flip-flop are connected to the two inputs of the 4-to-1 MUX. The remaining two
inputs of the MUX are connected to the OR gate output and its complemented output.
The output of the MUX is connected to the output through a tri-state buffer. The output is
also connected to the input of a 2-to-1 MUX. The other input of the 2-to-1 MUX is

Digital Logic Design: Combinational Logic with PLDs Page 6 of 10

connected to the complemented output of the flip-flop. The output of the 2-to-1 MUX
and its complemented output is connected to the input of the AND array. The select
inputs S0 and S1 select the appropriate 4-to-1 MUX input to be routed to the output or the
input. The S1 select input of the 2-to-1 MUX is used to route the appropriate input to the
input of the AND array. The select bits S0 and S1 are programmed in a dedicated group of
cells in the array which are separate from the logic array cells.

Figure 20.8 Circuit Diagram of OLMC

The four OLMC configurations are

• Combination Mode with active-low output
• Combinational Mode with active-high output
• Registered Mode with active-low output
• Registered Mode with active-high output

OLMC Combinational Mode

When the select inputs S0 and S1 are set to 0 and 1 respectively, the 4-to-1 MUX
selects the OR gate output and the output is active-low because of the inversion by the tri-
state buffer. When the select inputs are set to 1 and 1 respectively, the MUX selects the
complement of the OR gate output. The output of the OLMC is active-high due to double
inversion.

Tri-State Buffers
Tri-State Buffer is a NOT gate with a control line that disconnects the output from
the input. When the control line is high the buffer operates like a NOT gate and when the
control line is low the output is disconnected from the output and high impedance is seen
at the output. Tri-state buffers are used to disconnect the outputs of devices which are
connected or share a common output line. Figure 20.9

Digital Logic Design: Combinational Logic with PLDs Page 7 of 10

 Figure 20.9a Tri-State Buffer

Figure 20.9b Tri-State Buffer operating as a NOT gate

Figure 20.9c Tri-State Buffer in High-Impedence State

Referring to the OLMC logic circuit. Figure 20.8. When the control input to the
tri-state buffer is set to low, the output of the buffer is set to high impedance
disconnecting the OLMC from the output pin. The output pin is used as an input pin.

The GAL22V10 Array

The GAL22V10 has 22 inputs organized as 44 lines, one for each input and its
complement. Each AND gate has 44 inputs connected to the 44 input lines. Detailed
connection of the first OLMC to the AND array is shown in figure 20.10. The vertical
lines in groups of four represent the inputs. Thus the first group of four vertical lines
represents the input from the GAL input pin and the input from the OLMC. The
horizontal lines represent the product terms. The first OLMC has ten input product terms.
Out of the ten product terms, eight product terms are connected to the OR gate in the first
OLMC. Out of the remaining two product terms, the first product term is used to control
the tri-state buffer and the other is used for reset in the Registered mode for all OLMCs.

Digital Logic Design: Combinational Logic with PLDs Page 8 of 10

 Each OLMC ORs the product term to give a single sum of product term. The
GAL has ten such OLMCs therefore a total of ten Sum-of-Product terms can be
implemented.
Input Lines

Reset to all OLMCs

44

44

44

44

44

44
Input/Output
OLMC
44
Product Term Lines

44

44

44

Input

Figure 20.10 Detailed Connection to the first OLMC of GAL22V10

Programming the GAL22V10

Figure 20.11 shown the programmed GAL for the Boolean expression
X = ABCDEF + ABCDEF + ABCDEF + ABCDEF + ABCDEF + ABCDEF + ABCDEF

In the figure 20.11 the GAL has been programmed for a six variable Boolean
function. The six variables are connected at the six inputs of the GA device. The figure
shows the connection detail for the first variable A. The first group of four vertical lines
represents the variable A and its complement A . The remaining two lines in the group are
not used receive the un-complemented and complemented output from the OLMC.
Similarly, the second group of four vertical lines are connected to the second input pin of
the GAL which is connected to a signal representing variable B. The next four sets of
four vertical lines represent input pins 3, 4, 5 and 6 which are connected to variables C,
D, E and F. The Boolean expression that is implemented has seven product terms. The
first OLMC has eight input product terms, thus it can be used to program the Boolean
expression. The output of the first AND gate generates the first product term of the
Boolean expression. Similarly, the 2nd to 7th AND gates generate the remaining six
product terms respectively. The eight input OR gate (not shown) in the OLMC block
generates the sum of product terms. The last group of vertical lines is used to control the
tri-state buffer connected at the output of the OLMC. The diagram shows that it has been
set to high to allow the tri-state buffer connect the OLMC output to the output pin of the
GAL.

Digital Logic Design: Combinational Logic with PLDs Page 9 of 10

 Input Lines

Reset to all OLMCs

44
x
44
x x x x x x
44
x x x x x x
44
x x x x x x
44
x x x x x x
44
x x x x x x OLMC
Input/Output

44 Product Term Lines

x x x x x x
44
x x x x x x
44

44

Input

Figure 20.11 GAL22V10 programmed for Boolean Function

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