IPC-7093

Design and Assembly Process Implementation

for Bottom
Termination Components
March 2010
A standard developed by IPC

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 IPC-7093
Design and Assembly Process
Implementation for Bottom Termination
SMT Components

Developed by the IPC Bottom Termination Components (BTC) Task

Group (5-21h) of the Assembly & Joining Processes Committee (5-20)
of IPC

Use of this publication are encouraged to participate in

development of future revisions.

Contact:

IPC
3000 Lakeside Drive, Suite 309S
Bannockburn, Illinois
600015-1249
Tel 847 625.7100
Fax 847 615.7105

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Acknowledgement

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 Design and Assembly Process Implementation for Bottom
Termination Components

1 SCOPE IPC-SM-785 Guidelines for Accelerated Reliability

This document describes the design and assembly Testing of Surface Mount Solder Attachments
challenges for implementing Bottom Termination IPC-1756 Manufacturing Process Data Management
surface mount Components (BTCs) whose external
connections consist of metallized terminations that IPC-2226 Sectional Design Standard for High Density
are an integral part of the component body. Throughout Interconnect (HDI) Printed Boards
this document the word “BTC” can mean all
types and forms of bottom only termination components IPC-4101 Specification for Base Materials for Rigid and
intended for surface-mounting. This includes Multilayer Printed Boards
such industry descriptive nomenclature as QFN, DFN,
SON, LGA, MLP, and MLF, which utilize surface IPC-4761 Design Guide for Protection of Printed Board
to surface interconnections. The focus of the information Via Structures
contained herein is on critical design,
assembly, inspection, repair, and reliability issues IPC-6012 Qualification and Performance Specification
associated with BTCs. for Rigid Printed Boards

1.1 Purpose IPC-7351 Generic Requirements for Surface Mount

The target audiences for this document are managers, Design and Land Pattern Standard
design and process engineers, and operators
and technicians who deal with the electronic design, IPC-7525 Guidelines for Stencil Design
assembly, inspection, and repair processes. The
intent is to provide useful and practical information to IPC-7526 Stencil and Misprinted Board Cleaning
those companies who are using or considering Handbook
tin/lead, lead-free, adhesives or other forms of
interconnection processes for assembly of BTC type IPC-9201 Surface Insulation Resistance Handbook
components.
IPC-9701 Performance Test Methods and Qualification
1.2 Intent Requirements for Surface Mount Solder
This document, although not a complete recipe, Attachments
identifies many of the characteristics that influence the
successful implementation of robust and reliable J-STD-001 Requirements for Soldered Electrical and
assembly processes and provides guidance Electronic Assembly
information to component suppliers regarding the issues
being faced in the assembly process. The J-STD-002 Solderability Tests for Component Leads,
exchange of information between the component Terminations, Lugs, Terminals and Wires
supplier, product designer, and assembly personnel
about those parameters that influence good assembly J-STD-005 Requirements for Soldering Pastes
practices are more critical with BTC
implementation than with many other surface mount J-STD-020 Moisture/Reflow Sensitivity Classification for
parts. Nonhermetic Solid State Surface Mount Devices

2 APPLICABLE DOCUMENTS J-STD-033 Handling, Packing, Shipping and Use of

Moisture/Reflow Sensitive Surface Mount Devices
2.1 IPC
IPC-T-50 Terms and Definitions for Interconnecting and
Packaging Electronic Circuits

IPC-CH-65 Guidelines for Cleaning of Printed Boards

and Assemblies

IPC-D-279 Design Guidelines for Reliable Surface

Mount Technology Printed Board Assemblies

IPC-A-610 Requirements for Soldered Electrical and

Electronic Assemblies

8
2.2 JEDEC2 as lands for testing or vias that are associated with
the mounting of a single component.
JEDEC Publication 95, JEDEC Design Standard,
Design Requirements for Outlines of Solid State and
3.1.3 conductive pattern*
Related Products Design Guide: 4.8, Plastic Quad and The configuration or design of the conductive
Dual Inline Square and Rectangular No Lead material on a base material. (This includes traces,
Packages (With Optional Thermal Enhancements) lands, vias, planes, and passive components when
(QFN/SON) Date: September 2006, Issue: C these are an integral part of the printed board
JEDEC Publication 95, JEDEC Design Standard, manufacturing process.)
Design Requirements for Outlines of Solid State and
Related Products Design Guide: 4.19, Quad No-Lead 3.1.4 land pattern*
Staggered and Inline Multi-Row Packages (With A combination of lands that is used for the mounting,
Optional Thermal Enhancements) (QFN) Date: May interconnection and testing of a particular component.
2007, Issue: D 3.1.5 mixed component-mounting technology*
JEDEC Publication 95, JEDEC Design Standard, A component mounting technology that uses both
Design Requirements for Outlines of Solid State and through-hole and surface-mounting technologies on the
Related Products Design Guide: 4.20, Small Scale same packaging and interconnecting structure.
Plastic Quad and Dual InLine Square and Rectangular 3.1.6 printed board assembly
No-Lead Packages (With Optional Thermal The generic term for an assembly that uses a printed
Enhancements) (QFN/SON) Date: September 2009, board for component mounting and interconnecting
Issue: D.01 purposes.
JEDEC Publication 95, JEDEC Design Standard,
Design Requirements For Outlines of Solid State and 3.1.7 surface mount technology (SMT)*
Related Products Design Guide: 4.23, The electrical connection of components to the surface
Punch-Singulated Fine Pitch Square Very Thin and of a conductive pattern that does not utilize component
Very-Very Thin Profile, Leadframe-Based Quad holes.
No-Lead Staggered Dual-Row Packages (with Optional
Thermal Enhancements) Date: November 2005 3.2 BTC Executive Summary
The term BTC represents industry descriptive package
3 SELECTION CRITERIA AND MANAGING names such as DFN (Dual Flat No-lead), QFN (Quad
Flat No-Lead package), LGA (Land Grid Array), SON
BTC IMPLEMENTATION (Small Outline No-Lead – leads on two sides), PQFN
This section provides a high level overview of the (Plastic Quad Flat No-Lead), MLFP (Micro Leadframe
entire document. It is the executive summary of the Plastic), and MLP (Micro Leadframe Package) etc. They
usage and implementation of BTC parts in the are in some ways similar to BGAs which also have
electronic assembly. For technical details on BTC hidden terminations, but they are also very different.
They do not have spheres but rather metallized
design, assembly and reliability issues, refer to the terminations or pads underneath the package.
sections related to those topics.
When implementing BTCs into an electronic assembly,
3.1 Terms and Definitions one must keep in mind that these parts are not the only
Terms and definitions used herein are in accordance with components that must be mounted on the
IPC-T-50 except as otherwise specified. Any definition interconnection product board. The board will have
denoted with an asterisk (*) is a reprint of the term defined other packages such as BGAs, fine pitch and even
in IPC-T-50. some through-hole components, and those components
may have their own unique design and assembly
3.1.1 bottom termination components (BTC) implementation requirements.
Surface mountable electronic components whose external
connections consist of metallized There are two key issues in BTCs: providing the
terminations that are an integral part of the component appropriate amount of solder paste and ensuring solder
body. The terminology BTC includes such industry joint reliability. This entire document is essentially
descriptive nomenclature as QFN, DFN, SON, LGA, MLP, dealing with these two issues in various design and
and MLF, which utilize surface to surface assembly sections. Other variables such as surface
interconnections. finish, stencil selection, thermal profile are also
discussed and may not be different because of BTCs.
3.1.2 component mounting site Since there is no protruding lead on the package,
reliability of the solder joint is essentially controlled by
The location on a printed board or mounting
solder joint area and height. Lower paste volume can
structure that consists of a land pattern and reduce floating and voids but increases the risk of
conductor fanout to additional circuit features such solder opens so a balance is required to ensure overall
solder joint reliability.
9
Most,but not all, BTC packages have an exposed Die Because there are no protruding leads, BTCs have
Attach Pad (DAP) feature on the package bottom proved to exhibit minimal parasitic losses due to their
to provide a thermal interface with the mating circuit very low electrical resistance and capacitance,.and heat
board surface. When it comes to inspection, they transfer from the package to the PCBs is excellent due
pose even more challenge than Ball Grid Arrays (BGAs) to their large thermal pad in direct contact with PCB.
which allow inspection by endoscopes. One may not be
able to see side solder fillets and even when they are In order to ensure a robust package-to-PCB interface,
seen on BTCs with cut metal leadframes, they may look solder paste deposition must be tightly controlled.
non-wetted or dewetted. If plating is on the side metal, Excessive or unevenly deposited solder paste volume
dewetted and nonwetted side fillets on BTCs may may cause the package to float, resulting in poor land
indicate solder bonding problems. pattern alignment, random solder bridging, voiding and
Examples of BTC components covered in this section opens.
are shown in Figures 3.1 to 3. 4.
Too little solder volume may compromise product
a) General types: Discrete components (diodes, reliability. Even minimal warping in the package or
transistors, inductors etc. – some DFNs as shown in PCB can result in solder joint opens. Because the
Figure 3-1 terminal features may not protrude beyond the package
b) Quad Flat No Lead (QFN): Component part with I/O body, visual inspection and uncompromised verification
(input/output) on four sides as shown in Figure 3-2 of the solder interface will be difficult.
c) Small Outline No Lead (SON): Component part with 3.3 Description of Different Component Structures
I/O on two sides (includes some DFNs) as shown in Surface mount components with bottom only
Figure 3-3. terminations are becoming more and more prevalent
d) Land Grid Array (LGA): Component part with I/O in and there are many types of bottom only termination
rows and columns [structured or random] as shown components that go by various names. Unlike the more
in Figure 3-4. traditional leadframe packaged semiconductors with
The basic driver for BTCs is the cost. It is a package protruding leads, the BTC devices are furnished with flat
with the lowest per pin cost, as low as half a cent per pads or terminations on the bottom of the package.
pin. To put this in a proper perspective, if a package Those terminations are provided on only two sides or on
costs less than one cent per pin, it is considered a very all four sides of the package in single or multiple rows.
low cost package. So BTCs become an ideal package The Bottom Termination Component task group has
especially in high volume applications such as cell decided to use a common name for all these package
phones or other mobile products types since they require a common approach of design
and assembly. That common name is BTC or Bottom
Although many select BTC packaging for its favorable Termination surface mount Component to represent all
cost factor, the package family has become widely used of these packages in this document.
for semiconductors requiring electrical performance and
improved thermal management. Assembly processing, The BTC packages are leadless, near Chip Scale
however, will require a careful attention to process Package (CSP) size with low profile (1.0 mm and
control from solder material selection, deposition, less), excellent thermal dissipation and good electrical
package placement and solder reflow profile. In regard performance. Typical BTCs have solderable
to the mounting structure, the PCB must exhibit minimal terminations that are flush with the bottom of the device.
warp and the land patterns for BTC attachment must These devices can also have smaller solderable
provide a uniform surface finish. termination areas located along the perimeter sides or
flanks of the package near the bottom of the device.

Figure 3-1 Discrete General Types of Bottom-only Terminations

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 Figure 3-2 Quad Flat No Lead Type Bottom-only Terminations

Figure 3-3 Small Outline No Lead Type Bottom-only Terminations

Figure 3-4 Land Grid Array Type Bottom-only Terminations

One of the primary benefits provided by the BTC

package is a very low profile. This is a key Traditional gull-wing leaded packages have very good
requirement for newer generations of portable, wireless long solder joint reliability life¸ compared to leadless
and hand held electronic products where both components of the same size, since they have very
weight and package thickness must be minimized. This flexible leads. The BTC packages, on the other hand,
trend reduces the semiconductor package are not compliant and may exhibit a relatively shorter
outlines and profile for portable handheld devices. solder joint life when subjected to operation in harsh
environments. This is because they do not have leads
The contact pitch for BTC packages is generally 1.0 mm that can take up stresses and strains introduced by
or less and the packages tend to be smaller in size. The differing coefficients of thermal expansion between the
body outline dimensions can be as small as 2.0 mm x package and the substrate.
2.0 mm or as large as 12.0 mm x 12.0 mm. Due to finer
contact pitch variations this package is able to Many of the BTC packages are furnished with a copper
accommodate a die element that is nearly the same leadframe substrate and offer a thermal enhancement
size as the package by exposing the die attach pad on the bottom of the
package surface. The die-attach pad provides an
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efficient heat path when soldered directly to the board. thickness exposed to the sides of the package. Figure
This enhancement also enables stable ground interface 3-6 shows the differences in these package
by use of down bonds or by electrical connection configurations.
through a conductive die attach material. But such
thermal pads have the potential for large voids and may One of the biggest benefits of the BTC packages is their
even lead to the package floating if solder paste volume thickness. In mobile applications such as cell phone,
is not tightly controlled. palm top and lap top, weight and thickness of the device
becomes even more important. BTC packages allow
The BTC package comes in two formats: punch much thinner devices than possible when using other
singulated and saw singulated. While punch types of surface mount components. Figure 3-7 shows
singulated packages are individually punched from relative package thickness of various component
molded strip during final assembly, the saw packages. The MLF package is much thinner than
singulated package are assembled in array format and traditional SMT packages.
separated into individual components during the
final sawing operation. See Figure 3-5. Both singulation While the lack of traditional leads or balls allows lower
methods can leave the terminal edges without package thickness and better electrical and thermal
a wettable surface finish. performance, the low standoff height makes it difficult to
remove any trapped flux residues that remain in and
The saw singulated package is further divided into two around the solder joints. And if the flux is active, the
options: Full Lead package, and Lead Pullback corrosion potential is increased. Also, it is necessary
package. While full lead package has the whole that the package and PCB be very flat to achieve good
thickness of the lead exposed on the package sides, interconnection; otherwise the potential for opens in
the lead pullback package has a bottom half etch solder joints is increased. And since
leadframe, resulting in only the top half of the lead

Figure 3-5 Typical QFN Cross-section

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 Figure 3-6 Saw Singulated (a, b) BTC Package.

Figure 3-7 MLF package thickness when compared to other types of packages

the standoff height is very low, solder joint reliability may Land pattern design and stencil designs are the key
be a concern in harsher environments. tools to prevent potentials for opens and shorts in
the same package. Since some BTCs require wide
3.4 Total Cost of Ownership Low package cost is a lands for power/ground pins and narrow lands for
key driver for widespread use of BTCs. However, the signals,, it may be necessary to increase the stencil
low package cost may not immediately translate into aperture for signal pins to prevent opens but at the
overall low assembly cost since this package presents same time make the stencil apertures much smaller
many challenges in assembly, inspection, and rework. than the power and ground pads to prevent
squeeze balls and shorts.
In practical reality, the total cost of the final assembly is
often greatly impacted by decisions made early in the Figure 3-8 shows guidelines for land pattern design.
design process. Too often accounting systems track The lands are larger than the lead footprint. The land
“cost in the door” but fail to track “cost out the door”. pattern should extend beyond the package footprint
Purchasing is measured and rewarded by identifying especially underneath the package. The stencil aperture
and procuring at the lowest price, without understanding may have to be the same size as the land pattern.
and fully appreciating the impact on the manufacturing When the spacing becomes very close, solder mask is
process and long term reliability of the product and the used in order to retain the solder in the land pattern
implied cost of failures. Thus it is incumbent on area as shown in Figure 3-8.
management to prudently consider and decide on the
amount of effort to devote to “up front” engineering, Stencil aperture design is not only critical to preventing
including component selection or package design, opens and shorts in BTC package, it is also important to
solder joint design, board design, and design verification. prevent floating of BTC packages, a very common
Management must also understand and appreciate the phenomenon.
true piece part cost which is comprised of several
elements including the cost of components, incoming The reality is that BTC packages will be used with all
inspection, assembly, test, and final inspection. The other types of surface mount components, including
decisions made will directly impact product reliability. BGAs, PQFPs etc. So the selection of solder powder
Table 3-1 below lists the key components of Total Cost size will have to be done based on the lowest pitch
of Ownership. component on the board. That particular package may
or may not be a BTC package.
3.5 Design and Assembly Process Considerations
for QFN Type BTC Packages
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 Table 3-1 Total Cost of Ownership of Bottom Terminated Components (BTC)
Cost Contributor Impact
Incoming inspection The incoming component inspection level is a function of the confidence the buyer has in the
supplier considered in view of the cost of the different potential defects which might be
encountered and how they might be resolved. Rework is an expensive process but product
returns can ruin a business.
Component or package To meet cost and reliability targets, a reasonable rule of thumb is to select or design the
design lowest cost package that meets the lead count requirement and power dissipation with the
largest pitch tolerable within design constraints. Consideration of the potential change to
product specifications to improve product cost and reliability may be desirable under certain
circumstances.
Solder joint quality The solder joint is the most critical factor in product reliability today. Solder volume and
solder placement is critical to yield and reliability of BTC assembly. The die attach pad
(DAP) has been identified as an item that may be of high importance as some data show
that reliability is reduced when it is not soldered in place.
Board design The board materials choice, layout and land pattern design are all vital and directly impacts
board cost, assembly yield and reliability.
Assembly method The assembly process has several steps including solder paste deposition, component
placement, reflow and cleaning. The method chosen can represent a relatively minor % of
overall cost when done with a well controlled process but costly otherwise. In some cases
with BTCs, supplementary process equipment may be needed. While this will add some
cost, overall cost will be reduced by improving yield.
Test & inspection While it is impossible to inspect quality into a product, test and inspection are commonly
used to assure process control. Thus some level of visual, X-ray and electrical test is used
to verify the quality of assemblies. Assembling BTC devices with solderable flanks has been
shown to promote improved post-reflow inspection capability. Current BTC device
processing steps do not guarantee solderable flanks. Requiring device suppliers to produce
BTCs with solderable flanks may require adding additional processing. Post-reflow
inspection that allows bad or marginal solder joint escapes leads to lower end user
confidence and higher total cost.
Reliability Rigorous design control reduces cost by ensuring reliability. Demonstrating the reliability of a
design can be an expensive process and represent a major up front cost. A failure, however,
especially a field failure, has arguably even greater cost impact.

Figure 3-8 Solder Mask Clearance Guideline for BTCs

Also the thickness of the paste for BTC is critical since too
little paste will create insufficient or most likely open solder Figure 3-9 Example of Segmented Stencil Pattern Design
joints. But excessive paste may cause floating of BTC. To on Thermal Land
prevent package float during the solder process, paste deposit
The land pattern design should allow extension of the
thickness (especially on the center located thermal pad)
land beyond the package footprint outside of the
should not be on the excessive side. Figures 3-9 shows a
package to facilitate AOI or visual inspection. It is
stencil design approach to achieve 50 to 60% of the
important to keep in mind that a toe fillet is not required
thermal pad area.
since it is not possible to achieve a toe fillet on a
It is recommended stencil design to provide 50 to 60% solder consistent basis since the packages are sawed and
paste coverage on the thermal pad area and 100% solder paste have an exposed unplated surface. A land pattern
coverage on the I/O lands. Figure 3-10 shows a stencil design extension should provide visual evidence of reflowed
for both a ground plane with reduced paste coverage and solder at the toe of the BTCs even though the edge of
outer I/O pad with stencil apertures with 100% paste the metallization is not wetted.
coverage. It is difficult to inspect BTC solder joints from the top of
the package. So it may be necessary to tilt the PCB to
inspect
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 to remove and replace faulty components. Tools such
as hot air and laser systems are used for rework of
assemblies by removing the component in question,
redressing the lands and adding the appropriate solder
paste or perform and positioning the component before
applying heat.

3.6 Future Needs and Expectations

BTC packages are becoming more and more popular
because of their lower cost. But the lower package cost
has not necessarily translated into lower cost over all
when you take into account the total cost of the package,
assembly, inspection, repair and potentially increased
field failures. The root cause often attributed to this
increased failure is the lack of protruding leads which,
on the positive side, is the foundation of increased
thermal and electrical benefits of the BTC package
family.

As the industry has been constantly focused on cost

reduction, the package suppliers have carved out
Figure 3-10 Recommended Stencil Design to Provide a niche to reduce package cost. There remains a lot to
50-60 Percent Paste Coverage to Ground Lands (but 100% be done about reducing PCB and manufacturing cost.
on I/O lands)

BTC solder joints to see solder underneath the package 4 COMPONENT CONSIDERATIONS
even though no toe or end fillet is expected. See 7.4 for
more detail for post assembly inspection techniques of This section provides the details of various BTC from
BTC devices. the point of view of the component manufacturer.
The common fabrication methods using both
X-ray inspection is one way to detect solder shorts leadframes and substrates are described as well as
underneath the BTC package. The X-ray image is also common defects from each of these processes. The
a good way to view solder voids in the solder joints. The section describes not only the manufacturing
acceptance limit of percentage of voiding in BTCs process flow for producing the different packages but
should be less than acceptable limits of 25% voids describes the geometries, materials and many
allowed in BGAs since there are no balls in BTCs and standard variations.
hence the potential for void is much less than in BGAs.
However the void limits in the BTC thermal solder joints Although a number of small outline semiconductor
will have to be much higher because of much higher package innovations have been available (BGA and
solder paste volume used on thermal pads. It is FBGA), an effective method to significantly reduce the
recommended that producers/manufacturers determine package area and cost was not available until
the voids allowable in volume and distribution for the introduction of the SON and QFN package
respective application requirements. technology. The most significant feature of all of these
small outline leadframe package families is their power
The micro-sectioning and die penetration techniques dissipation capability and minimal electrical
are other methods of inspecting solder joints. parasitics. The improved thermal dissipation
These methods are not meant for production inspection, performance comes from the exposed leadframe that is
but should be used for process development. used to help pull heat out of the die to a mating thermal
pad on the circuit board. Electrical parasitics
BTC components removed during PCB rework should are inherently low due to the small size and short wire
not be reused for final assemblies. A package that has bonds.
been attached to a PCB and then removed has seen
two solder reflows and if the PCB is double sided, the 4.1 General Description of Different BTC Packages
package has seen three solder reflows. Thus the A large variety of bottom termination component
package is at or near the end of the tested and qualified packages are in the market. A few of the options are:
range of known survivability. These removed BTC
components should be properly disposed of so th will 1. package configuration
not be mixed in with fresh equivalent BTC components. 2. pitch (1.0-0.4 mm)
See 7.7 for more detail for rework and repair of BTC 3. termination geometry
devices. 4. land pattern geometry
5. package thickness
The rework station for BTCs should be similar to many 6. thermal pad geometry
other type rework systems and have available the tools 7. plating

15
Figure 4-1 shows some of the BTC parts as shipped by consist of several different, but complementary,
the manufacturer to the board assembly plant. functions that together create a product that can be
classified as a system-in-package (SiP). See Figure 4-2.
These parts are available in a variety of configuration.
Table 4-1 shows the configurations of QFN and 4.2 Detailed Description and Standards for BTCs
SON (DFN) that are available from one packaging
foundry. Other foundries are likely to have many of 4.2.1 Single Row Molded Lead-frame Based
these as well as some that do not appear here. The Packaging
JEDEC Standards list many other size, lead and
thickness combinations that result from a general The Die Attach Pad (DAP), when exposed outside the
approach. Most of those listed, however, are not in mold compound, also serves as a heat spreader.
common use. The die element is first bonded to the DAP surface
followed by wire-bond termination from the die bond
Table 4-1 QFN and DFN Configurations pads to the contact features at its perimeter (see Figure
Typical QFN/SON (DFN) 4-3). The package is completed when the plastic casing
Plastic Packages That are Commercially Available is molded around the die and wire-bond area leaving
All dimensions in millimeters only the bottom area of terminals and heat spreader
Lead Nominal exposed for solder attachment.
Size QFN DFN Pitch Thickness
2x2 6, 8 0.50 0.9
To control the effects of the large surface area of the die
3x3 8 0.65 0.9 attach pad feature during the reflow soldering process, it
3x3 12, 16, 8, 10 0.50 0.9 will be necessary to tailor the solder stencil pattern or
3x3 20 0.40 0.9 alter the mating thermal plane on the PC board.
4x3 12 0.50 0.9
4x4 16 0.65 0.9
4.2.2 Multiple Row Molded Lead-frame Based
Packaging
4x4 20,24 0.5 0.9
5x5 20 0.65 0.9 Plastic quad configured multiple row no-Lead packages
5x5 28, 32 0.50 0.9 (QFN) are plastic semiconductor packages with
6x6 40 0.50 0.9 metallized terminals. Terminal contacts are located
7x7 48 0.50 0.9 along the edges of the bottom surface of the
7x7 56 0.40 0.9 package body arranged in 1, 2 or 3 rows. Typical of the
single row QFN, the multiple row QFN package
8x8 52, 56 0.50 0.9
is a lead-frame based product. Before wire-bond, the
9x9 64 0.50 0.9
die is bonded to the DAP surface followed by
12x12 100 0.40 0.9 wire-bond termination from the die bond pads to the
contact features at its perimeter (see Figure 4-4).
Land Grid Arrays are built in comparable sizes to those
in the JEDEC standards and those in the table The package is completed when the plastic casing is
above. LGAs are typically larger than 5 mm x 5 mm and molded around the die and wire-bond area leaving only
are almost always built on a multilayer the bottom area of terminals and heat spreader exposed
substrate. Many of the laminate based LGA for solder attachment. The die attach ‘paddle’, when
components include multiple die elements and a exposed, also serves as a heat spreader.
number of passive devices. These configurations may

Figure 4-1 Various Forms of BTC Parts

16
 4.2.3.2 QFN
Plastic Quad Flat No-Lead Packages have terminals on
all four edges of the bottom surface of the package. The
QFN can have either a square or rectangular body
outline as well as either symmetric or asymmetric
terminal patterns.
The single row small outline no-lead (SON) and quad
flatpack no-lead (QFN) package technology has
become a viable low cost methodology furnishing a
package outline only slightly greater than the die.
JEDEC defines the QFN/SON as a plastic
semiconductor package with metallized terminals
located on the bottom of the package body along its
periphery as detailed in Figure 4-5.

Figure 4-2 Singulated LGA Showing Bottom of Part

Figure 4-5 Terminal Configuration for Single Row SON

and QFN Packaging

As noted in earlier sections, because the terminal

features are flush with the bottom surface of the plastic
body and do not protrude beyond the body outline,
these packages are categorized as “bottom termination
components” or “no-lead”. In addition, the supplier has
Figure 4-3 Basic Single Row Lead-Frame Based SON-QFN the option of supplying an exposed heat spreader
Package Assembly Model element on the bottom surface to assist in transferring
thermal rise generated by the die element into the host
circuit structure using solder or thermally conductive
compounds.

The JEDEC design guide defines the symbology,

algorithms, and recommended dimensions and
tolerances for a family of QFN and SON Packages. The
guidelines are based on hard metric dimensions and
adhere to the geometric dimensioning and tolerancing
principles defined in ASME Y14.5M-1994.

Figure 4-4 Basic Multiple Row QFN Package Assembly In regard to the contact numbering method for the SON
Model package positions terminal #1 (viewed from the top
surface) at the lower left corner. Dimension ‘D’ should
4.2.3 JEDEC Publication 95 Design Guide 4.8 then be measured in the horizontal direction.
The following excerpts are for Plastic Quad and Dual Similarly, measure dimension ‘E’ in the vertical direction
Inline, Square and Rectangular, No-Lead Packages for both package types. For QFN, the position
(With Optional Thermal Enhancements). They include of terminal #1 is perpendicular to the body edge in the
JEDEC definitions for SON and QFN packaging. upper left corner as compared in Figure 4-6.

4.2.3.1 SON (DFN) Terminal #1 identifier and terminal numbering

Plastic Dual Inline Flat No-Lead Package is a convention will conform to JEDEC Pub.95, Sec 4.3,
semiconductor package with metallized terminals SPP- 002. Terminal #1 identifier will be located within
located on the bottom of the package. The SON has the zone indicated on the outline drawing. Topside
terminals on only two opposite sides of the bottom terminal #1 indicator may be a molded or marked
surface. By design, these terminals are flush with the feature. Optional indicator marking or features may also
bottom surface of the plastic package body outline. The be furnished on the bottom surface as well.
industry also uses the term DFN (dual flat no-lead) to
describe SONs.
17
Figure 4-6 JEDEC Defined Package Outlines for Single Row SON And QFN Packaging

Basic dimension for D and E dimensions suggested in There are three terminal variations-
the JEDEC design guide to be in increments of 0.50 mm 1. Pullback – The terminals are located completely
ranging from 1.00 mm through 12.00 mm. Outlines with under the package body outline.
"D" and "E" increments less than 0.50 mm should be 2. No Pullback – The terminals extend all the way to
Registered as "standalone" outlines. These outlines the edge of the package outline.
should use as many of the algorithms and dimensions 3. Extended – Terminals extend beyond the body
(stated in this guide) as possible to ensure predictability outline (flange type molded version) but the overall
in manufacturing. measurements do not exceed the ‘D’ and ‘E’
dimensions defined in the guideline.
The JEDEC members acknowledge that differing
manufacturing processes by supplier companies will The terminal contacts may be furnished in ‘odd ‘or
require some flexibility in the package configuration. ‘even’ numbers as illustrated in Figure 4-8. Inner edge
Although the primary controlling dimensions will remain of corner terminals may be chamfered or rounded in
common, the terminal geometry may vary from one order to achieve minimum gap ‘k’. This feature should
supplier to another. not affect the terminal width ‘b’ which is measured from
the edge of the package body.
An example of two terminal design variations is detailed
in Figure 4-7.
18
Figure 4-7 Terminal Design Variations for Single Row SON and QFN Packaging

Figure 4-8 Odd and Even Terminal Contact Layout

Suppliers will generally furnish components with a document allows two optional length dimensions
balanced depopulation to reduce unequal surface defined as ‘short foot’ and ‘long foot’. The terminal is
tension forces that may occur during reflow solder classified as "short foot" when ‘L’ nominal is 0.35-0.45
assembly processing. Non-symmetric package mm. If the package terminal dimension ‘L’ nominal is
configurations should be separate mechanical outline 0.50-0.60 mm, it is classified as a "long foot" variation.
variations including depopulation graphics.
Corner population of terminal features is also an option In regard to contact pitch, although six variations are
on the QFN package and both SON and QFN, included in the guideline standard, a majority of
as noted, may be furnished with an exposed portion of products actually reaching the market have been
the die attach pad on the bottom surface as supplied with either 0.65 mm or 0.50 mm pitch. The
shown in Figure 4-10. The bottom exposed die attach 0.40 mm pitch devices are also being offered for limited
pad may be a solid or segmented, arranged in a applications, however, second level assembly
matrix format, and may have optional corner radii on processing requires very strict control.
each segment.
4.2.4 JEDEC Publication 95 Design Guide 4.23
4.2.3.3 SON/QFN terminal spacing and dimensions The JEDEC Design Guide applies to Punch-Singulated,
The ‘b’ dimension represents the width of the metallized Fine Pitch, Square, Very Thin and Very Very Thin
terminals (including lead finish) exposed at the bottom Profile, Lead-frame Based, Quad No-Lead Staggered
surface of the package. The terminal width (b) will vary Dual-Row Packages (with optional Thermal
as the pitch dimension narrows as shown in Table 4-2 Enhancements). The examples shown in Figure 4-11
represent dual and triple row QFN with and without
The length (L) of the terminal as measured from the optional exposed die attach pad features.
edge of the plastic body. The JEDEC 4.8 guideline

19
Figure 4-9 Depopulation Schemes for Single Row QFN Packaging

Figure 4-11 Fine-Pitch Two Row QFN (No lead) Packaging

In regard to the description of the package as ‘very thin’

Figure 4-10 Corner Terminals and Exposed Heat Spreader and ‘very-very thin’, the overall component height is
measured from the seating plane (surface of the host
The QFN is described as a plastic semiconductor substrate). The very thin (V) version will have a
package with metallized terminals located along the maximum dimension of 1.0 mm while the package
peripheral edges of the bottom surface of the package. defined as very-very thin (W) configuration has a 0.8
As noted, the package terminals are flush with mm height limitation. The uniform square body
the bottom surface of the plastic package body, so the dimensions are established in 1.0 mm increments from
packages are considered to be “BTC” or “nolead”. 5.0 mm through 12.0 mm and, depending on contact
This package has 2 rows of terminals on all four pitch (0.50 mm or 0.65 mm), an established maximum
peripheral edges of the bottom surface of the terminal count possible in the two row configuration (see
package (see Figure 4-12). Table 4-3).

The dual row QFN package may have either symmetric Outlines with "D" and "E" increments less than 1.00 mm
or asymmetric terminal patterns. Terminal A1 identifier will likely be registered as “stand-alone" outlines. These
must be located within the zone indicated on the outline outlines should use as many of the algorithms and
drawing. Topside terminal A1 indicator may be a dimensions (stated in this guide) as possible to ensure
molded or marked feature and an optional indicator on predictability in manufacturing.
bottom surface may be furnished as a molded, marked,
or metallized feature.

Table 4-2 Terminal width variations for SON and QFN

20
 Figure 4-12 QFN Dual Row Package (top and side views)

Table 4-3 Body Outline and Maximum Terminal Count The JEDEC design guide document explains that the
Terminal Count by Pitch tolerance that controls the position of the entire terminal
Body Outline
0.65 mm 0.50 mm pattern (bbb) with respect to Datum’s A and B cannot
5.00 x 5.00 36 52 exceed 0.10 mm. The center of the tolerance zone for
6.00 x 6.00 44 68 each terminal is defined by the basic dimension “eT” as
related to Datum’s A and B.
7.00 x 7.00 60 84
8.00 x 8.00 76 100 The bilateral profile tolerance (aaa) that controls the
9.00 x 9.00 84 116 position of the plastic body sides cannot exceed
10.00 x 10.00 100 132 0.10 mm. The centers of the profile zones are defined
11.00 x 11.00 108 148 by the basic dimensions D and E.
12.00 x 12.00 124 164 centerline-tocenterline spacing between two adjacent
Maximum terminal counts are calculated rows of terminals (eR) is 0.65 mm for the 0.50 mm pitch
using established formulas. terminals and for the 0.65 mm pitch variation the
spacing is specified at 0.75 mm. The nominal length
(L) specified for the metallized terminals (including lead
finish) exposed at the bottom surface of the package is
Depopulation of terminal features is allowed, but only 0.40 mm with a min./max. tolerance of 0.10 mm as
under the following conditions: illustrated in Figure 4-14. The minimum separation
1) Depopulation scheme must be consistent in each between the inner terminal tip and the heat spreader
quadrant of the package. feature and or between the terminals at the package
2) Non-symmetric variations should be broken out as corners is 0.20 mm.
separate mechanical outline variations, including
depopulation graphics.

In regard to terminal layout variations, terminals are

defined as even row spacing or odd row spacing as
illustrated in Figure 4-13.
21
 Figure 4-13 Outer and Inner Terminal Layout Variations

Figure 4-14 Two Row Terminal Layout

The tolerance that controls the position of the optional

exposed metal heat spreader feature is
positioned so that the center of the tolerance zone will
be the datums defined by the centerlines of the
package body. Because the die element is mounted to
the inside surface of the heat spreader, thermal
transfer of any heat generated by the die can be
effectively transferred onto the surface of the host
circuit structure. Although the dimple detail on the top
surface of the mold compound clearly identifies
the orientation of the device, the addition of a small
chamfer or notch feature on the exposed die attach
pad (illustrated in Figure 4-15) further assists in
confirming the location of the A1 and B1 terminal.

4.2.5 JEDEC Publication 95 Design Guide 4.19 Figure 4-15 The notch feature on the exposed die attach
JEDEC defines this package family as a ‘Plastic Quad pad confirms package orientation with reference to the A1
No-Lead (QFN) having staggered’ or inline multi row and B1 terminals
terminals. Typical of the preceding package
configurations, this QFN family is classified as a plastic that may be laminate based or plastic molded
semiconductor package with metallized terminals leadframe-based. The primary difference of this
located along the edges of the bottom surface of the variation from the two previous guidelines is that this
package body. This design guide furnishes the primary guideline details the requirements for square or
outline features of the family of packaging rectangular contact terminal features arranged in 2 or 3
rows typical of those shown in Figure 4-16.
22
 0.05 mm. The tolerance that controls the position of the
entire terminal pattern with respect to Datum’s
A and B is 0.10 mm for the 0.65 mm and 0.50 mm pitch
package and is reduced to 0.07 mm for the
0.40 mm pitch package variation. The center of the
tolerance zone for each terminal is defined by the basic
dimension ‘e’ as related to Datum’s A and B.

The overall package outline dimensions are defined as

‘D’ for package width and ‘E’ for package length. The
current document specifies that the ‘D and E’
dimensions be in increments of 0.50 mm ranging from 4
mm to 19 mm. Outlines with ‘D’ and ‘E’ increments less
than 0.50 mm should be registered as “stand-alone "
outlines. These outlines should use as many of the
algorithms and dimensions (stated in this guide) as
possible to ensure predictability in manufacturing. The
overall package height is not specifically defined but the
Figure 4-16 Two and Three Row QFN Package Examples
guideline recommends a profile no higher than
1.0 mm where the overall component height is
By design the package terminals are flush with the
measured from the seating plane (surface of the host
bottom surface of the plastic package body, so the
substrate). The unilateral tolerance located above the
packages are considered to be “BTC” or “no-lead” and,
seating plane wherein the bottom surface of all
as noted, the package has 2 rows or 3 rows of
terminals must be located is 0.08 mm. This tolerance is
terminals on all four edges of the bottom surface of the
commonly known as the “coplanarity” of the package
package.
terminals. The tolerance which controls the top surface
of the package is nominally 0.10 mm.
The package can have a square or a rectangular body
The basic QFN package outline shown in Figure 4-20
as well as symmetric or asymmetric terminal
defines the basic outline features referenced above for
patterns as detailed in Figure 4-17 and Figure 4-18.
‘D’ (package width) and ‘E’ (package length) and ‘A’,
overall package height.
Three contact pitch (e) variations are specified; 0.65
mm, 0.50 mm and 0.40 mm. The dimensions
defined for the terminals are adjusted to allow clearance Terminal A1 identifier must be located within the zone
at various pitch conditions and the supplier indicated on the outline drawing. Topside terminal A1
has the option of selecting uniform or non uniform ‘b’ indicator may be a molded or marked feature. Optional
and ‘L’ dimensions to provide a square or indicator on bottom surface may be
rectangular geometry. (see Figure 4-19). a molded, marked, or metallized feature. See Figure
4-21 for examples of pin 1 indicator.
The tolerance that controls the position of the terminals
to each other (e) is nominally defined at

Figure 4-17 Basic Two Row Terminal Layout Variations

23
 Figure 4-18 Basic Three Row Terminal Layout Variations

Figure 4-19 Contact Geometry Variations

4.3 Detailed description of QFN and SON (DFN)

Packages
4.3.1 Manufacturing Methods

BTC package configurations are frequently used for

individual semiconductor chips and less frequently
to package multiple components. See Figure 4-22.

The outline dimensions of the BTC package family

ranges between 2.0 mm x 2.0 mm having only four
terminals to 12 mm x 12 mm outline with as many as
108 terminals. The package height may vary between
0.4 mm to 1.5 mm, however, a 0.8 mm to 1.0 mm
package height are more common. There are a number
of terminal spacing (pitch) variations allowed on the
BTC packages with 0.4 mm, 0.5 mm and 0.65 mm
being the most common. QFNs and SONs (DFN) are
most commonly assembled on an etched or stamped
metal leadframe that is 0.150 mm to 0.200 mm thick.
The die attach side of a multiple site leadframe panel is
Figure 4-20 Basic QFN Package Outline Drawing shown in Figure 4-23 and the bottom side of the panel is
shown in Figure 4-24.

24
 Figure 4-21 Pin 1 Location Option

Figure 4-23 Typical Die Attach Side Leadframe with

NiPdAu Finish for QFNs

Figure 4-24 Typical Solder Pad Side of QFN Panel for with
Tape Over the Leadframe
Figure 4-22 BTC Multiple Package Configurations

The leadframe panel shown in Figure 4-23 and Figure The major purpose of the undercuts is to provide
mechanical interlocking of the mold compound and
4-24 measures 75 mm x 300 mm and includes
four sections each having 42, 7.0 mm x 7.0 mm QFN leads to increase the mechanical strength.
sites. The bottom, or terminal side of the leadframe
In preparation for package assembly and to
panel will be covered with a protective film that prevents
mold compound from encroaching onto the terminals accommodate the eventual mounting of the BTC
surface during the overmold process. package, the leadframes are electroplated with alloys
compatible with both wire-bond processing and reflow
Leadframes are usually made from rolled sheet copper solder soldering (a NiPdAu alloy composition is most
etched from both sides with slightly different patterns. common).
The difference in etch pattern gives the undercut
evident in the drawings and sketches in section 4
25
Another option is to spot plate the wire-bond sites with a
silver alloy leaving the remaining area of the copper
based leadframe without plating until after the overmold
process. The remaining exposed contact and thermal
pad features on the panel are plated with a tin-alloy
finish for solder attachment.

The BTC package assembly process may vary

somewhat from one supplier to another, but, the basic
sequence of assembly for the product described above
will follow the flow of the diagram detailed in Figure
4-25. and additional is typically reserved for very high volume
production.
An overmolded version of the leadframe in Figure 4-23
is shown in Figure 4-26. The example is a four section The process flow for Punch Singulated QFNs is
overmolded array right after it was removed from the illustrated in Figure 4-27.
mold. The dark colored areas are the molding
compound that form the 4 arrays, each of which The mold design for the punch singulation method is
measures approximately 45 mm x 55 mm. The dark more complex and expensive than those used for saw
areas around the periphery and between the molded singulation. Punch singulation requires a mold with a
arrays are mold compound that fill slots in the cavity for each part so that the web of the
leadframe. leadframe remains exposed between individual parts.
This web is punched out in a single stroke with a
Following the overmold process the individual devices die that matches the part.
will be marked and singulated from the panel format.
The most common method for singulation of BTC Both saw singulation and punch singulation leave bare
devices is a precision saw. An alternate method uses a copper edges on the leads where they are cut from the
punch press operation. For this method the mold design leadframe. These bare edges can serve as a surface for
will be pre-segmented at each device site to provide a solder fillet if the solder system will wet the bare
access for the die-punch. Due to the high cost of tooling copper.

Figure 4-25 QFN Fabrication with Saw Singulation

26
 Figure 4-27 QFN Fabrication with Punch Singulation

Some users may also require BTC suppliers to take cavity walls have some draft shown in the sketch to
additional measures, after singulation, to preserve flank facilitate removing the molded parts from the cavities
solderability. These measures are intended to allow
users to rely on toe fillets formed along the BTC flanks A second characteristic of punch singulated devices
as an aid to reliable assembly inspection. evident in the image on the left of Figure 4-28 is the
small leadframe extension beyond the edge of the
molding compound to provide space to prevent the die
The illustrations in Figure 4-28 show the detailed from cutting the mold compound.
differences that result using punch singulation and saw
singulation. The sketch on the right of Figure 4-28 shows the saw
singulated cross section that lacks both draft and the
While punch singulated packages are individually extended lead. Figure 4-28 also shows the 3 common
punched from molded strip during final assembly, the wire bond options:
saw singulated package are assembled in array format  bonds between the die and the finger leads
and separated into individual components during the  bonds between the die and the die attach pad (so
final sawing operation. called “down bonds”).
 bonds from the die pad to the finger leads.
The image on the left of Figure 4-28 is punch singulated
from an array of individually molded sites. The mold. These wire bond options are used to make the required
electrical connections.

Figure 4-28 Comparing punch-press and saw-cut singulation and illustrating wire bond options

27
Saw singulated packages are further divided into two  Inadequate tolerance control of the part dimensions,
options as illustrated in Figure 4-29: the nopullback especially the width and length, resulting in a poor
(full) lead package, and the pullback lead package. fit to test sockets
While the full lead package has the whole  Incorrect marking of pin 1
thickness of the lead exposed on the package sides, the
lead pullback package has a bottom half etch Table 4-4 shows some examples of common leadframe
leadframe, resulting in only the top half of the lead package defects. The table provides three
thickness exposed to the sides of the package. levels of defects and highlights the possible causes.

The plating characteristics are an important part of the

leadframe BTC construction. Attachment both within the
component package as well as the external terminations
must be carefully addressed for the most robust joint
structure. Table 4-5 provides some examples of the
potential defects.

4.3.3 Marking Alternatives

Common methods of marking BTC packages are:

 pad printing with a high contrast ink, usually white
 Laser marking to give finer features that often has
Figure 4-29 Example of half etch pullback contact and full low contrast
etch no-pullback perimeter contact configurations  Laser marking using an ink that provides good
contrast as well as fine features
The pullback approach is only viable when the package
is built into an etched leadframe. The pullback 4.3.4 Materials Used
approach provides better capture of the lead and thus Leadframes are most commonly made of copper.
makes the package stronger. One disadvantage A variety of molding compounds are used. Which is
is that some test sockets may not be designed to make used depends not only on the part and components
contact in this area. within the QFN-SON, but the mold design and molding
machine. These molding compounds are formulated to
A more important disadvantage of the pullback have excellent flow characteristics to ensure fill while
configuration is that the solder joint is not visible minimizing wire sweep.
making inspection more difficult. The mold compound
blocking access to the ‘pullback’ terminal makes A variety of lead finishes are used. The most common
it impossible to form a solder fillet on the outer edge of are NiPdAu, and Tin. SnBi is also sometimes used as a
the device. While the unplated surface of these plating finish as is plated solder using other alloys.
edges that result from both the punching and sawing Table 4-5 shows some of the plating variations while
processes makes solder wetting difficult, the pull Figure 4-30 shows the thickness relationships of some
back configuration virtually guarantees that a fillet of the plating combinations.
cannot form with any soldering process.
4.3.5 Solderability Testing
4.3.2 Types of Defects The solderability testing of BTC components should be
Common defects that result from the fabrication conducted in accordance with the IPC-J-STD- 002
methods described are: specification. A number of individual test methods are
 delamination of the mold compound from the applicable to the BTC components. Test Method S (for
leadframe that sometimes results in wire bonds tin/lead solder processes) and S1 (for lead-free solder
pulling loose from the leadframe processes) are the most applicable for BTC surface
 mold compound flash on the leads or die pad that mount components.
interferes with soldering, die attach or wire bonding
voids resulting from incomplete mold compound fill 4.4 Custom QFN and SON (DFN)
bond wire sweep in the molding process resulting in
shorted wires or, less frequently, broken wires One of the attractive features of the leadframe based
 smear of copper during the sawing process along QFN family of BTC packages is the relative low cost
the side of the package, sometimes severe enough and minimal time required to design and fabricate a
to result in shorting, especially during SMT solder custom version. All of the processes, materials, etc.,
reflow
 burrs from the sawing or punching process
interfering with the planarity of the part or the
geometry of the solder joint

28
 Table 4-4 Leadframe Package Defects and Failure Modes
Common Leadframe Based Package Defects & Failure Modes
Defect/Failure Mode Potential Failure Detection method Cause
Level 1, within package
Excess water content due Pop corning, Hard to detect. Water uptake from environment
to inadequate storage or delamination during when parts are not stored or dried
drying solder reflow. properly
Detrimental package Corrosion, Ultrasonic Poor molding control or poor
compound voids delamination handling
Cracked package Mechanical and/or Visual examination, Excess mechanical bending of
electrical failure die penetrant package, mold compound knit line
Lead to compound failure Lead falling off or Visual examination Molding, sawing or punching
potentially resulting in lead breaking wire bond process defect
fall out
Paddle to die delamination Overheating, wire Ultrasonic, Poor wetting, incorrect cure
break, die cracking decapsulation
Broken wires Electrical open X-ray Wire bonding process control
error, mold compound sweep
Lifted stitch/broken heel to Electrical open X-ray, electrical test Wire bond process control error,
leadframe surface contamination,
inadequate plating
Lifted wire bond balls from Electrical open X-ray, electrical test Wire bond process control error,
die surface contamination, die
metallization error
Shorted wire Electrical short X-ray, electrical test Mold wire sweep, or wire bond
process control
Level 2, outside of package
Non-wetting lead surfaces Open connection Visual, X-ray oxidized surfaces, plating
contamination or incorrect
thickness
Out of dimensional spec Poor contact in test Measurement Molding (thickness) or singulation
socket
Lead smear of copper Shorting of leads Visual Sawing conditions
Inadequate flatness Open joints Visual Molding or singulation method
Burrs Electrical shorts Visual Singulation process
Dimples on pads cause by Void in solder joint Visual Aggressive probing breaks
test socket contact and potential open through plating resulting in
connection non-wetting spot and void in final
joint
Marking defects Wrong part or Visual Poor marking, handling damage
unknown part
Level 3 package to board
Voiding in joints Long term electrical X-ray Solder paste or reflow process
open
Non-wetting of pads Electrical open X-ray, electrical test Part contamination or solder
process
Bridging under package Electrical short X-ray, electrical test Part or board contamination,
solder process
Liftoff of package from Electrical open, less Visual Too much solder paste
PCB due to floating on the shock resistance
solder
Sinking of package into Electrical short X-ray Part too heavy for reflow
solder due to its weight conditions, paste or solder
causing detrimental solder rheology at temperature
displacement resulting in
bridges and/or poor joints.

29
 Table 4-5 Plating Systems Used on Metal Leadframes
Plating types Characteristic Descriptions
Tin plate 10 μm min. Most common.
Often called the Samsung 0.4 mm pitch are all NiPdAu. Larger are
NiPdAu 0.508 μm, 0.013 μm and 0.005 μm finish other systems
Tin finish with Ag on bond sites Post mold tin plate of bare copper
0.4 mm pitch are all NiPdAu. Larger are
NiPdAu 1.02 μm, 0.08 μm and 0.010 μm Often called the Shinko finish other systems

Figure 4-30 Plating Layer Construction Comparison

are described above for QFNs. The major method of Another alternative is to split the thermal die pad. That
customizing is modifying the leadframe. Figure 4-31 option allows some thermal isolation of individual die.
shows several modifications built into one leadframe.
4.5 Detailed Description of LGA, QFN and SON (DFN)
Substrate-Based Packages

4.5.1 Manufacturing Methods for Substrate-Based

Packages

Substrate-based packages are similar to

leadframe-based packages in many ways. Many
devices that can be packaged using the leadframe
approach could also be packaged using a substrate. For
reasons having to do with cost and reliability, substrates
are used as an alternative to leadframes in only small
volume.

Substrates are sometimes used for individual die but

more commonly to interconnect and package multiple
active and passive components. Many of these
assemblies are SiPs (system in a package) per the
ITRS definition implying at least 2 different active
Figure 4-31 Detailed View of a Custom Site for a QFN components. Others that do not comply with the strict
SiP definition are simply high density electronic
This leadframe is not square but measures 5 mm x 7 assemblies. The density is increased by using direct die
mm with 7 leads on one side and 9 on the other. In attach, stacking die, flip chip assembly, 0201 and 01005
addition, leads on two sides are tied directly to the die SMT parts.
paddle.
30
The substrates used for BTC devices are essentially  sawing induced defects such as delamination of the
multilayer circuit boards, often built with BT dielectric mold compound from the substrate
and frequently implemented utilizing HDI technology.  warpage from the molding process or inherent in the
Figures 4-32 and 4-33 show both sides of a typical substrate that interferes with the planarity of the part
substrate for a BTC part. or the geometry of the solder joint
 Movement or sweeping off of SMT parts due to
excessive temperature rise during the molding
process
 excess water uptake by the part during storage
resulting in delamination during solder reflow

Table 4-6 shows some examples of common substrate

based package defects. The table provides three levels
of defect potential and highlights the possible causes.
Figure 4-32 Bottom View of Land Grid Array Printed Board
4.5.3 Marking Alternatives

Common methods of marking these packages are the

same as those used with QFNs and SONs
(DFN):

1. Pad printing with a high contrast ink, usually white

2. Laser marking to give finer features but often furnish
a low contrast image
3. Laser marking onto a printed ink background
Figure 4-33 Top View of Land Grid Array Printed Board
provides good contrast as well as fine features
The substrate measures ~75 mm x 300 mm. This
bottom surface of the substrate is eventually soldered to 4.5.4 Materials Used
the circuit board. Those sites with an “X” were found to Substrates are commonly built using standard circuit
be defective during board test and will not be populated. board fabrication methods. Many of the substrates
This particular substrate does not have a large pad in incorporate HDI technology to increase density.
the center as many QFNs do because the final package Four-layer boards are common.
does not dissipate a lot of heat so a good thermal
connection to the circuit board on which the BTC device The most common dielectrics are BT and FR-4.
is attached is not required.
A variety of board finishes are used depending on
Figure 4-33 shows the top surface of the substrate choice of the designers working with both the substrate
where parts are placed. 0402 down to 01005 size fabricator and the assembly house. Since most BTC
SMT parts are commonly used. Die interconnect is substrate based packages incorporate some wire
either wire bond or flip chip, often with multiple die. bonded die, gold finish on at least the component
25 parts in a 7 mm x 7 mm size is common. Many of surface of the substrate is common. A typical system is
these assemblies are Systems in a Package (SiP). Ni Pd with an Au flash that is wire bondable, solderable
and avoids the risk of solder embrittlement.
A typical process flow to assemble a BTC using a
substrate like that above is shown in Figure 4-34. A variety of molding compounds are used. The choice
depends not only on the part and components within the
QFN-SON, but the mold design and molding machine.
4.5.2 Types of Defects
These molding compounds are formulated to have
Some common defects that result from the BTC on excellent flow characteristics to ensure fill while
substrate fabrication methods described are: minimizing wire sweep. They are also formulated to
have a TCE that is close to copper and to comply with
 delamination of the mold compound from the
environmental requirements.
substrate that results in pulling parts off of the
substrate
4.6 Description of Commercial Variations
 mold compound flash on the leads that interferes
Many detailed variations of the QFN and SON (DFN)
with soldering
type of BTC have been developed. These are now
 voids resulting from complex internal geometry that marketed under a broad number of trademarks and
is hard to fill or from mold compound that does not acronyms by various companies, a few of which are
flow for some reason described below.
 wire sweep in the molding process resulting in
shorted wires or, less frequently, broken wires

31
 Figure 4-34 BTC Fabrication on a Substrate with Saw Singulation

4.6.1 Detailed Description of MLF®, MLP, and

MLFP™ Components Carsem's MLP (Micro Leadframe Package) is a family
of JEDEC compliant QFN plastic packages. This near
4.6.1.1 Part descriptions CSP package is available in three versions. The Quad
The microleadframe (MLF®), micro leadframe package (MLPQ™) has 4 sides of I/Os with a body size range of
(MLP) and micro leadframe package (MLFP™) 3 x 3 mm with 8 I/Os to 9 x 9 mm with 64 I/Os and body
are all near CSP size plastic encapsulated quad contact thickness options of 0.9 mm, 0.75 mm, plus the
configured no-lead (QFN) packages with a Ultra-Thin that is only 0.5 mm thick. The Micro (MLPM™)
copper lead-frame substrate. This package family uses has 2 sides of I/Os with a body size range of 2 x 2 mm
perimeter lands on the bottom of the package to provide with 3 I/Os to 3 x 3 mm with 10 I/Os and a thickness of
electrical contact to the PCB. Typical of all QFN 0.9 mm. The Dual (MLPD™) versions are designed to
packaging, these variations offer a thermal provide a footprint compatible replacement for SOIC,
enhancement by having the die attach paddle exposed SSOP, TSSOP and MSOP packages. Typical of most
on the bottom of the package surface to provide an QFN and SON devices, MLPs have an exposed die
efficient heat path when soldered directly to the PCB as attach pad for improved thermal performance. However,
exhibited in Figure 4-35. the company also offers a non-exposed pad option they
refer to as COL™ (Chip On Lead), FCOL™ and other
Fairchild and Carsem’s MLP (Micro Leadframe Package) special applications.
are near chip-size plastic encased packages that are
JEDEC MO-220 and MO-229 compliant QFN and SON The Micro Leadframe Plastic Package (MLFP) from
(DFN) plastic packages. The highdensity lead-frame Intersil is also a JEDEC standard package outline
package design is furnished with RoHS compliant (EIA/JEDEC Publication 95, MO-220). Figure 4-37
lead-free plating and meets the most stringent moisture illustrates a section view of a 16-Lead MLFP package.
sensitivity level (MSL)1. To provide even greater The die pad and perimeter I/O pads are fabricated from
utilization of package space and enhanced performance, a planar copper lead-frame substrate.
MLPs have the bottom exposed thermal feature visible
in Figure 4-36.

32
 Table 4-6 Substrate Based Package Defects & Failure Modes
Substrate Based Package Defects and Failure Modes
Defect/Failure Mode Potential Failure Detection method Cause
Level 1, within package
Excess water content due to Pop corning, delamination Hard to detect Water uptake from environment
inadequate storage or drying during solder reflow when parts are not stored or
dried properly
Detrimental package Corrosion, delamination Ultrasonic Poor molding control
compound voids
Cracked package Mechanical and/or electrical Ultrasonic Poor molding control or poor
failure handling
Substrate to compound Broken connection, Visual examination, Molding or sawing process
failure corrosion from water die penetrant defect
ingress
Part to substrate Open circuit, die Ultrasonic, Inadequate mold compound
delamination overheating, bond wire decapsulation, cross flow, poor wetting of parts and
break, part cracking sectioning substrate, surface contamination
Broken wire bonds Electrical open X-ray Wire bonding process control
error, mold compound sweep
Lifted wire bond Electrical open X-ray, electrical test Wire bond process control error,
stitch/broken heel to surface contamination,
substrate inadequate plating
Lifted wire bond ball from die Electrical open X-ray, electrical test Wire bond process control error,
surface contamination, die
metallization error
Shorted wire Electrical short X-ray, electrical test Mold wire sweep, or wire bond
process control
Level 2, outside of package
Non-wetting lead surfaces Open connection Visual, X-ray oxidized surfaces, plating
contamination or thickness
Out of dimensional spec Poor contact in test socket Measurement Molding (thickness) or
singulation
Lead smear of copper Shorting of leads Visual Sawing conditions
Inadequate flatness Open joints Visual Substrate defect, Molding or
singulation method
Burrs Electrical shorts Visual Singulation process
Dimples on pads cause by Void in solder joint and Visual Aggressive probing breaks
test socket contact potential open connection through plating resulting in
non-wetting spot and void in final
joint
Marking defects Wrong part or unknown Visual Poor marking, handling damage
part
Level 3 package to board
Voiding in joints Long term electrical open X-ray Solder paste or reflow process
non-wetting of pads Electrical open X-ray, electrical test Part contamination or solder
process
bridging under package Electrical short X-ray, electrical test Part or board contamination,
solder process
liftoff of package from PCB Electrical open, less shock Visual, cross-section Too much solder paste
due to floating on the solder resistance
sinking of package into Electrical short X-ray, cross section Part too heavy for reflow
solder due to its weight conditions, paste or solder
causing detrimental solder rheology at temperature
displacement resulting in
bridges and/or poor joints.

33
 can be processed using the existing package assembly
infrastructure
4.6.1.2 Tolerances Dimensions and tolerances conform
to ANSI Y14.5M, all dimensions are in millimeters and
angles are in degrees. Figure 4-38 represents the basic
QFN package outline

The QFN family detailed in JEDEC registered outline

MO-220 ranges in size from 2.0 mm x 2.0 mm to 12.0
mm x 12.0 mm graduating in 1.0 mm increments. For
each outline there are two lead spacing formats, odd
and even. The image shown in Figure 4-39 represents
the even row variation.

There are five contact pitch variations allowed for the

QFN; 1.0 mm, 0.8 mm, 0.65 mm, 0.50 mm and 0.40 mm.
The length (L) and width of the contact can vary
Figure 4-35 Amkor's 28 I/O MicroLeadFrame® Package significantly between suppliers. Although square
outlines are most common, rectangular outlines are
allowed. The examples shown in Table 4-7 are
represent a number of square and rectangular QFN
package outlines currently available from a prominent
package assembly service provider.

4.6.1.3 Material specification QFN packages are

available in several alloy finishes: post plated SnPb,
Matte Sn, SnBi, pre-plated NiPd with flash of Au.
Surface mount studies on parts plated with NiPd and
Matte Sn show no significant difference compared to
SnPb finish parts. The following are typical of the basic
materials used for QFN package assembly.

Figure 4-36 Fairchild’s MLP is a thermally enhanced SON  Die thickness: 250 μm 50 μm (thinner for special
developed for power switch technology applications)
 Plating: Sn/Pb, Matte Sn, SnBi, NiPd (flash Au)
 Marking: Laser
 Lead-frame: Copper Alloy, Dual gauge
 Die attach: Conductive Epoxy
 Bond Wire: 25 μm low loop
 Mold compound: Pb free/Green capable

4.6.2 Detailed Description of LLC™ and LFCSP™

Components The LLC from Analog Devices and
LFCSP from National Semiconductor are near chip
scale plastic encapsulated wire bond QFN packages
with a copper leadframe substrate in a BTC package
format.

Figure 4-37 Intersil’s Quad No-lead Micro Leadframe 4.6.2.1 Part Description The LLP and LFCSP package
Package (MLFP) is available in two thicknesses variations. The 0.8 mm is
the most prevalent thickness but the package is
This family is described as plastic encapsulated device selectively available in a lower 0.6 mm profile thickness
with the bottom of the die attach pad and contacts. as well. Perimeter input/output pads are located on the
outside edges of the package. Electrical contact to the
The die pad and perimeter I/O pads are fabricated from printed circuit board (PCB) is made by soldering the
a planar copper lead-frame substrate. This is perimeter pads and exposed paddle on the bottom
encapsulated in plastic with the bottom of the die attach
pad (DAP) and I/O pads exposed to create a
very small package outline. In addition to furnishing a
small outline the package has minimal mass and

34
 Figure 4-38 JEDEC MO-220 Package Outline

Terminal contacts:

 The contact pads (or solder pad) are located

peripherally in single row format depending on the
specific number of pins and body size.
 For certain specific applications the packages are
incorporated with common power and/or ground
pins
 All contacts are plated with matte tin solder for ease
of surface mount processing.

The bottom termination QFN package family (see

Figure 4-39 QFN Contact Design JEDEC MO-220) furnishes enhanced chip speed,
reduced thermal impedance, and, because of its small
surface of the package to the PCB. Heat is efficiently outline, minimizes the printed circuit board area required
conducted from the package by soldering the exposed for mounting. The small size and very low profile make
thermal paddle to the PCB as illustrated in Figure 4-40. this package, shown in Figure 4-41, ideal for high
density PCBs used in small-scale electronic applications
Stable electrical ground connections are provided such as cellular phones, pagers, and handheld PDAs.
through down bonds and through conductive die attach
material. Wire bonding is provided using gold wires. In addition to their small package outline and low profile
Perimeter and thermal pad finish is plated as 100% Sn the LLP and LFCSP have a low thermal resistance and
(Sn/Pb is available as well). Packages are punched or reduced electrical parasitic.
sawed from a molded strip during final assembly.
4.6.2.2 Package Tolerances
Half-etching of the leadframe provides mold compound
locking features for the perimeter pads and die thermal
This JEDEC design guideline standard for this package
paddle. This package is currently characterized as
family applies to packages with optional thermal
moisture sensitivity (MSL) level 3 (see IPC/JEDEC
enhancements as well as various height profiles and
J-STD-020 for MSL levels).
pitches. This package has terminals on all four edges of
the bottom surface of the package. The LLC and
LFCSP can have either a square or a rectangular body
35
 Table 4-7 Typical Package Outline and I/O for QFN
Body Size (mm) QFN lead counts (0.8, DFN/SON Lead counts Dual Row Lead counts
0.65, 0.5, 0.4 mm pitch (1.27, 0.95, 0.5 mm pitch (0.5 mm pitch)
< 2 x 2 (saw only) - 4/6/8 -
2x3 - 6/8 -
3x3 4 / 8 / 10 / 12 / 16 8 / 10 -
4x4 12 / 16 / 20 / 24 / 28 - -
5x5 16 / 20 / 28 / 32 / 36 - 44 / 52
6x5 36 8 -
6x6 20 / 28 / 36 / 40 / 48 - 60/68
7x7 28 / 32 / 44 / 48 / 56 - 76 / 84
8x8 32 / 40 / 52 / 56 / 68 - 92 / 100
9x9 36 / 44 / 60 / 64 / 76 - 108 / 116
10 x 10 44 / 52 / 68 / 72 / 88 - 124 / 132
11 x 11 - - 140 / 148
12 x 12 48 / 60 / 84 / 88 / 100 - 156 / 164

developing the land pattern and thermal paddle

geometries.

The width of the metallized terminals (including lead

finish) exposed at the bottom surface of the package is
detailed in Table 4-8.

For component tolerances and profile tolerances usually

given in the package outline drawings are converted
into maximum material condition (MMC) and least
material condition (LMC) based tolerances.

4.6.2.3 Material Specifications

In compliance with RoHS and WEEE, companies

modified molding compounds and, in some cases, die
attach materials. In addition, there was strong support
Figure 4-40 Analog Devices LFCSP™ (Leadframe from users for converting mold compounds to more
Chip-Scale Package)
robust versions so that packages are compatible with
higher temperatures required for reflow soldering
lead-free alloys. The data supplied in Table 4-9 is
typical of the device packaging materials listed in a
‘materials declaration’ form for the LLC and LFCSP.

The change to RoHS compliant elements provided base

material sets that demonstrate capability to meet
elevated reflow conditions of 255°C (+5/-0°C) for
lead-free reflow. Additionally, most companies are
offering lead-free lead finish on all plastic encased
LFCSP packages from Sn85Pb15 to 100% Sn (tin
Figure 4-41 National Semiconductor LLP™ (Leadless plating) to eliminate Pb from these package types.
Package)
Other material elements:
outline as well as either symmetric or asymmetric
terminal patterns. Versions of the Internal leadframe plating Ag (silver)
package may also have terminals placed in the corners External leadframe plating Sn (tin)
at 45 degrees to neighboring leads. The basic Bond wires Au (gold)
dimensions for the package outline are shown in Die element Si (silicon)
increments of 0.50 mm ranging from 1.00 mm through
12.00 mm. The outline detail shown in Figure 4-42
illustrates the primary dimensions used when

36
 Table 4-9 Basic Material Elements for the LLC and LFCSP
Devices
Category Materials Content
Mold com- SiO2 Fillers 86.9%
pounds Epoxy and Phenol Resins 12.8%
Carbon Black 0.3%
Die attach Ag (silver) 73.4%
material Epoxy Resin 18.35%
Metal Oxide 2.75%
Curing Agents 2.75%
Gamma Butyrolacetone 2.75%
Leadframe Cu (copper) 97.5%
Fe (Iron) 2.35%
Zn (zinc) 0.12%
P (phosphorus) 0.03%

Figure 4-43 JEDEC Tray Carrier Format

The overall dimensions of the JEDEC shipping and

handling tray carrier are 135.9 mm x 322.6 mm with
components arranged in a column and row format. The
matrix of the pocket pattern is fixed to a standard
formula based on the outline of the semiconductor
package. Although the components mounted in the
Figure 4-42 Typical LLC and LFCSP Outline Detail carrier are shipped with a ‘dry pack’ wrapping, the
plastic material used to mold the carrier must withstand
Table 4-8 Contact Pitch and Width Variations thermal exposure typical of that required for ‘bake-out’
Contact Terminal dimensions of components that are exposed to ambient conditions
Pitch Minimum Nominal Maximum and prone to moisture retention. For more detailed
0.65 0.25 0.30 0.35 information on the carrier tray specification see JEDEC
0.50 0.18 0.25 0.30 Publication 95 Design Guide 4.10.
0.40 0.15 0.20 0.25
All of these package delivery systems use ESD safe
materials.
Although no change may be made to a component’s
part number, products converted to lead-free will be
The environmental conditions these devices are
identified on the outer packaging label, and if space
designed to tolerate are:
permits, a Pb-free symbol will be marked on converted
devices.
 Moisture sensitivity JEDEC Level 1*
characterization 85 0C/85%, 168 hours
4.7 Packaging and Handling
BTC parts are shipped in a variety of standard  HAST 130 0C/85% RH, 96 hours
configurations designed for automated assembly  Temp cycle -65/+150 0C, 1000 cycles
system efficiency. QFN products and BTC devices built  Temp/Humidity 85 0 C/85% RH, 1000 hours
on substrates are shipped in tubes, stackable JEDEC  High temp storage 150 0C, 1000 hours
tray carriers (Figure 4-43), or in tape and reel. SON
(DFN) devices are commonly shipped in tubes or tape
and reel.

37
5 MOUNTING STRUCTURES circuit product. The traditional multilayer is created by
printing and etching thin layers of copper clad
This section provides information on the various substrates and laminating them into a monolithic
materials and concepts used to produce a mounting structure which can be drilled and plated so as to make
structure onto which the BTC may be placed and connection between the layers where required.
properly attached. Also included in addition to the
physical requirements will be electrical, thermal and More recently, however, alternative structures have
construction detail intended to provide a clear been developed to address the higher density and
correlation with the BTC design and assembly process. routing difficulties associated with BTCs. These newer
Some new techniques for providing interconnection structures employ a variety of different approaches to
concepts will be explored as well as a method for create suitable multilayer structures. The new structures
embedding the BTC into the mounting structure. are referred to as High Density Interconnect (HDI)
printed boards and include build-up multilayers,
5.1 Types of Mounting Structures PCBs and other sequential multilayers and colaminated multilayers.
similar types of interconnection platforms serve as the
mounting structures for BTCs and other components. A key feature of these structures is their use of very
There are a variety of alternative mounting structures small vias. The term microvias has been applied to
available which serve BTC needs as interconnection describe these miniscule interconnections. A typical
substrates for electronic assemblies. These structures microvia is less than 150 μm in diameter and has a
employ a wide range of materials, both organic and capture land (where the via starts) and a smaller target
inorganic and have a wide range of physical properties. land (where the via ends). Figure 5-1 shows one of the
Materials choice is normally made based on most popular HDI structures, although methods of
cost/performance needs of the finished product. stacking the micro vias have also been developed as
shown in IPC-2226.
5.1.1 Organic Resin Systems Organic substrates are
the most commonly used in the construction of
electronic interconnection structures. There is a
well-established worldwide manufacturing base for this
type of product. As a result of the large manufacturing
base, this type of interconnection structure has the
lowest cost among the competing technologies. Organic
materials have intrinsic beneficial electrical properties.
Most notable is a relatively low dielectric constant on
average which can be made much lower by the proper
Figure 5-1 Typical Build-up HDI platform, 2[4]2 Layer
choice of resin and reinforcement. Organic substrates Configuration
are commonly reinforced using an appropriate material
such as woven glass cloth; however, flexible circuit 5.2 Properties of Mounting Structures Mounting
materials are not commonly reinforced. structures for BTCs are identical to those that satisfy the
needs of many different component package
5.1.2 Inorganic Structures Inorganic substrates are configurations. These configurations drive the
alternatives to the organic substrates; they are usually complexity of the mounting structure and determines the
refractory materials comprised of sintered metal oxides. resin, reinforcement and, for many applications, the
While they are typically brittle, they have some metallic configuration of the surface to which the
significant benefits not easily obtained with organic components are attached.
substrates.
PTH vias connect the PCB thermal pad to any
Chief among the advantages are excellent thermal electrically appropriate internal PCB plane(s). For
properties. Like organic structures, there are a number double-sided PCBs, the un-tented PTH vias has the
of possible choices available: ceramic, silicon, and potential for solder, during wave soldering of mixed
enameled metals. The dielectric properties of these assembly, to reach the PCB top side and cause
materials tend to be higher than organic based secondary reflow, leading to potential opens and shorts.
materials and, because they are brittle, they are So PTH vias should be plated shut, plugged with epoxy
generally more prone to breakage. Because of the more or tented with solder mask to avoid low package
limited vendor base for inorganic substrates, these stand-off height due to solder wicking into the PTH vias
structures are normally more expensive. during the reflow process. However, plating of vias shut
may increase PCB cost.
5.1.3 Layering (Multilayer, Sequential or Build-Up
and HDI) While single and two metal layer circuits are To achieve the highest possible thermal performance, it
still common, multilayer interconnection structures are is good to use a maximum number of PTH vias, but it is
commonly required to support the interconnection of important to keep in mind that they do impact the
BTCs in today’s high performance electronics. soldering surface of the PCB thermal pad. A
recommended via pattern is 0.3 mm PTH via drill
There are several approaches to creating multilayer diameter on 1 mm centers but much smaller

38
vias are also being used. Improved thermal the electrical properties. Presently, E type glass is the
performance can be obtained with a greater density of most commonly used glass cloth for printed circuit
vias and larger vias on the same pattern that provides substrates.
good solderability.
5.2.2.2 Glass Felt
5.2.1 Resin Systems There are a number of different Glass felt or non-woven glass mat has been commonly
resin systems suitable for use in organic laminate used as a reinforcement material for
construction. There is a long and well understood fluoroplastic resins and is commonly used in low loss,
history and years of faithful service for the traditional RF or microwave applications. It has seen some
resins systems. However, to support the move to meet application in formable laminates as well but the
legislated lead-free requirements by the EU, many new technology is not widespread.
resins are being developed to meet the higher
temperature assembly reflow requirements. Test 5.2.2.3 Aramid Cloth
methods have been developed, i.e., Td (Temperature of Aramid cloth has been used to reinforce certain
decomposition) and T260, T288, T300 (Time to laminates. It is unusual in that it has a negative CTE in
Delaminate), to quantify material properties for the X and Y direction, which helps to offset the in-plane
conformance to the new EU requirements. Some of the CTE of the resin. Because of the counteracting
new resin systems are classified to new material slash expansion and contraction, laminate materials of this
sheets such as IPC-4101 /99, /101, /121, /124, /126 and combination can match approximately the CTE of
/129. ceramic. However, a drawback of the material is that the
aramid has Z axis CTE much higher than glass and, in
5.2.1.1 Epoxy There are a number of different resin thermal excursions, can fracture nearby resin, leaving
systems that can be used to create a printed wiring micro-cracks along the surface of the fibers.
substrate. Epoxy is among the organic resins with the
longest history and it is one of the most commonly used 5.2.2.4 Aramid Paper
resin systems for PCBs. It offers a good blend of The supply of non-woven aramid paper has diminished
physical, electrical and processing properties at due to a lack of manufacturing sources. Aramid papers
reasonable cost. The general properties are provided in have been effectively used in a number of multilayer
Table 5-1. Higher temperature capability epoxy resin applications. They have most of the benefits of the
systems have been developed for lead-free applications aramid cloth with more process latitude. They are often
and are available at a cost premium. used for thin core layers at or near the surfaces of the
multilayer printed boards to better control CTE. Because
5.2.1.2 Polyimide Polyimide offers the highest the aramid is organic, it has the added advantage of
operating temperature among resin systems in use being more easily processed by laser ablation and can
today. It has been a favorite for military applications also be processed using plasma etching for making
where the potential for board rework and repair in the holes. The organic nature of the material also helps to
field with uncontrolled soldering tools is anticipated. keep the dielectric constant low.
Because of its high glass transition temperature, 5.2.3 Reliability Concerns with High Temperature
polyimide provides a safety margin and potential to Lead-free Soldering
reduce damage to the board when uncontrolled The higher temperatures required for soldering lead-free
soldering irons are used to remove or replace a solders creates reliability concerns for the survivability
component. The general properties are provided in of the PCB resins as well as the integrity of the PCB
Table 5-1. interconnect structures, such as plated-through holes
and vias.
5.2.1.3 Bismaleimide Triazine Bismaleimide triazine or
BT resin is the most popular choice for the construction The properties that are most important in this respect
of some semiconductor packages including BTCs, are the thermal expansion, the glass transition
because of its combined advantages of high temperature and the decomposition temperature. The
temperature capability at reasonable cost. The general thermal expansion from 50–260°C, TE(50-260°C) is a
properties are provided in Table 5-1. composite of the thermal expansions below and above
the glass transition temperature. The glass transition
5.2.2 Reinforcements Reinforcements provide the temperature (Tg) is the temperature at which an
dimensional stability and the bulk of the mechanical amorphous polymer, or the amorphous regions in a
properties of the organic substrate laminate. Following partially-crystalline polymer, changes from being in a
are some of the more commonly used reinforcements. hard and relativelybrittle condition to being in a viscous
or rubbery condition.; These different molecular
5.2.2.1 Glass Cloth Glass cloths are the most structures result in very different physical properties.
commonly used reinforcement for printed board See Figure 5-2. The decomposition temperature (Td)
substrates. They are widely available and are measures the temperature at which the resin
processed with relative ease. The cloths are available in decomposes irreversibly, and thereby loses weight;
a number of different thicknesses and weaves. The typically the temperature to a weight loss of 2% or 5% is
chemical make-up of the glass can vary and can affect measured.

39
 Table 5-1 Environmental properties of common dielectric materials
Material
FR-4 High Bismaleimide
(Epoxy Multi-Functional Performance Triazine/ Cyanate
Environmental Property E-glass) Epoxy Epoxy Epoxy Polyimide Ester
Coefficient of Thermal
Expansion, xy-plane, 16 -19 14 -18 14 -18 ~15 8 -18 ~15
CTE(xy) (ppm/°C)
Coefficient of Thermal
Expansion, z-axis below
50 -85 44 -80 ~44 ~70 35 -70 ~81
Tg1, CTE(z,<Tg)
(ppm/°C)
Coefficient of Thermal
Expansion z-axis above
240 -390 240 -390 240 -390 TBD TBD TBD
Tg1, CTE(z,>Tg)
(ppm/°C)
Thermal Expansion
3.0 - 4.5 2.5 - 4.0 2.0 - 3.5 TBD TBD TBD
z-axis, TE(50-260°C) (%)
Glass Transition
110 -140 130 - 160 165 - 190 175 - 200 220 - 280 180 - 260
Temperature2, Tg (°C)
Decomposition
Temperature3, Td (5%) 310 -330 320 -350 330 -400 334 ~376 ~376
(°C)
Soldering Temperature
170 -205 200 -220 215-260 TBD TBD TBD
Impact Index4, STII
Flexural Modulus (GPa)
18.6 12.0 18.6 20.7 19.3 22.0 20.7 24.1 26.9 28.9 20.7 22.0
Fill5 Warp6
Tensile Strength (MPa)
413 482 413 448 413 524 393 427 482 551 345 413
Fill5 Warp6
Water Absorption (wt%) 0.5 0.1 0.3 1.3 1.3 0.8
Notes:
1. CTE (z,<Tg) is also known as Alpha 1, and CTE(z,>Tg) as Alpha 2. Contact supplier for specific values of the other materials.
2. The glass transition temperature can be measured by three different methods (TMA, DSC, DMA). Of these the values obtained by
TMA are the most pertinent for the purpose of assessing reliability issues. A very rough relationship between the results of these
three methods is Tg(TMA) ≈ Tg(DSC) -10°C ≈ Tg(DMA) -20°C. Contact supplier for specific values of other materials.
3. The decomposition temperature can be measured to two different values of weight loss, Td (2%) and Td (5%). Td (5%) is more
commonly used, but Td (2%) is becoming popular because of its greater usefulness. Contact supplier for specific values of other
materials.
4. Soldering Temperature Impact Index, STII, which is defined as STII = Tg/2 + Td/2 — (TE%(50 to 260°C) x 10).
5. Fill - yarns that are woven in a crosswise direction of the fabric.
6. Warp (cloth) - yarns that are woven in a lengthwise direction of the fabric.
the Tg. The z-axis expansion will have its greatest effect
The impact of these three properties is captured with on plated-through hole and via reliability.
the Soldering Temperature Impact Index, STII, which is
defined as STII = Tg/2 + Td/2 — (TE%(50–260°C) x 10). Table 5-1 shows the conditions for various reinforced
This equation relates to the material Tg and Td plus the resin types. All thermal expansion is measured in
thermal expansion characteristics. See Table 5-1. parts/million/change in temperature (°C).
Where:
5.2.5 Moisture Absorption
Tg is the laminate glass transition temperature Most organic materials are hygroscopic to some degree
Td is the temperature that the material decomposes and soak up moisture at different rates; some do so
TE is the thermal expansion from 50 to 260°C in percent relatively rapidly. This moisture absorption changes the
electrical properties of the material such as loss tangent
5.2.4 Thermal Expansion and as well the processing characteristics of the
Thermal expansion is usually characterized in terms of material as outgassing can result in blisters. It can also
changes to the x-y plane, which is controlled primarily impact physical dimensions and the laminate’s weight.
by the reinforcement of the material. The x-y expansion
will have the greatest effect on surface mounted
components and their reliability. Thermal expansion
also occurs in the z-axis at a rate significantly larger
than in the x-y plane, particularly at temperatures above

40
Figure 5-2 Material Thermal Expansion Comparison

Thus a simple way to determine that the material has flatness measurement at room temperature, and also at
absorbed moisture is to note the increase in weight the elevated temperatures (e.g., 260°C) for
under defined moisture exposure conditions. Table 5-1 implementing lead free soldering. Traditional techniques
shows the water absorption rate by weight for the of measuring overall board flatness, do not reflect the
various materials highlighted in this section. problems in attaching high terminal count BTCs to
certain local areas of a board.
5.2.6 Flatness (Bow and Twist)
The planarity of 1.5, 2.25 and 3.0 millimeter thick boards 5.3 Surface Finishes
varies, especially with respect to being able to assemble Printed board surface finishes serve several functions,
BTC type parts. Flatness is measured in relationship to these include: solderability provision and protection,
the length and width of the laminate or the completed reliable contact surface for contacts/switches, wire
printed board. The term bow is applied to the longest bondable surface, and solder joint interface. Although
dimension of the part; whereas twist requirements are BTCs are the focus of this document, the other
applied to the length across the diagonal distance. components and assembly operations of the printed
These requirements are usually set as a percentage board must be taken into consideration when choosing
allowance of the distance in question. Thus, the the most appropriate surface finish. There is no single
allowable bow of a printed board might be specified as surface finish that will be best for all applications.
0.50% of the length of the longest dimension.
The key to flatness however in regards to the mount of While no surface finish is ideal for all applications, the
BTCs needs to be evaluated based on localized search continues for improved surface finish
flatness measurement with such techniques as shadow solutions. Because of the component mix many have
moire imaging. This technology allows local been satisfied with some of the immersion surface
41
finishes, immersion immersion silver in particular, widely from 0.75 μm to 35 μm. It is generally held that
however since the emphasis on mounting BTCs is to the lower thickness is not acceptable because
make sure that there is sufficient solder volume some the very thin layer of solder is completely transformed
companies still require some form of solder as into copper-tin intermetallic, which has very poor
the preferred finish. The concern is mainly the uniformity solderability. However, studies on the solderability
of the final board finish as well as the flatness evaluation of printed boards with HASL and other
of the plating or coating on the land to which the BTC protective coatings indicate that soldering performance
will be attached. as indicated by visual examination showed no
correlation to the solder thickness or solder coverage on
Some of the application features are provided in Table the lands observed in cross-sections. As a
5-2. result, acceptance criteria for the solderability of printed
circuit boards should be based on functional
5.3.1 Hot Air Solder Leveling (HASL) testing of sample boards.
The surface finish of long standing is hot air solder The wide variation seen in solder thickness in HASL
leveling (HASL). In this process, the finished printed affects the coplanarity of solder termination on the
board is dipped either vertically or horizontally into a printed board and hence the components. Moreover,
molten solder bath and the excess solder is blown the uneven surface makes more difficult the
away and leveled with hot air, giving the process its paste-printing task, because it makes it more difficult to
name. The HASL process is the first soldering achieve good sealing of the stencil while
stress that the printed board experiences. Some printing. Lack of a good seal or “gasketing” will result in
material combinations may be prone to delamination leakage of solder paste beneath the stencil.
during the multiple excess temperature exposures. The result is that the manufacturer must either increase
The HASL finish provides a virtual guarantee of the frequency of cleaning (thus lowering
solderability in that the process creates one half of the throughput) or risk increased potential for bridging (thus
soldered joint by fully wetting the copper substrate. The lowering yield).
quality of the product regarding solderability 5.3.1.2 Lead-free HASL
can be confirmed easily through a simple dip test, The lead-free hot air solder leveling process has proven
conditioned by an aging process or by simple visual to provide both quality and reliability of the
inspection. Any evidence of non-wetting or dewetting is surface finish in providing long shelf life solderability.
immediately apparent as the board exits the The most likely candidates for lead-free HASL are
process. Sn-Cu eutectic (227°C melting point), or Sn-Ag-Cu
The HASL solder surface finish provides a long eutectic (217°C melting point). Other SAC alloys
solderable shelf life. Solderability is lost only when the such as 105, 305 or others may also be candidates. The
intermetallic has grown through the surface. Thus, a Sn-Ag-Cu alloy appears to offer an advantage
properly applied coating can last more than a year due to its lower melting point, but there are also
if stored correctly. In addition, the coating’s solderability advantages of the tin-copper system since the raw
properties will survive several cycles of materials are readily available, and represent the lowest
adhesive cure or paste reflow. cost. The Sn-Cu solder pool is easy to
5.3.1.1 Tin Lead HASL manage and recycle since there are only two
Although the tin lead surface finish was the main constituents. The solder bath is not too aggressive, has
solution for many printed boards, one concern with low copper pick up characteristics, and is relatively
the HASL process is the coating thickness uniformity. tolerant of common impurities.
Often in the process, the solder thickness varies

Table 5-2 Key attributes for various board surface finishes

Electroless Electrolytic
HASL NI/Immersion Ni/Electroplated Immersion Immersion
SnPb/SnCu* OSP AU AU Silver** Tin
Shelf Life
proper
Handling 1 Year 6 Months > 1 Year > 1 Year 6 Months 6 Months
Avoid physical Avoid physical Avoid physical
Handling Normal contact Normal Normal contact contact
SMT land Sur-
face topology Domed/Not flat Flat Flat Flat Flat Flat
Multiple Good, need Fair, better
assembly robust with thick
reflow cycles laminate coatings; Good Good Fair/Good Fair/Good
Notes:
* Tin copper alloy is the preferred alloy for lead-free HASL
** May require an organic preservative in order to remain untarnished.

42
The melting point is low enough for most current method will work. The coating thickness can range from
equipment and components and, with some of the very thin (0.01 μm) to relatively thick 0.2 to 0.5 μm. The
newer laminate properties, is compatible with the thicker coatings are preferred over the thinner coatings,
printed board fabrication sequence and processing. In especially if there is need for multiple reflow cycles
order to fine tune the process, solder alloy bath and/or a long wait (e.g., days) between soldering of
suppliers have added a proprietary stabilizing each side. It should be noted that all OSPs are not alike
constituent—HASL, which is identified as Sn-0.7Cu. A since there are specially developed OSPs to withstand
typical alloy developed for lead-free soldering is the higher reflow profiles associated with lead free.
SnCuNi with a melting temperature of 227°C and a
processing temperature for soldering of 250°C to 260°C The OSP surface has many advantages. Most important
(482°F to 500°F). Copper dissolution can be a problem of all, it avoids the key problem of the tin/lead HASL by
if the bath exceeds 0.85% copper which will likely keeping the board surface flat. It is also lead-free and
increase the incidence of bridges, icicles, and other will meet with EU legislative requirements. An OSP may
defects. The Sn-0.7Cu+Ni is 227–265°C (38°C variation) also improve gasketing, thereby reducing solder paste
vs. Sn63Pb37 183–250°C (67°C variation). printing related defects and thus provides better overall
yield.
The finish has good solderability which is retained
through thermal excursions and storage. The finish is Because the OSP coating is transparent, the coated
smooth and bright and less domed than the tin/lead it is terminations maintain their copper appearance, further
replacing. The solder bath composition can be held enabling the detection of any solder paste misprint
stable by the use of a low copper top-up alloy, and conditions. Alcohol or other solvents, if used for washing
dross losses are low. Most important is that the alloy is off the misprinted paste, will also wash off coatings, and
not aggressive towards solder bath materials. therefore will increase the risk of oxidation of the copper
which impacts solderability. However, such boards can
In situations where large boards (>250 x 250 mm) are be recoated if necessary. Washing and wiping the board
used with large BTCs (>25 x 25 mm), it may be a good is not recommended, but should instead be processed
idea to increase the printed board thickness to at least 2 in accordance with IPC-7526 which recommends stencil
mm to minimize board bending and flexing. This will and misprinted board application data. Process
reduce or eliminate interfacial failures due to engineers should work with chemical cleaning suppliers
mechanical stress that is caused by bending and flexing to establish the correct cleaning process that will
of the printed board. However, with the conversion to remove the wet paste and minimize removal of the OSP
lead free, thicker boards will require a greater time at surface.
temperature exposure making reliability a greater
concern. The increase in the use of thin PCBs (<0.5 mm There are some potential process incompatibilities with
in thickness) in many hand held products may preclude OSPs. For example, if paste or flux does not cover all
the use of HASL because of warping of the PCBs during land surfaces during soldering, there may be some
processing. dewetted appearance after reflow soldering. It is thus
important for flux to get into the PTH during wave
5.3.2 Organic Surface Protection (Organic soldering to achieve topside fillet. Similarly, in the SMT
Solderability Preservative) Coatings process, the paste must cover the entire land surface to
With wide spread use of bottom termination avoid dewetted appearance at the land edges. Another
components (BTC) and more fine pitch devices such as example may be potential incompatibility between
the land grid array, the need for increased control of no-clean fluxes and certain solvents. There is also the
PCB flatness is more critical. As an alternative to potential of solderability concerns when the assembly is
HASL, which can cause warping, an alternative surface subjected to multiple thermal cycles during reflow, wave,
finish is organic solderability preservative (OSP). An and hand soldering.
OSP is an anti-tarnish coating of an organic compound
(such as a benzimidazole-based compound) which is 5.3.3 Noble Metal Platings/Coatings
applied over exposed copper surfaces to prevent With the EU’s legislation to remove lead from electronic
oxidation. An OSP is commonly a water-based organic solder, noble metals, for example gold and palladium,
compound that selectively bonds with copper to provide are seeing increased use as PCB surface finishes. Two
an organometallic layer that protects the copper, other noble metal surface finishes have gained
preserving its solderability. popularity, and are electroless nickel/electroless
palladium/immersion gold (ENEPIG) and direct
Various chemistries of OSPs are available. Some immersion gold (DIG). These are also sometimes called
common ones are benzotriazol, imidazol and universal surface finishes since they can be soldered to,
benzimidazol. These coatings keep the copper surface wire bonded to, and are also suitable as contactable
solderable by preventing oxidation or tarnish. The surface finishes. ENEPIG, in particular, can alleviate
coating is commonly applied either by dipping the board solder joint brittleness problems occasionally seen with
in an OSP bath or by spray. As long as the process is
controlled to achieve uniform OSP coating, either

43
ENIG when used with SAC lead-free BTC termination another combination of electroless and immersion
finishes. plating processes have been developed. The switch to
lead-free solder has raised many issues on the
5.3.3.1 Electroless Nickel/Immersion Gold (ENIG) manufacture, processing, and reliability of lead-free
Electroless nickel/immersion gold (ENIG) provides very electronic products. Some of the evaluations included a
good shelf life, a flat soldering surface for SMT Ni-7%P/Pd/Au (ENEPIG) (5 μm/0.06 μm/0.03 μm)
processing, and a good surface for electrical probe process.
contact required for in-circuit-test (ICT). The ENIG finish
provides solderable surfaces which can survive through 5.3.3.4 Direct Immersion Gold (DIG)
multiple reflow operations and they are less prone to Direct immersion gold (DIG), is another surface finish
handling related problems. The presence of nickel that is able to deposit a fine and uniform gold layer
plating strengthens the through-hole barrels during directly on the copper surfaces. By examining the
multiple reflow cycles and rework of through-hole deposition reaction of the flash gold plating bath, it can
components. Noble metal plating finishes typically cost be confirmed that copper does not co-deposit with gold
more than OSP finishes, and are either comparable or and also that the main driving force for deposition is an
more expensive than HASL, depending on the auto-catalytic reaction. The copper surface roughness
complexity of the PCB. If it is desired to mix multiple affects solder spread-ability, and the solder joint
board finishes on a single board, for example Ni/Au in characteristics are excellent when the film thickness is
some areas and OSP in others, this can be difficult and within the range of 30 to 80 nm. In addition, good wire
expensive to achieve in manufacturing. bonding characteristics can also be derived from
deposits plated by a neutral pH, auto-catalytic type
The reducing agents used in the electroless nickel heavy electroless gold plating bath, atop the flash gold.
process contain either phosphorous or boron. In the
reduction of the nickel in the electroless nickel Lead-free solder results are usually inferior (spread less)
deposition, either phosphorous or boron is incorporated as compared to tin/lead eutectic solder with a
into the nickel deposit. The level of these co-deposited DIG finish. It is necessary to understand this
elements should be controlled within the specified characteristic when lead-free solder is utilized, in that
process limit. Variation of phosphorous or boron level, the IMC layer changes at 150 C degrees with time and
outside the specified process limits, may have adverse shows:
effects on the solderability of the finish and possibly the
reliability of the solder joints. a) A small difference between Sn/Ag/Cu solder and
tin/lead solder IMC layer thickness at 0 hours
5.3.3.2 Electrolytic Nickel/Electroplated Gold b) After 100 hours of exposure the IMC thickness is
Another version of a nickel/gold combination is the usually equal
electrolytic nickel/electroplated gold surface finish. c) The IMC layer of Cu3Sn thickness continues to
This plating is similar, however it results in a different grow as the heating time increases
grain structure from electroless nickel/immersion gold, d) As with tin/lead solder, Cu3Sn is clearly apparent
and does not exhibit the ’black pad’ joint cracking when Sn/Ag/Cu solder is used
phenomenon.
5.3.3.5 Immersion Silver
Electrolytic nickel/electroplated gold is applied after Immersion Silver is a metallic solderability preservative.
pattern plating and most often before solder mask, and It can be permanent, becoming an integral part
therefore carries some risk of surface contamination. of the assembled board, or sacrificial, preventing copper
Solder mask applied over electrolytic oxidation and preserving solderability through
nickel/electroplated gold exhibits lower solder mask the assembly process. Immersion silver is also a good
adhesion than other surface finishes. This can create surface for contact probe testing.
problems during assembly of BTCs, and especially
during rework. If the solder mask dams covering the The industry continues to search for alternative surface
conductors between BTC lands and vias peel off, solder finishes that can overcome the disadvantages
will flow from the lands into the vias and cause associated with the HASL, OSP, and ENIG finishes.
insufficient or open solder joints. Some of the most promising alternative surface finishes
are immersion silver and immersion tin.
Another concern is that it can be difficult to control the
gold thickness across the board. The gold may be too 5.3.3.6 Immersion Tin
thin (for example in areas with dense circuitry) or the Immersion tin has a relatively long history but its use
gold may be too thick (for example in isolated circuits). has been limited due to earlier concerns about
This latter situation may lead to gold embrittlement due intermetallic formation and reduced solderability. These
to excessive gold (>3%) in the solder joints. concerns seem to be getting addressed in more recent
processes. Immersion tin is a metallic solderability
5.3.3.3 Electroless Nickel/Electroless preservative that is sacrificial, preventing copper
Palladium/Immersion Gold (ENEPIG) oxidation and preserving solderability through the
In order to address some of the problems with the assembly process.
electroless nickel/immersion gold (ENIG) process,
44
Due to the higher contact resistance of tin it is not as separated from the array and fluxed as single
good as immersion silver for contact probe testing. One images before shipping.
of the concerns about the amount of tin in the solder 5.4 Solder Mask
joint of lead-free solder is the growth of tin whiskers as
the unit experiences changes in various stresses. Solder mask is a polymer coating which serves to
protect copper surfaces which are not to be soldered.
Both immersion silver and immersion tin are deposited Unlike the laminate, which is a composite, solder mask
on the board surface using the immersion method of is commonly a homogeneous material. As the name
metal deposition. suggests, solder mask is used to mask off the outer
surfaces of the board where solder is not required.
5.3.3.7 Solid Solder Deposition Having solder mask over the copper also helps to
Solid Solder Deposit (SSD) has been in existence since prevent bridging between conductors.
1986. It is a method for pre-loading the surface Because of process changes for lead-free soldering,
mount lands with all of the solder needed to complete evaluating solder mask performance takes on a whole
the component attachment, in a solid form. The new meaning.
SSD process uses an adhesive flux coating to hold the
components in place during the final reflow In the past not all boards required a solder mask
cycle. The adhesive flux once dried has a much higher because the conductors and lands were spaced quite
holding power than solder paste and it does not far apart. The solder bridges between adjacent
matter if it is smeared as it is non conductive and non conductors during wave soldering were not likely. But
corrosive. This means that placing components with the advent of fine lines and spaces, the use of a
with lead styles that are blind or underneath the solder mask has become almost mandatory for boards
component body can be done with more predictability that are going to be wave soldered. On a full SMT board
and achieve better yields. where no wave soldering is required, tenting or plugging
of via holes is done to assist drawing a vacuum on
The basic steps for the SSD application are shown in some ICT testers. Also, the application of solder mask
Figure 5-3. to block or plug a via allows closer spacing between a
via and the adjacent conductors.
 Solid Solder Deposit Application Process Sequence
(see Figure 5-4) 5.4.1 Wet and Dry Film Solder Masks
 Printing paste onto pads and reflowing it without Permanent solder masks are available in dry film and
disturbing it is an easier method for applying solder wet film. Dry film masks can have an aqueous or a
paste. All defects associated with Z-axis pressure solvent base. In both cases, the mask starts out as a
from component placement is eliminated. polymer film, which is applied to the board by vacuum
 Reflowing solder paste on to surface mount lands lamination. Wet film solder masks, as the name implies,
also highlights solderability issues associated with are liquid or paste-like. They include photoimageable
the surface finish. De-wetting is easily identified and wet screenable solder masks. The latter are
without the components in the way. differentiated by the method of cure. Some wet
 Reflowing solder without components allows proper screenable solder masks can be cured by UV light and
out-gassing of the flux. Consequently the formation some can be cured thermally in convection or IR ovens.
of voids is decreased or eliminated. UV masks do not provide as good adhesion as thermal
 Cleaning flux residue from bare boards is easier masks but require only seconds to cure as opposed to
and more efficient without the components in the 30-60 minutes for thermal cure.
way.
 The adhesive flux supplied with SSD is tackier than Each of the liquid solder masks has advantages and
solder paste and will last up to 6 months if stored disadvantages. They are inexpensive and highly
properly.The design of a SSD printed circuit board durable. Being liquid, they flow between conductors and
is no different than a standard printed circuit board. prevent the formation of air pockets. There is no trim
waste, and the thickness of the mask can be controlled
The design considerations for an SSD are: for each design. Since the wet film solder masks are
screened on (a mechanical process), they are difficult to
 Completely surround every surface mount feature register and have a tendency to skip over conductors,
with solder mask. This means dams in between all especially on fine line boards. They also tend to bleed
pads to help shape the SSD during flattening. onto the lands and surface mount lands during cure.
Wet screenable masks are difficult to use on boards
 Isolate all holes including via holes so that paste
with fine lines and spaces (<200 μm), and they are also
does not drain during reflow.
vulnerable to voids, bubbles and pin holes.
 Identify lands with via holes in them and the SSD
process can be modified to accommodate a solder
filled via hole in a surface mount land.
 Step small boards into arrays for handling.
Depending on the design, some boards can be

45
46
 Figure 5-3 SSD Application Basic Fabrication Steps

Figure 5-4 SSD Process Steps

application process for dry film solder masks is
The use of screenable mask has been on decline as sometimes difficult to control. Not many film thicknesses
photoimageable solder masks have gained in are commercially available, and this can limit flexibility
popularity. and increase cost. Typically, most dry film solder masks
are 75 μm to 100 μm thick.
The wet film solder mask cannot successfully tent via
holes. The degree of fill needs some control in order to The thicker masks can cause problems in reflow
develop a plug that prevents chemistry from going soldering as well. For example, a dry film mask applied
through the via. Partially filled vias trap process between the lands of BTCs can cause standoff
chemicals and are difficult to clean. problems during reflow soldering because of the rocking
effect of the mask. For this reason, dry film solder mask
Dry film solder masks have some advantages over their should not be used between the lands of BTCs or in
wet screen counterparts. The former provide very assemblies that have components glued to the bottom
accurate registration, which is critical in preventing side for wave soldering.
solder bridging or bleeding on fine line boards, as well
as sharper resolution. Tenting of via holes is also 5.4.2 Photoimageable Solder Masks
superior with dry film solder masks because they are Photoimageable solder masks combine the advantages
never in a liquid state and do not drip into the via during of dry film and wet solder masks. Dry film is also a
vacuum lamination. However some problems may arise photoimageable mask. Focusing on wet film
when trying to laminate a semisolid dry film over an photoimageable masks provide accurate registration;
uneven board surface with conductors and lands. Any they are easy to apply, encapsulate the circuit lines
bow and twisting of the board will compound the totally, have excellent durability, and are less expensive
problem, possibly causing air pockets underneath the than dry film.
dry film near conductors.
Photoimageable masks can be either screened on or
Dry film masks are more costly than the wet film variety, applied by a process called curtain-coating, in which the
and the supplier base is limited. Moreover, the board is passed at high speed through a curtain or
waterfall of solder mask.

47
The photoimageable mask may contain solvent along board manufacturer is understood to accurately provide
with photopolymer liquid. If the solvent is added the relationships of the land pattern for a BTC on one
in the mask, the liquid mask is screened on, solvent is board with all other land patterns of sister boards in the
dried off in an oven, and then the mask is exposed to same panel. Inconsistent arrangement of the assembly
UV light by off-contact or on-contact methods. (If no array can result in misprints when stenciling solder
solvents are used, the liquid is 100% reactive to UV paste onto the panel for surface mount assembly.
light.) The off-contact method requires a collimated light
system to minimize diffraction and scatter in liquid. This 5.4.4 Via Protection
makes the system more expensive. The on-contact
approach needs no collimated UV light source, and the 5.4.4.1 Encroached vias The encroached via concept
system is relatively cheaper. Photoimageable solder is one that permits solder mask being on the land
masks can tent only very small via holes. Most without filling the via plated-through hole. Encroachment
photoimageable wet film masks will not reliably tent 0.35 vias take the primary solder mask opening and adjust it
mm via holes because it is difficult to cure polymer in via so that it is slightly larger than the via hole size. This
holes. If tenting is required, dry film is needed because concept will permit any outgassing or cleaning of the via
only dry film can tent via holes effectively. plated-through hole, provide more surface coverage and
increase adhesion between the solder mask and copper
5.4.3 Registration Registration between individual of the annular ring. It will also provide a larger web
boards within a multi board panel becomes critical for between the land and the via, and thus should minimize
any surface mount application. This is especially true solder mask removal during BTC removal for rework.
when the board is made in a panel array format to assist See Figure 5-5.
the assembly process and throughput characteristics.
Board manufacturers inherently build printed boards in a 5.4.4.2 Via Filling Via filling, capping, flooding, tenting
manufacturing panel format; assemblers also want to and plugging (conductive or nonconductive) are some of
take advantage of the multiple board array format when the process names applied to techniques used to cover
they complete their assembly. or fill via holes with different materials. Materials
currently being used to protect vias include standard
The positioning and orientation of individual boards on liquid photoimageable and non-imageable solder masks,
any panel is usually at the discretion of the board dry film solder masks, specially formulated hole
manufacturer. The manufacturer optimizes the use of plugging inks, conductive inks, liquid dielectric materials
the material in the panel and the tolerance conditions and even materials not used in other PCB
that can be achieved with the material used to build a constructions.
particular board. It is a well known fact that organic
materials are prone to movement (e.g., growth and/or The processes for protection of via structures serve
shrinkage); thus, the board manufacturer, based on different purposes. Via filling is normally performed on
their knowledge of materials and their predicted boards that use both reflow soldering and wave
dimensional change movement, will commonly adjust soldering. Via filling is also recommended under certain
the phototool to compensate for material stretch or specified conditions, such as for boards where exposed
shrinkage depending on the circuit, the board size and vias under BTCs are exposed to a wave solder. The
the particular properties of the selected material. concern is based on the fact that, when a board with
BTCs on the first side is processed through wave
It is important to understand that assembly companies soldering, a large amount of heat can transfer from the
frequently build their stencils based on a process of vias. This can be very significant because some BTCs
“step and repeat” where elements of an individual board can have very high via densities beneath them.
are repeated to match the arrangement of the boards on
the subpanel. It is vital that the exact layout used by the

Figure 5-5 Comparing Solder Mask off Via Land with a Solder Mask Encroached Via Land

48
There are three basic characteristics of via protection  Capped Via – A secondary operation providing a
addressed in IPC-4761. The first is a bumped via, metallized coating covering the via. The
where the hole being plugged or filled with material metallization is on both sides.
protrudes above the surface of the hole interface
producing a convex shape. The second characteristic is Via plugging is frequently used in conjunction with BTCs
one that has a dimple in the construction where the hole to prevent solder flow to the BTC solder joints when
plugging or fill material recedes below the hole interface wave soldering is used. Table 5-3 shows the
producing a concave shape. The last of the conditions is relationship between via filling and the surface finish
identified as a planarized via where the excess hole conditions.
plugging or fill material protruding above the hole
interface has been removed by a process to produce a As a general rule, via flooding and capping processing
coplanar surface. See Figure 5-6. should be performed after a surface finish has been
applied. For OSP and ImAg (immersion silver) finishes,
via capping must be done after the surface finish is
applied because the harsh chemicals that are used to
clean the copper surface can become trapped around
the via cap. These trapped chemicals can damage the
via wall resulting in open vias. Applying the via caps
after the surface finish has been applied can degrade
some surface finishes (e.g., OSP, ImAg, ImSn) due to
the thermal exposure that is necessary to cure the via
cap material.

There are presently seven different methods of via

plugging/capping identified in IPC-4761. These are
shown in Figure 5-7. It is important to realize that the
choice of tented, plugged and filled vias for via
protection can have direct impacts on the subsequent
Figure 5-6 Planarized and Capped Via Protection example assembly processes.

The following definitions apply to the various via filling Besides identifying the seven via protection methods,
operations. There are four basic concepts which there are also pros and cons indicated in IPC-4761. The
include: preference of the plugging method among the options
 Tented Via – A via covered with dry film solder presented will depend on the capabilities of both the
mask; the via has no fill. When tenting from both fabricators and the assemblers. To avoid complication
sides there may be issues with air entrapment and during assembly, it is imperative that all involved in the
expansion during mass soldering. When tenting on manufacturing process understand the trade-offs among
one side there may be issues with chemical the options.
entrapment during the assembly process, especially
when using aggressive flux. For printed boards with HASL finish, the solder coating
 Flooded Via – A via that is flooded with LPI solder will effectively prevent most surface degradation due to
mask; the via is partially filled or the walls are chemical exposure. HASL finishes also increase overall
coated with solder mask. This process could wall thickness of the via barrel. It should be noted that
possibly be improved by using a vacuum assist for vias that are solder coated before plugging, the
table. solder coating will melt during second side reflow. As a
 Plugged Via – An additional operation which is done result, the plugging material can become loose. In some
prior to solder mask application; the via is filled with cases, when there is excessive solder coating thickness
a conductive or nonconductive material. or solder entrapped within via during fabrication, solder
 Filled Via – A via with material applied into the via can potentially outgas and spatter or drain to the
targeting a full penetration and encapsulation of the remaining openings.
hole.

Table 5-3 Via filling/encroachment to surface finish process evaluation

Surface Finish Tenting Flooding Capping Plugging Encroaching
HASL Okay Okay Okay Okay Okay
OSP Okay Not Recommended Okay Okay Okay
ENIG Okay Okay Okay Okay Okay
ImAg Okay Not Recommended Okay Okay Okay
ImSn Okay Not Recommended Okay Okay Okay

49
 Via, Tented
(Type 1 Via)
A via with a mask material (typically dry film) applied
bridging over the via wherein no additional materials
are in the hole. It may be applied to one side or both.
Type I Single Sided Type I Double Sided

Via, Tented and Covered

(Type II Via)
A Type I via with a secondary covering of mask
material applied over the tented via.

Type II Single Sided Type II Double Sided

Via, Plugged
(Type III Via)
A via with material applied allowing partial
penetration into the via. It may be applied from either
one side or both sides.
Type III Single Sided Type III Double Sided

Via, Plugged and Covered

(Type IV Via)
A Type III via with a secondary covering of material
applied over the via. The secondary covering may be
applied from either one side or both sides.
Type IV Single Sided Type IV Double Sided

Via, Filled
(Type V Via)
A via with material applied into the via targeting a full
penetration and encapsulation of the hole.

Type V

Via, Filled and Covered

(Type VI Via)
A Type V via with a secondary covering of material
(liquid or dry film solder mask) applied over the via.
It may be applied from either one side or both sides.
Type VI Single Sided Type VI Double Sided

Via, Filled and Capped

(Type VII Via)
A Type V via with a secondary metallized coating
covering the via. The metallization is on both sides.

Type VII
Figure 5-7 Via Protection Methods

50
5.5 Thermal Spreader Structure Incorporation (e.g., multilayer should be approximately 25% of the board’s
Metal Core Boards) total thickness. Constraining core board is more often
When structural, thermal, or electrical requirements used because the core layers may be imaged, etched,
dictate, a conductive constraining core or metal core and connected to the plated-through hole. The thicker
can be added to the organic substrate to make the new center core must be pre-drilled before lamination to
structure. It is recommended that the board circuit layer accommodate drilled and plated holes needed to join
configuration be made symmetrical about the center of the two outer sections of the PCB. Better thermal cycle
the core. It is possible to create structures that are survival has been shown in some studies for structure
asymmetrical (i.e., having a different number of layers to having two constraining cores in the board rather than
either side of the core); however, plated-through holes one.
going through the entire stack may be less reliable due
to the differences in expansion on either side of the Another configuration is to have a special constraining
metal or constraining core. See Figure 5-8. core board made by bonding a multilayer board to each
side of a thick metal core after each of the boards has
been completed. The composite board is then
sequentially drilled, plated, and etched to form
plated-through hole connections between the two
boards. Coupons should be provided to test the integrity
of the composite structure.

5.5.2 Heat Transfer Pathway

Metal core boards add significantly to the thermal mass
of the assembly. This may force the preheating
soldering process to be operated at abnormally high
limits. These designs should be thoroughly evaluated
under production conditions prior to release. Laminate
ruptures and discoloration and grainier textured solder
are typical effects that have been observed. The heat
transfer path between components and the planes are
Figure 5-8 Metal Core Board Construction Examples usually accomplished through either direct contact with
the plane or through thermal vias positioned under the
The advantage of the asymmetrical design is that it can component and connected to the thermal core or plane
separate electrical properties and functions from in its position.
mechanical features, and/or areas requiring heat
dissipation. Among the drawbacks are the significant 5.5.3 Thermal Pad Attachment
differences in the coefficient of thermal expansion of the In order to obtain peak performance of some BTC high
board and the core material. The circuit board may pin count packages the printed board must be properly
distort during assembly soldering/reflow operations, or designed and the package mounted with special
while the system is in use if exposed to excessive consideration. For enhanced thermal, electrical, and
operating temperature variations. board-level performance, the exposed pad on the
package should be soldered to the board using a
Some compensation can be achieved by having corresponding thermal pad on the printed board. For
additional copper planes added to the back of the proper heat conduction through the board, thermal vias
interconnection product. The extra copper plane may should be incorporated in the printed board design in
increase the expansion coefficient slightly and make the thermal pad region. Clearance between the inner
soldering more difficult due to the need to put more row’s terminations and the thermal pad are required for
energy into the board to assure proper solder joint vias to route the inner row signals. The amount of
formation; however, a positive effect is that it enhances clearance required depends on the application.
thermal conductivity.
The printed board land pattern design should take into
5.5.1 Lamination Sequences account the dimensional tolerance of package,
The more desirable constructions are those where the printed board, and board assembly. Some of the
circuit layers are symmetrical about the core chosen to factors that can significantly affect the mounting of
serve at the center of the board. By so doing, individual the BTC package on the board and the quality of the
multilayer circuits can be produced separately, each solder joints are:
with their own laminating sequence. For example, a four
layer board might be manufactured having vias through  The amount of solder paste coverage in the thermal
the entire four layers and this can be duplicated for use pad region
on either side of the core.  The stencil design for peripheral and thermal pad
region
To achieve mechanical constraint within a chosen and  The type of via used to interconnect the BTC
useful range, the total thickness of the core in the  The printed board thickness

51
 The plated finish on the terminations of the package
 The surface finish on the board
 The type of solder paste
 The reflow profile

Ideally, the size of the thermal pad should match the

exposed die paddle size of the BTC. Due to needed
clearance for vias, the thermal pad size may need to be
reduced to less than the package paddle size. From a
board mounting perspective, there are no major issues
if the board thermal pad is smaller than the package Figure 5-9 Examples of Type VII Filled and Capped Vias
paddle size, however from a thermal efficiency
perspective, there is minimal efficiency loss as long as 5.6 Solderless Interconnections Systems
the thermal pad on the board is close to the same size Due to the regulations eliminating the use of some
as the die inside the package. materials in the fabrication of the electronic assembly
interconnecting structures, several alternative and
The thermal pad design on the printed board should unique assembly methods designed to eliminate solder
have 75% paste coverage and may use a hatch pattern completely from the assembly process are generating
to reduce the amount of total solder paste. The number interest. One approach for discussion is a process
of openings should be chosen in order to maintain a identified as Solderless Interconnection process, e.g.,
web thickness between openings of approximately 0.20 plating process. In this process, tested and burned-in
mm; this will allow space for flux volatiles to escape, packaged components are encapsulated and the
thus minimizing voids. electrical connections are made to component leads
using an electroplating process during the circuit
5.5.4 Thermal Vias patterning, thus bypassing the soldering process.
In order to effectively transfer heat from the top metal
layer of the PCB to the inner or bottom layers, thermal The BTC packages are devices which conform to a
vias should be incorporated into the thermal pad design. common fundamental grid pitch in order to facilitate
The number of thermal vias will depend on the design and testing. The other components that are part
application, power dissipation, and electrical of the electronic assembly should also be available in a
requirements. Although more thermal vias improve the bottom only termination mode. The prospective of
package’s thermal performance, there is a point of benefits of such processing include: lower material use,
diminishing returns where additional thermal vias may reduced energy requirements, fewer manufacturing
not significantly improve the performance. Usually BTC steps, simpler designs with fewer wiring layers, higher
suppliers recommend incorporating an array of thermal performance, improved thermal management, better
vias at 1.0 mm to 1.2 mm pitch with via diameters of 0.3 EMI and ESD protection, obviation of concerns about
mm to 0.4 mm. The number of should be determined for metal finish solderability, solder joint quality or tin
each application operating environment and condition. whiskers.

Thermal vias may take several configurations. They The burned-in or tested components are bonded to a
could be left open, they could be filled with thermally temporary or permanent organic base material, after
conductive materials, they could be plated shut or which the components and base material are over
capped with plating as in the description of a type VII via molded with an insulating material. The assembly is
fill defined shown in Figure 5-9. Any thermal via should inverted and the component leads or terminations are
be connected to a plane within the multilayer board in accessed by ablation of the organic base material. Vias
order to transfer the heat to a cooler material surface. are then plated along the circuit layers as shown in
The concept for BTC removal or replacement needs to Figure 5-10.
address the soldered connection of the thermal pad and
the amount of mass that must be heated in order to Structures fabricated without having to be exposed to
disconnect the BTC from the mounting surface. high temperatures can open doors to new potentials in
terms of interconnection and thermal management. The
structures themselves could be assembled in a modular
form into 3D

Figure 5-10 Example of Circuit Development of Solderless Connection Technology

52
structures that are interconnected on all sides. There (in-line and staggered leads) and full and partial area
are several of these concepts being developed which array devices. The leads on the bottoms of the
make the interconnecting substrate part of the assembly packages can be rectangular or round depending on the
process and thus the lines of responsibility for testing type with lead-frame devices (e.g., QFN) typically
become somewhat blurred. Only time will tell as to represented by the former and substrate devices (e.g.,
which application provides the most benefit to the user LGA) represented by the latter. (see Figure 6-1)
and the status of the infrastructure that can provide this Because BTC packages do not have solder balls
form of interconnection methodology. terminations, the electrical connection between the
package and the assembly board must be made using
6 PRINTED CIRCUIT ASSEMBLY DESIGN only the solder deposited on to the circuit board. Getting
CONSIDERATIONS sufficient solder on the lands and making viable and
This section provides information on the design reliable solder joints is one of the significant challenges
principles for incorporating bottom termination for this type or product. Thus, special attention is
components (BTC) into electronic products including needed in designing the land pattern.
modules and product board design concepts. The
principles define placement and interconnection rules The component land pattern for the PCB is commonly
and the mounting characteristics that must be predicated either on guidelines developed by the
considered during the design process. Methods of component manufacturer, within a company or by
mounting structure requirements are detailed to the following established industry standards such as
extent that they coincide with the assembly process IPC-7351. While BTCs such as the SON and QFN have
considerations. Emphasis is also placed on the thermal been available for some time, they have not been
management of the final assembly and the contribution broadly used and thus the learning experience with
that the mounting structure provides to the assembly. them is still limited and industry guidelines may not have
been refined. The development of an optimum geometry
6.1 BTC Part Description may require some experimental trials. Moreover,
BTC parts are a near chip scale plastic encapsulated because certain structures of the exposed die attach
wire bond package with a copper leadframe or organic paddle and the package lands on the bottom side of the
laminate substrate in a BTC package format. The QFN package, certain constraints must be considered.
and LGA are representative of the package technology.
The QFN variation offers a number of significant The SON and QFN versions are of high interest to
benefits over standard plastic lead-frame packages: industry. The 0.8 mm is perhaps the most prevalent
thickness but the package is selectively available in a
 Reduction in board mounting space as die size is lower profile thickness as well such as 0.6 mm.
closer to the package size. Perimeter input/output pads are located on the outside
 Superior electrical characteristics are obtained due edges of the package. Electrical contact to the printed
to minimal lead lengths, reducing the electrical path circuit board (PCB) is made by soldering the perimeter
distance between die and PCB. pads and exposed paddle on the bottom surface of the
 Lower thermal resistance because the bottom package to the PCB. Heat is efficiently conducted from
exposed die attach paddle can be soldered directly the package by soldering the exposed thermal paddle to
to a corresponding thermal feature on the PCB the PCB as illustrated in Figure 6-2.
surface.
 The QFN leadframe type package assembly Stable electrical ground connections are provided
process utilizes existing proven SO-IC leadframe through down bonds and through conductive die attach
package infrastructure. material. Wire bonding is provided using gold wires.
Perimeter and thermal pad finish is plated as 100% Sn
 Standard SMT assembly equipment can be used
(Sn/Pb is available as well). As noted in Sections 3 and
and high assembly yields can be realized from the
4 SON and QFN packages are punched or sawed from
self-aligning characteristic of the low mass package.
a molded strip during final assembly. Half-etching of the
leadframe provides mold compound locking features for
Coplanarity is not an area of concern for this component
the perimeter pads and die thermal paddle. This
family because all contacts are flush with the bottom of
package is currently characterized as moisture
the package. In regard to moisture sensitivity level
sensitivity (MSL) level 3 (see J-STD-020 for MSL
(MSL), the molding compounds used for encapsulation
levels).
are a resin-based material, so moisture absorption will
vary depending on the size of the specific package, the
Terminal contacts:
size of the die attach pad (DAP) and the number of
wire-bonds.
 The contact pads (or solder pad) are located
6.1.1 BTC Package Variations peripherally in single row format depending on the
The BTC packages are available in various lead formats specific number of pins and body size.
and thicknesses. In general terms, the family of BTC  For certain specific applications the packages are
components includes: peripherally leaded dual (two) incorporated with common power and/or ground
and quad (four) sided devices, peripheral multi-row pins.
53
 Figure 6-1 Family of Bottom Termination Components (BTC)

small-scale electronic applications such as cellular

phones, pagers, and handheld PDAs.

6.1.1.1 In addition to their small package outline and

low profile, the BTC devices have a low
thermal resistance and reduced electrical
parasitic.Board Material
As detailed in Section 5 standard epoxy glass
substrates (FR-4) are compatible with BTC assembly.
Use of a substrate with lower coefficient of thermal
expansion (CTE) can improve reliability. A printed board
can also be affected by factors such as number of metal
layers, laminate material selected, balanced
construction, trace density, operating environment, site
population density, and mounting of components on the
reverse side of the printed board. For specific board
material specifications refer to IPC-4101.

Figure 6-2 QFN Bottom Termination Component 6.1.1.2 Surface finish

Lead-frame Array The surface finish on the printed board is also very
important to proper design of the assembly. There are a
 All contacts are plated with matte tin solder for ease variety of finishes available (see Section 5), and many
of surface mount processing. times a compromise is required in order to meet the
conditions of all the components that are part of the
The bottom termination QFN package family (see assembly. The methodology for the analysis includes
JEDEC MO-220) furnishes enhanced chip speed, the finish on the component package and the
reduced thermal impedance, and, because of its small compatibility with the alloy that has been chosen to
outline, minimizes the printed circuit board area required solder all of the parts into place.
for mounting. The small size and very low profile make
this package ideal for high density PCBs used in
54
6.1.2 Termination Formats 6.1.3.1 PCB Design Guidelines
The SON and QFN device packages are available in The PCB land pattern dimensions required for a design
both Pullback and No-Pullback contact configurations are shown in Figure 6-4. In the figure, the dimensions
and soldering the exposed die attach pad (DAP) to the ZD max and GD min (and ZE max and GE min) are the
PCB optimizes thermal performance. (See Section 4) outside to outside and inside to inside land dimensions,
In the Pullback configuration the standard solder pads respectively. The dimension X and Y indicate the width
are offset from the edge of the package by 0.1 mm. In and the length of the land, respectively. Two additional
the No-Pullback configuration the standard solder pads clearances CLL and CPL are also defined to avoid solder
extend and terminate at the edge of the package as bridging.
compared in Figure 6-3.
While CLL defines the minimum distance between land
The advantage of the No-Pullback design is that the to land for the corner joints on adjacent sides,
end-exposed contact feature offers a more visible solder CPL defines the minimum distance between the inner tip
fillet after board mounting. of the peripheral lands and the outer edge of the
thermal pad. In developing the land pattern for the SON
6.1.3 Mounting Conditions with contact only on two sides, the designer can apply
In order for components to perform at peak level, the same basic rules. See Figure 6-5.
special considerations must be addressed to properly
design the circuit board and to mount the package. For In order to design a proper land pattern, tolerance
example, for enhanced thermal, electrical, and board analysis is required on package and printed board
level performance, the exposed die attach pad (DAP) on dimensions. The 6 I/O package outline example
the package needs to be soldered to the board using a illustrated in Figure 6-5 is typical of the configuration
corresponding thermal pad on the board. Recent data selected for power amplifiers, signal translators and
indicate that this may be important for board reliability load switching functions.
as well. In addition, to assure proper heat conduction
through the board for higher power devices, thermal With contacts only on two sides of the package, the land
vias may be needed in the PCB in the thermal pad pattern and DAP layout is less complex than the quad
region. The PCB assembly design should account for contact variations. The example shown in Figure 6-6 is
the dimensional and manufacturing tolerances of all the land pattern of the 6 I/O devices illustrated in the
elements of the design including the package, PCB, and Figure 6-5.
assembly.
For component tolerances, the profile tolerances usually
There are a number of factors which may impact given in the package outline drawing are converted into
mounting BTC packages on the board and the quality Maximum Material Condition (MMC) and Least Material
of solder joints, These factors include: amount of solder Condition (LMC) based tolerances. The minimum and
paste coverage in thermal pad region, stencil design for maximum values can thus be obtained for various QFN
peripheral and thermal pad region, type of vias, board type packages. In order to determine the land pattern
thickness, lead finish on the package, surface finish on dimensions, three sets of tolerances are involved; one
the board, type of solder paste, and reflow profile. It set for the overall component tolerances, and the other
should be emphasized that these guidelines are offered two sets for the leads on each end. Since it is unrealistic
to help the user in developing the proper printed board to assume that all three tolerances will be at their worse
design and surface mount practices and requirements case, a more realistic RMS (root-mean-square) system
but that characterization of the processes used for is used here as described in IPC-7351. See Figure 6-7.
assembly.

Figure 6-3 Comparing Pullback and No-Pullback Configurations

55
 The dimension between internal component pads,
shown in Figure 6-7 is not normally shown in package
outline drawings. Since this dimension is required to
determine the land pattern length, it is calculated as
follows:

Space between pads [S] min = Amin – 2T1max

Space between pads [S] max = Amin + [S] tol (rms)

Where,

[S]tol (rms) = √(Amax-Amin)2 + 2(T1max-T1min)2

The board tolerance defines the difference between the

MMC and LMC of each land pattern dimension and is
assumed as 0.05 mm in this example. The placement
tolerance is also assumed as 0.05 mm
Diameter of True Position (DTP), given that most
placement machines have placement accuracy between
Figure 6-4 Land Pattern and DAP Land Layout Guide 20 and 70 microns. The minimum values for solder joint
fillets, defined in Figure 6-8, used to calculate the land
pattern dimensions are:

Figure 6-5 Basic Outline Drawing for the 6 I/O SON

56
 the thickness of the lead exposed on the side of the
package, depending on the full lead or lead pull back
options. Since the pad pattern dimension is most likely
to be larger than the nominal lead dimension, solder
joints may assume some angular shape or fillets as
shown in Figure 6-8 for full lead option.

It should be noted that the formation of toe fillets is not

guaranteed unless specific measures are taken (usually
by the BTC supplier) to ensure solder wetting to the
sides of the leads during typical reflow assembly. It is
generally observed, however, that the toe fillets are
formed depending on the type of solder paste used and
length of exposure of package to environment. The toe
fillet, if formed, will improve the solder joint reliability and
allocation must be made for its formation. Although the
toe fillet is not expected to form for the lead pullback
option, the same land pattern as the one for full lead
option can be used for this design. Table 6-1 shows the
target conditions for three variations of land patterns.
Figure 6-6 Recommended Land Pattern for JEDEC 6 I/O
SON Package
6.1.3.2 Land Pattern Design Calculations
With the assumptions and tolerances previously
described, the land pattern dimensions are determined
by using the following relations:

Zmax = Amin + 2JT + TT

Xmax = Wmin + 2JS + TS
Gmin = Smax - 2JH - TH

Where:

TT, TH, and TS are the RMS values of toe, heel and side
tolerance accounting for component, board, and
placement tolerances.

The calculations for these values are defined in more

Figure 6-7 QFN Component and Land Pattern Composite detail in IPC-7351 document. The above calculation for
G min does not account for the leads on all four sides of
the package. In order to include this and to avoid any
solder bridging between the two perpendicular leads on
each corner, a minimum clearance, CLL, is needed. This
clearance is assumed as 0.1 mm and the final value of
G min is determined by using the following constraint:

Gmin ≥ Amax + 2 CLL

Where:

Amax = (Lead Pitch) X (# of leads on one side –1) + Pad

Width
Figure 6-8 Definition of Toe, Heel and Side Fillets Finally, the pad length is determined as:
Y = (Zmax – Gmin)/2
Minimum Toe Fillet = JT min = 0.1 mm
Minimum Heel Fillet = JH min = 0.05 mm Using the above methodology, the perimeter land
Minimum Side Fillet = JS min = 0.0 mm pattern dimensions for various QFN packages with
full-lead option are listed in Table 6-2. It should be noted
The values are selected recognizing that both sides and that the calculated X max dimension (pad width) from
one end of the leads are embedded in the mold the above equations is reduced for 0.4 and 0.5 mm
compound and solder fillets cannot be formed on these pitch devices to avoid any solder bridging issues.
sides. The fourth side, however, has either all or half of
57
 Table 6-1 Quad Flat No Lead Tolerance Goals for Solder Joint Formation
Minimum (Least) Density Median (Nominal) Density Maximum (Most) Density)
Lead Part
Level C Level B Level A
Toe (JT) 0.2 0.3 0.4
Heel (JH) 0 0 0
Side (JS) -0.04 -0.04 -0.04
Round-off factor Round off to the nearest two place decimal, i.e., 1.00, 1.05, 1.10, 1.15
Courtyard excess 0.1 0.25 0.5
Note: The rationale for the relatively large negative heel stems from the tolerances for the lead lengths as also being relatively large.
To maintain a minimum clearance of 0.20 mm to the thermal tab it becomes necessary to trim the heel by -0.2 mm. Without a thermal
tab the heel can usually be increased to as much as 0.50 mm.

The pads may also be rounded on the inner edge. Also, metal dimensions and adjusting the land pattern to
because of rectangular dimension of the package in maintain 0.2 mm minimum metal-to-metal clearance.
most cases, the suffix D and E from dimension Land pattern dimensions are determined initially using
notations in Figure 6-4 (e.g., ZD and ZE) are dropped in the following:
the table and it is implied that Zmax = ZDmax = ZEmax.
Zmax = Amin + 2JT + TT
The Xmax dimension reduced for the 0.4 and 0.5 mm
pitch devices to avoid solder bridging. Refer to Note: Amin is the package external outline minimum
"Exposed Pad Variations" in the Package Outline value. See Figure 6-10.
Drawing for specific D2 and E2 dimensions. D2' should
be equal to Component D2 or D2'TH max above, 6.1.3.5 Thermal Pad Design As noted, BTC devices
whichever is minimum. Analysis of the land pattern are designed with an exposed thermal pad to conduct
geometry requires the consideration of a) component heat away from the package and into the PCB. By
tolerances, b) the PCB tolerances, and c) the accuracy incorporating thermal vias into the PCB thermal pad,
of the equipment used for placing the component. In heat is dissipated more effectively into the inner metal
addition, minimum values of toe, heel, and side fillets layers of the PCB. Depending upon the package pad
must be considered for the formation of reliable solder size, the PCB thermal pad size is modified to avoid
joints. solder bridging between the thermal pad and the
perimeter pads. This is done by defining a minimum
6.1.3.3 PCB Land Pattern Development The PCB land clearance between the outer edges of the thermal pad
pattern for the QFN may be furnished by the component and the inner edges of the perimeter pads. This
manufacturer, guidelines developed by the board minimum clearance is fixed at 0.2 mm.
assembler, or by following an industry standard such as
IPC-7351. Because of exposed thermal paddle and the The number of thermal vias incorporated into the design
package perimeter pads on the bottom side of the will depend on the power dissipation and electrical
package, constraints should be added to the IPC requirements of the specific application. There is a point
methodology. of diminishing returns where additional thermal vias may
not significantly improve the performance of the
The tolerance analysis requires the consideration of: package. This is shown in Figure 6-11 where the effect
of number of vias is plotted for 7 mm x 7 mm, 48-lead
 Component tolerances packages.
 PCB tolerances
 Accuracy of the equipment used for placing the A via diameter of 0.3 mm is used for this simulation. As
component the via pitch decreases, more vias can be incorporated
for the same thermal pad size; however, the incremental
The PCB land pattern for the BTC defined in Figure 6-9. performance improvement reduces. Thermal vias are
necessary because they conduct heat from the exposed
The thermal land is a metal (normally copper) region pad of the package to the ground plane. The number of
centrally located under the package and on top of the vias is application specific and is dependent upon
PCB. It has a rectangular or square shape and should electrical requirements and power dissipation. The
match the dimensions of the exposed DAP on the thermal performance of a package may be improved by
bottom of the package (1:1 ratio). The legend for the
mechanical dimensions referenced in Figure 6-9 is
furnished in Table 6-3.

6.1.3.4 Land Pattern Design Adjustment To ensure a

robust design and to minimize any possibility of solder
bridging during board assembly, a minimum
metal-to-metal clearance of 0.2 mm is required.
Therefore, a final adjustment to the land pattern is made
by overlaying the package outline with the maximum

58
 Table 6-2 Package and Land Pattern (Pullback and No-Pullback) Dimensions

increasing the number of vias. Figure 6-12 shows the via hole diameter. The solder mask thickness should be
effect for a 36 I/O BTC with a 9 x 9 mm body and 7 x7 the same across the entire PCB.
mm pad.
Two via diameters illustrated are 0.2 mm and 0.33 mm.
The via diameter should be 0.2 mm to 0.33 mm with 1 Different patterns are also shown to depict possible
oz. copper via barrel plating. It is important to plug the layouts for specific numbers of vias. Two die sizes are
via to avoid any solder wicking inside the via during the shown in this example, 2.1 mm x 2.1 mm and 6.4 mm x
soldering process. The thermal vias can be tented with 6.4 mm. For a given number of vias, placing the vias
solder mask on the top surface of the PCB. The solder toward the periphery of the pad provides up to 5%
mask diameter should be at least 75 μ larger than the improvement over centrally placed vias. There is
59
 Figure 6-9 Comparing pull back to no-pull back package outline and land pattern thermal land layout

diminishing improvement, however, as the number of than the solder masking process, NSMD is preferred
vias increases. over SMD. The solder mask opening on NSMD pads is
larger than the copper pads to allow the solder to
6.1.3.6 Solder Mask Design Two types of land patterns adhere to the sides of the copper pad, improving
are used for surface mount packages: ‘Non-Solder reliability of the solder joints.
Mask Defined’ lands (NSMD) and ‘Solder Mask Defined’
lands (SMD). NSMD has an opening that is slightly The recommended solder mask opening should be 120
larger than the land geometry, while the SMD land μm to 150 μm larger than the copper land size to allow
surface is defined by a solder mask opening that is for solder mask registration tolerances, typically
smaller than the metal land geometry. Figure 6-13 between 50 μm to 65 μm. The solder mask web must be
illustrates the two different types of solder mask to land a minimum of 75 μ in width to adhere to the PCB
pattern geometry. surface. This constraint allows each land pad to be
individually masked for lead pitches of 0.5 mm and
Because the copper etching process has tighter control higher. However, for 0.4 mm pitch parts with PCB pad

60
 Table 6-3 Legend for Basic Mechanical Attributes microns smaller than the thermal land size on all four
sides. This will guarantee 25 μ solder mask overlap
Dimensions A, B, C, D, and E of PCB are 1:1 ratio with
even for the worse case mis-registration.
package pad dimensions.For specific detailed package
dimensions, refer to respective marketing outlines.
6.1.4 Package Tolerances
Terminal Pitch A The JEDEC design guideline standard for QFN package
Terminal Width B family detailed in Section 4 applies to packages with
Terminal Length C optional thermal enhancements as well as various
Exposed DAP Width D height profiles and pitches. This package has terminals
Exposed DAP Length E on all four edges of the bottom surface of the package.
Thermal Via Diameter. Recommended A BTC may have either square or rectangular body
V1 outline as well as either symmetric or asymmetric
0.2 – 0.33 mm
Thermal Via Pitch. Recommended 1.27 mm V2 terminal patterns. Versions of the package may also
Source: National Semiconductor have terminals placed in the corners at 45 to
neighboring leads. The basic dimensions for the
package outline are in increments of 0.50 mm ranging
from 1.00 mm through 12.00 mm. See Figure 6-15.

The outline detail shown in Figure 6-15 illustrates the

primary package outline dimensions used when
developing the land pattern and thermal pad geometries.
The width of the metallized terminals (including lead
finish) exposed at the bottom surface of the package
are detailed in Table 6-4.

The component tolerances and profile tolerances

usually given in the package outline drawings are
converted into maximum material condition (MMC) and
least material condition (LMC) based tolerances.
Figure 6-10 SON 0.5 mm Pitch, 6 Pin with Thermal Tab
6.1.4.1 Circuit Routing, Thermal Pad and Via Design
For best performance, all circuit traces should be as
short as possible. To be most effective, the input and
output capacitors should be placed close to the BTC
device to minimize parasitic trace inductance. Using
wide conductors for V-IN, V-OUT and GND will help
minimize parasitic electrical effects along with
enhancing the thermal transfer between the case and
the ambient environment.

Additional good practices are:

 Dedicate an internal power plane to spread the
heat and optimize thermal dissipation.
 Make the heat sink plane within the circuit board
as large as possible to minimize board and die
Figure 6-11 DAP to PCB Interface Example temperature.
 Use conductive copper plated vias to make the
electrical and thermal tie to the heat sink plane.
width of 0.25 mm, not enough space is available for
solder mask web in between the pads. It is
As stated, the SON and QFN package is designed to
recommended to use a trench type solder mask
provide a superior thermal performance. This is partly
opening where a big opening is designed around all
achieved by incorporating an exposed die paddle on the
pads on each side of the package with no solder mask
bottom surface of the package. However, in order to
in between the pads, as shown in Figure 6-14.
take full advantage of this feature, the PCB must have
features to effectively conduct heat away from the
It is better to round the inner edge of the solder mask,
package. This can be achieved by incorporating thermal
especially for corner leads, to allow for enough solder
pad and thermal vias on the PCB.
mask web in the corner area. For the cases where
thermal land dimension is close to the theoretical
maximum, it is recommended that the thermal pad area
should be solder mask defined in order to avoid any
solder bridging between the thermal pad and the
perimeter pads. The mask opening should be 100
61
Figure 6-12 The affect of θJA vs. number, distribution and diameter of thermal vias and die sizes for a 36 I/O QFN with a 9 x 9
mm body and 7x7 mm thermal land

Figure 6-13 Comparing Optional Solder Mask Variations

While a thermal pad provides a solderable surface on

the top surface of the PCB (to solder the package die
pad on the board), thermal vias are needed to achieve a
suitable thermal path to inner and/or bottom layers of
the PCB to remove the heat.

Generally, the size of the thermal pad on the PCB

should match the exposed die paddle feature provided
on the device. However, depending upon the die paddle
size, this size needs to be modified in some cases to
avoid solder bridging between thermal pad and the
perimeter pads. This is done by defining a clearance
between the outer edges of the thermal pad and the
inner edges of perimeter pads. It should be noted that
Figure 6-14 Solder Mask for (A) Perimeter Lands for 0.5 the D2′TH dimension gives the theoretical maximum
mm and Higher Pitch Parts, and (B) for 0.4 mm Pitch Parts value. Since the size of the exposed die paddle on the
component may actually be much smaller than this
62
 Figure 6-15 Representative BTC Outline Detail
Figure 6-16 where the effect of number of vias plotted
Table 6-4 Contact Pitch and Width Variations for 7 mm x 7 mm, 48 contact package. A via diameter of
Contact Terminal Dimension 0.3 mm was used for this simulation. As the via pitch
Pitch decreases more vias can be incorporated for the same
Minimal Nominal Maximum thermal pad size but the incremental performance
0.65 0.25 0.3 0.35 improvement diminishes.
0.5 0.18 0.25 0.3 With this constraint, the maximum size of the thermal
0.4 0.15 0.2 0.25 pad is calculated by the following relationship and is
listed under the graph in figure 6-16 for various package
value, the actual D2′ dimension should be modified by sizes. Based on this and similar thermal simulations, it
Component D2 ≤ D2′ ≤ D2′TH max Note: QFN with is recommended that an array of thermal vias should be
down-bond ring design does not require the ring to be incorporated at 1.0 mm to 1.2 mm pitch with via
soldered to the board. The thermal pad design on the diameter of 0.3 mm to 0.33 mm. Representative of
board should be based on the exposed paddle area, these arrays are shown in Figure 6-17 for 7x7 mm, 48
excluding the ring area. lead and 10x10 mm, 68 lead packages.

In order to effectively transfer heat from the top metal 6.1.4.2 Standard Grids
layer of the PCB to the inner or bottom layers, thermal Standard grids offer the potential for significant
vias need to be incorporated into the thermal pad improvement in routing and BTC components are key.
design. The number of thermal vias will depend on the
application and power dissipation and electrical The industry is presently compelled to deal with legacy
requirements. Although more thermal vias improve the component lead pitches because of the long established
package thermal performance, there is a point of precedent. The now registered and accepted range of
diminishing returns as additional thermal vias may not options include: 0.100” (2.54 mm) which was the
significantly improve the performance. This is shown in original single de facto standard for IC components.

Figure 6-16 Effect of Number of Thermal Via on Package Thermal Performance

63
 moreover, such requirements actually reduce circuit
performance. See Figure 6-18.

Figure 6-17 PCB Thermal Pad and Via Array for 7x7 mm,
48 lead and 10x10 mm, 68 Lead Packages

It has the advantage of allowing the designer to lay out

his entire design using that value as a fundamental pitch. Figure 6-18 Comparison of the 80% rule with Standard
The first full metric pitch of 1.0 mm was established, Grid Systems for Routing Improvement
from this point on the “80% Rule” has been in effect.
The component pitches for IC packages that followed in BTC area array components based on the “80% Rule”,
service of the new convention were 0.8 mm, 0.65 mm, increase routing complexity requiring more
0.5 mm, 0.4 mm and 0.3 mm. sophisticated routing tools. Note that only 2 of the 5 grid
pitches derived from the concept have the ability to
The key thing to remember is that the “80% Rule” has conform to a common grid based on the smallest
been applied regardless of the component lead defined lead pitch for component I/O (in this case 0.5
configuration, be it two sided, four sided or area array. mm). In contrast, on the right side of Figure 6-18 can be
The effect, is illustrated in Figure 6-18. As can be seen seen a number of components based on the use of a
in the graphic on the left, following the de facto 80% rule common grid pitch where it can be seen that every
leads to greatly increase routing complexity as only 2 of component lead falls on grid allowing for high efficiency
the 5 grid pitches derived from the concept have ability “Manhattan routing” of circuits.
to conform to a common grid based on the smallest
defined lead pitch for component I/O (in this case 0.5 6.1.5 Attachment Techniques
mm which is the accepted lower limit for effective Because of the small metal pad termination surface
soldering). This might seem a trivial concern but it has area and the sole reliance on printed solder paste on
far reaching impact in design. the PCB surface, care must be taken to form reliable
solder joints for BTC packages. This is further
If components of varying grid pitch are used in the complicated by the large thermal pad underneath the
assembly as seen on the left side of the figure, the package and its proximity to the inner edges of the
routing of interconnections will be more complex and leads. Although the pad pattern design suggested
more sophisticated routing tools are required and, more above might help in eliminating some of the surface
importantly more layers as well. In contrast, on the right mounting problems, special considerations are needed
side can be seen the same number of components with in stencil design and paste printing for both perimeter
placement based on the use of a common grid pitch and and thermal pads. Since surface mount processes vary
wherein it can be seen that every component lead falls from company to company, careful process
on grid. “Manhattan routing” is the term frequently used development is recommended.
for electronic circuits using the principals of base grid,
street and avenue routing. This has a number of 6.1.5.1 Stencil Design for Perimeter Pads
compelling benefits. Though it is not commonly their responsibility, the
designer of the PCB should understand stencil design
For example, there is potential for much improved requirements. In general, the optimum and reliable
routability as the streets and avenues used for routing solder joints on the perimeter pads should have about
channels are perfectly defined making the routing much 50 μm to 75 μm standoff height and desirably, a fillet on
easier and faster. No less important is all of the circuit the outside terminal ends if possible. A solder joint with
board real estate which can be potentially returned to good standoff height but no fillet, or minimal fillet at the
use for components. Clearly, the mixture of peripheral terminal end, should still provide a reliable interface for
and area array leads of various lead pitches results in a most applications. The first step in achieving good
much more complex circuit routing challenge and standoff is the solder paste stencil design for perimeter
necessitates the distancing of components and addition pads. The stencil aperture opening should be so
of many more circuit layers than would normally be designed that maximum paste release is achieved. This
required to accommodate the redistribution wiring is typically accomplished by considering the following
required to make all of the required connections, two ratios:

64
1. Area Ratio = Area of Aperture Opening/Aperture
Wall Area; and 6.1.5.3 Via types and solder voiding
2. Aspect Ratio = Aperture width/ Stencil Thickness Voids within solder joints can have an adverse effect on
high speed and RF applications as well as on thermal
For rectangular aperture openings, as required for this performance. As the typical BTC package incorporates
package, these ratios are given as Area Ratio = a large center pad, controlling solder voiding within this
LW/2T(L+W), and Aspect Ratio = W/T Where L and W region can be difficult. Voids within this center plane can
are the aperture length and width, and T is stencil increase the current path of the circuit. The maximum
thickness. For optimum paste release the area and size for a void should be less than the via pitch within
aspect ratios should be greater than 0.66 and 1.5 the plane. This recommendation would assure that any
respectively. It is recommended that the stencil aperture one via would not be rendered ineffectual based on any
should be 1:1 to PCB land sizes as both area and one void increasing the current path beyond the
aspect ratio targets are easily achieved by this aperture. distance to the next available via.
The opening can be reduced for the lead pullback
option because of reduction of solderable area on the The presence of small voids in the thermal pad region is
package. The stencil should be laser cut and electro not likely to result in degradation of thermal and
polished. The polishing helps in smoothing the stencil electrical performance. The specific thermal simulation
walls which results in better paste release. It is also shown in Figure 6-21 indicates that combining smaller
recommended that the stencil aperture tolerances multiple voids up to 50% of the thermal pad area, does
should be tightly controlled, especially for 0.4 mm and not result in a loss in thermal performance. It should
0.5 mm pitch devices, as these tolerances can also be noted that the voids in thermal pad region do
effectively reduce the aperture size. More detailed not impact the reliability of perimeter solder joints.
information for stencil development is available in
IPC-7525. Large voids in thermal pad area should be avoided. In
order to control these voids, via filling may be required.
6.1.5.2 Stencil Design for Thermal Pad Filling the via holes, located in the DAP area, will
In order to effectively remove the heat from the package prevent solder from wicking inside the via during the
and to enhance electrical performance the die pad reflow solder process. There are different methods
needs to be soldered to the PCB thermal pad. For larger employed within the industry for this purpose: “via
thermal pad geometry it is recommended that the stencil tenting” (from top or bottom side) using dry film solder
be designed to provide smaller multiple openings. This mask, “via plugging” with liquid photo-imageable (LPI)
will typically result in 50 to 80% solder paste coverage.

Figure 6019 Effect of Voids on Thermal Performance

65
solder mask from the bottom side, “via encroaching”, or
“via capping”. Via filling is discussed more in 5.4.4.2. 6.1.5.4 Solder Joint Standoff Height and Fillet
Formation
All of these options have pros and cons when mounting The design should facilitate the creation of a suitable
QFN package on the board. While via tenting solder joint standoff. Solder joint standoff is a direct
from top side may result in smaller voids, the presence function of amount of paste coverage on the thermal
of solder mask on the top side of the board may pad and the type of vias used for BTCs with an exposed
hinder proper paste printing. On the other hand, both via pad at the bottom. It is worthwhile for the designer to
tenting from bottom or via plugging from know, that board mounting studies have shown that the
bottom may result in larger voids due to out-gassing, package standoff increases by increasing the paste
covering more than two vias. Finally, encroached coverage and by using plugged vias in the thermal pad
vias allow the solder to wick inside the vias and reduce region.
the size of the voids. However, it also results in
lower standoff of the package, which is controlled by the The standoff height varies by the amount of solder that
solder underneath the exposed pad. Figure 6- wets or flows into the PTH via. The encroached via
22 shows representative X-ray pictures of QFN provides an easy path for solder to flow into the PTH
packages mounted on boards with different via and decreases package standoff height while the
treatments. In case of via tenting, the solder mask plugged via impedes the flow of solder into the via due
diameter should be 100 μm larger than via diameter. to the plugged via’s closed barrel end. In addition, the
number of vias and their finished hole size will also
Encroached via, depending on the board thickness and influence the standoff height for encroached via design.
amount of solder printed underneath the exposed pad, The standoff height is also affected by the type and
can result in solder protruding from the other side of the reactivity of solder paste used during assembly, PCB
board. It should be noted that the vias are not thickness and surface finish, and reflow profile. To
completely filled with solder, suggesting that solder wets achieve the preferred 50 μm thick solder joints it is
down the via walls until the ends are plugged. This recommended that that the solder paste coverage be at
protrusion is a function of PCB thickness, amount of least 50% for plugged vias and 75% for encroached via
paste coverage in the thermal pad region, and the types.
surface finish of the PCB. Manufacturers note that this
protrusion can be avoided by using lower volume of The peripheral solder joint fillets formation is also driven
solder paste and reflow peak temperature of less than by multiple factors. Due to the singulation process
215°C in the case of SnPb soldering. during package assembly, a majority of the commercial
non-pullback BTC devices are furnished with uncoated
Via filling and capping is a good option to prevent the copper on the exposed terminal ends. The resulting
issues with tenting, flooding, and encroach vias though bare copper on these surfaces will oxidize and may
it does require a secondary process. It is important to compromise solder wetting during typical reflow
ensure that the capping process produces minimal assembly process, especially if the packages are not
depressions in the pad (<0.002”). By accepting larger stored in a controlled environment. Additional measures
depressions, air/gas entrapment within the depression would need to be taken by suppliers to coat or plate
may create voids that bridge between vias.

Figure 6-22 X-ray Example Showing Voids in the Thermal Pad

66
 Figure 6-23 Solder Protrusion from the Bottom Side Of PCB for Encroached Vias

exposed copper terminal ends to ensure solder wetting. warpage and uneven solder surface. When using
It is, however, possible that a solder fillet will be formed immersion tin, some concern should be considered due
depending on the solder paste (flux) used and the level to solderability and health concerns.
of oxidation.
For an (ENIG) electroless nickel immersion gold finish,
The fillet formation is also a function of PCB land size, the gold thickness should range from 0.05 μm to
printed solder volume, and the package standoff height. 0.20 μm to avoid solder joint gold embrittlement. ENIG
The land size concepts for toe and heel fillets, along is a good choice but has black pad concerns however
with 1:1 aperture, will provide sufficient solder for fillet the concern is generally for PCBs when using BGAs.
formation if the package standoff is not excessive. Since Black pad is less of a concern with BTCs.
there is only limited solder available, higher
standoff—controlled by paste coverage on the thermal Using a PCB with Organic Solderability Preservative
pad—may not leave enough solder for fillet formation. coating (OSP) finish is also recommended, as an
Conversely, if the standoff is too low, large convex alternative to Ni-Au. A high temperature OSP must be
shape fillets may form. utilized if performing a lead-free soldering process.
OSPs may not survive multiple reflow processes such
When solder wetting to the exposed terminal ends of as for double sided assemblies. OSP is a good choice
the BTC leads does occur, solder fillets will form along (lower cost) but multiple reflow or hole-fill in wave are
the BTC perimeter, especially when these parts are some of the key concerns in OSP. High temp OSPs are
mounted on the PCB with a protruding land pattern and available to address these concerns but they do add to
1:1 stencil aperture for peripheral located land patterns. the cost.
Since center land coverage and via type were shown to
have the greatest impact on standoff height, the volume Immersion silver is acceptable as a flat surface but
of solder necessary to create optimum fillet varies. other issues such as champagne voiding and caving
from inadequate plating processes are concerns and
If protrusion of the solder through thermal vias cannot must be addressed. Also, immersion silver shelf life is
be avoided, the components may have to be assembled limited and this plating type will tarnish if not protected
on the top side (or final pass) assembly, as the and may not be suitable for assemblies requiring
protruded solder will impede acceptable solder paste multiple reflows. Immersion Silver addresses most of
printing on the other side of the PCB. See Figure 6-23. the issues in OSP but planar microvoids, creeping
corrosion and tarnishing in salty and sulfur
7 ASSEMBLY OF BTCs ON PRINTED BOARDS environments are a concern.

The assembly processes for attaching BTCs requires For a PCB with Hot Air Solder Leveling (HASL) finish,
careful process development and control. the surface flatness should be understood and
Process defect rates can be significantly reduced: monitored to ensure uniform solder connections across
however good process control is a necessity. the BTC.

7.1 PCB Surface Finish Requirements Since all surface finishes of some concerns, it may be
wise to consider two finishes: OSP for single sided;
A uniform PCB plating thickness is key for high ENIG and immersion silver for double sided and mixed
assembly yield. There is no perfect surface finish. All (SMT and Through Hole) boards. Use of nitrogen in
finishes have some issues. Even lead-free HASL is reflow and wave will allow additional flexibility in using
being reconsidered by some despite board OSP but one can get away without nitrogen with ENIG
67
even when using no clean flux. Use of aggressive flux connection is made between the device pad and the
allows additional flexibility. When using aggressive flux, board land. Also, it is recommended for pull-back
OSP can be used even without nitrogen. So it is packages that the board land extend beyond the outer
important to keep in mind that use of nitrogen, type of edge of the device package to allow visual access for
flux, reliability concerns and cost sensitivity play a inspection of solder joint flow.
critical role selection of surface finish. See Section 5.
7.2.1 Consideration for Soldering Process
For more information on surface finishes, see IPC-2221 Because of the small terminal pad surface area and the
& IPC-6012. sole reliance on printed solder paste on the
PCB surface, care must be taken to form reliable solder
7.2 PCB Design joints for BTC packages. This is further complicated by
Proper land pattern design is critical for maintaining high the large thermal pad underneath some BTC packages
yields and good reliability of BTC solder joints. and its proximity to the inner edges of the leads.
Figure 7-1 shows examples of good BTC land patterns; Although the land pattern design might help in
Figure 7-2 shows examples of poor land patterns for eliminating some of the surface mounting problems,
BTC type parts. special considerations are needed in stencil design and
paste printing for both perimeter and thermal pads.
The solder pad on the device should be aligned with the Since surface mount processes vary from company to
lands on the board such that a complete solder

Figure 7-1 Example of Good Land Patterns for Bottom Termination Components

Figure 7-2 Example of Poor Land Patterns for Bottom Termination Components

68
company, careful process development is solder paste to connect the BTC terminations to the
recommended. lands on the board. Solder paste can be applied to the
lands using several methods including screen or stencil
7.2.2 Component Preconditioning Bake printing and dispensing or jetting.
BTCs shipped in moisture barrier bags require special
handling to insure proper surface mount conditions are Solder paste consists of a homogeneous mixture of
met. The moisture barrier bag will be labeled with the metal powder particles and flux. The metal content
proper instructions concerning the correct handling of (typically 90% by weight) in the solder paste determines
the BTCs. BTCs exposed to room temperature and the amount of solid alloy in the solder joint. Metal
humidity conditions beyond the cumulative time powder particles are generally spherical in shape. A
specified on the label must be baked prior to surface uniform powder shape aids the printing or dispensing
mount reflow. The BTC size, thickness and MSL process and it decreases the surface area, which
determine the bake times and conditions. Industry minimizes oxidation.
standard bodies such as JEDEC publish tables with
bake times and temperatures. J-STD-033 should be Flux, solvent and jelling agent makes up the remainder
followed to prevent damaging the BTC devices. of the solder paste volume. The activators in the flux
remove oxides from the solder particles, the land
7.2.3 Component Preparation for Assembly patterns, and the BTC termination surfaces to promote
Component solder dipping is not recommended for BTC good solderability during the reflow process. The
terminal surface preparation. Dip soldering will not solvents have an important role in controlling the
maintain coplanarity and makes the BTC unproducible tackiness of the paste and affecting the rheological
during assembly. Inconsistent solder on the thermal properties. The formation of voids in the BTC
plane can raise the BTC and cause the signal solder joint may be related to the solvents in the solder
terminations to not make contact during reflow creating paste. Solvents with low boiling points and/or
solder opens. Non uniform solder volume on the signal improper reflow parameters can increase the incidence
terminations can also create a non contact condition of voids in BTC solder joints.
resulting in solder opens in random locations. See
Figure 7-3. For successful fine pitch BTC printing, the solder paste
must pass through very small apertures in the stencil.
Land pattern and thermal pad geometry on the PCB The solder paste needs to remain printable and tacky
must be sized and aligned to ensure uncompromised for an extended period of time, and it must maintain
electrical and mechanical interface with the BTC device. print definition prior to and during reflow. Solder paste
The example shown in Figure 7-4 illustrates the viscosity, particle size and stencil life are critical
potential for compromising the solder interface between parameters for solder paste application.
surfaces.
Solder paste dispensing is not as widely used as
7.2.4 Solder Paste and its Application printing due to a reduction in throughput speed;
The quality of the paste print is a critical factor in however, selective dispensing allows for more flexible
producing high yield reliable assemblies that use BTC paste volume deposition and placement for tighter
technology. The surface mount assembly process uses

Figure 7-3 Comparison of Solder Dipped and a Non Solder-dipped BTC and Resultant No Solder Condition
69
 Figure 7-4 Undersized PCB pads resulting in potential areas where pure tin finish has not mixed with SnPb solder paste
processing. Stencils are usually made of stainless steel
process control. A technology referred to as solder or electroformed nickel. Apertures
paste “jetting” has greatly increased solder deposition should be trapezoidal to ensure uniform release of the
speed while still allowing for the flexibility of volume and solder paste to reduce smearing. The solder
placement accuracy. The jetting technology, however, joint thickness for the attachment of BTCs should
requires specific solder paste formulations which may typically be 50 μm to 75 μm after reflow.
have limited wide industry acceptance. Future
refinements in the equipment and dispensing methods Aperture modifications:
could make this technology more viable and desirable
as a way of maintaining tighter process control.  Specify ≤0.6 mm radius to inside corners of all
apertures
7.2.4.1 Particle Size and Paste Selection  Reduce all 0.8 mm pitch and finer aperture widths to
A Type 3 or 4, low residue, no-clean solder paste 50% of pitch
(Sn63/Pb37 or 96.5Sn/3.0Ag/0.5Cu) is commonly used  Segment BTC thermal pad apertures to reduce
in mounting BTC packages; however, water soluble flux printed solder volume by 50% or as specified by the
materials are also widely used. Solder paste manufacturer’s recommendation
composition is often a compromise given the variety of
components which must be placed on a PCB, and Note: Segmented solder paste deposits may not be required
special SMT specific solder pastes are being marketed on some components. Apertures with a dimension greater
by solder paste vendors that minimize voiding in the than 5.0 mm (0.200) are broken into multiple apertures.
solder joint. The solder particle size is classified by
J-STD-005 (see Table 7-1). Stencil thickness:

Table 7-1 Particle Size Comparisons It is recommended to use a 1.25 mm (0.005”) stencil
Maximum thickness for 0.5 mm (0.020”) pitch or smaller and a
Solder
Mesh particle 1.5 mm (0.006”) stencil thickness for larger pitches. The
paste type
size [m] stencil may require stepped areas to allow for both
Type 2 -200/+325 80 small pitches and larger pitches on the same board.
Typical BTC arrays and passive components as small
Type 3 -325/+500 50 as 0402 and 0201 may also require a 1.25 mm thick
Type 4 -400/+500 40 stencil.
Type 5 -500 30 The stencil thicknesses should all be considered as
recommendations for a Laser Cut stencil. A
7.2.4.2 Stencil Thickness and Aperture Design checkerboard pattern should be used on large thermal
The formation of reliable solder joints is a necessity. pads. Thickness of the stencil (C) is usually in the 100
The large numbers of terminal contacts on some μm to 150 μm (0.004" to 0.006") range. The actual
BTC type parts can present a challenge in producing a thickness of a stencil is dependent on other surface
uniform solder print thickness. To this end, mount devices on the PCB. A squeegee durometer of
careful consideration must be applied to the stencil 95 or harder or a metal squeegee should be used to
design. The stencil thickness, as well as the etched distribute the paste. The blade angle, pressure, and
pattern geometry, determines the precise volume of speed must be fine-tuned to ensure even paste transfer.
solder paste deposited onto the device land An inspection of the stenciled board is recommended
pattern. Stencil alignment accuracy and consistent before placing parts; as proper stencil application is the
solder volume transfer is critical for uniform reflowsolder most important factor with regards to reflow yields later
in the process. See Figure 7-5.

70
In order to effectively remove the heat from the package process details are critical in conjunction with careful
and to enhance electrical performance the die stencil design to ensure maximum yield and minimum
paddle needs to be soldered to the PCB thermal pad. If failure rates. It is important to find out what printing
the solder paste coverage is too large, it is techniques are used at any assembly facility where the
recommended that smaller multiple openings in stencil BTC will be installed. Each of these sites should be able
be used instead of one big opening for printing to provide recommendations for stencil design
solder paste on the thermal pad region. This will limitations.
typically result in 50 to 80% solder paste coverage.
Some examples of different stencil configurations are Another commonly used ratio is called area ratio. An
shown in Figure 7-6 describing ways to achieve area ratio of greater than 0.66 is recommended for laser
an appropriate level of coverage. cut foils. The formula to calculate area ratio is the area
of the stencil aperture divided by the area of the stencil
7.2.4.3 Importance of Paste Volume aperture walls. Area of aperture divided by area of
It is very important to design a stencil aperture that will aperture walls = L*W/2*(L+W)*T >0.66.
provide good paste release. In order to ensure good
paste release, an aspect ratio of 1.5 minimum is The stencil aperture opening should be designed such
recommended for laser cut foils. Aspect ratio is the ratio that maximum paste release is
between stencil aperture width and stencil thickness. achieved. This is typically accomplished by considering
The aspect ratio relates to the manufacture of stencils the following 2 ratios and Figure 7-7.
and the solder paste stencil aperture and/or thickness
and may need to be modified to maintain acceptable Area Ratio= LW / 2T (L + W)
aspect ratio. Aspect Ratio = W/T
Where “L” and “W” are the aperture length and “T” is the
Using thicker stencils may increase the probability of stencil thickness
balling and bridging, while compensating for the
increased thickness with a reduction in aperture size
diminishes the release efficiency, leading to less
predictable printed volume. Using thinner stencils
necessitates the use of a 1:1 aperture to feature ratio
which increases the chances of even minor
misalignment causing balling, while any reduction in the
Note: If the apertures are different than described
aperture to feature ratio or less than perfect release above, then recalculate the area ratio. But for simplicity,
threatens insufficient volume, starved or open joints,
the previous equation may be used and will result in a
and may lead to poor mechanical strength.
slightly conservative number.
Regardless of the stencil features, proper care must be
Use of electroform stencils can yield success with area
given to the printing process at the assembler’s facility
ratios of <0.6. IPC-7525 Stencil Design Guidelines
and are best handled by qualified technical staff. The contains more information on other stencil design rules.
preparation, paste rheology, handling time, standoff
distance, blade hardness and speed, and re-flow

Figure 7-5 Recommended Aperture Dimensions for Commonly Used Stencil Thicknesses

71
 Figure 7-6 Thermal pad stencil designs for 7x7 mm and 10x10 mm BTC devices

and process dependent. Slightly misaligned parts (less

than 25 percent off the land center) will automatically
self-align during reflow (see Figure 7-8). Grossly
misaligned packages (greater than 50% percent off land
and pad centers) should be removed prior to reflow as
they may develop electrical shorts, as a result of solder
bridges during reflow solder processing.

7.2.5.1 Vision Systems for Placement Accuracy

Placement accuracy is a very critical part of the BTC
process. It is strongly recommended to not move a BTC
Figure 7-7 Solder Stencil Aperture Wall Area after machine placement to correct placement problems
as this may cause solder bridging in adjacent solder
In addition to the variable constraints in stencil thickness
joints, since the connections cannot be seen visually.
and aperture design to balance volume and proper
The placement machine's accuracy is largely dependent
release, gold embrittlement is an issue with some BTC
on the vision system and the ability of the nozzle to hold
components that have a gold finish (more so when also
the component. Matching the vision system to the
combined with an ENIG finish PCB). In order to get
application is also important. The vision system
enough volume to mitigate embrittlement, there may be
determines the X, Y and theta offset of each component
situations where thicker stencils or overprinting may be
prior to placement. In addition to determining the
considered. However, these methods for applying
component offset, the vision system can also inspect
solder can lead to issues with solder paste release and
the component for dimensional integrity.
bridging.
Charge-Coupled Device (CCD) camera-based systems
employ two lighting methods, referred to as binary and
7.2.5 Component Placement Impact
gray scale. Both methods can be sensitive to contrast
The pick and place accuracy governs the package
and lighting chang
placement and rotational alignment. This is equipment

Figure 7-8 Assessing Maximum Pre-reflow Off-land Acceptance

72
There are two popular methods for package alignment
using machine vision: package silhouette, where the Placement machine nozzle designs vary from supplier
vision system locates the package outline; and terminal to supplier. It is important that the correct nozzle is
recognition, where the vision system locates the chosen which will have sufficient surface area to hold
terminals or leads of the package. Some vision systems the part without any shifting during the placement
can directly locate on the pad metallization pattern. Both process. The nozzle must gasket against the part, not
methods are acceptable for BTC placement. The allowing vacuum leakage. Tactile sensing, which helps
terminal recognition type alignment tends to be more control the Z axis (vertical) stroke of the spindle, is
accurate, but is also slower since more complex vision desirable because it prevents a component from being
processing is required of the pick and place machine. crushed between the vacuum nozzle and the substrate.
The package silhouette method allows the pick and
place system to run faster, but is generally less accurate. Also, without leads or balls to act as a hard stop or
Both methods are acceptable, and have been standoff, extra care must be taken to limit the Z axis
successfully demonstrated by major pick and place pressure of the part into the solder paste, which can
equipment vendors and contract PCB assembly houses. result in solder shorts.

Depending upon the type of pick and place system, a 7.2.6 Reflow Soldering and Profiling
change in package carrier format may be required. As with all SMT components, it is important that profiles
Local fiducials may also be helpful in helping the vision be monitored on all new board designs. In addition, if
systems recognize the exact location of the land pattern there are multiple package types on the board, the
for the BTC, similar to what is used for fine-pitch thermal profile should be measured at multiple locations.
peripheral leaded parts. Gray scale systems use front Component temperatures may vary because of
lighting, which illuminates the component from below. surrounding components, location of the device on the
Surface features are reflected into the CCD camera for board, and package densities. To maximize the
processing. Binary systems use back lighting, which self-alignment effect of a BTC (see Figure 7-9), it is
illuminates the component from above. The outline of recommended that the maximum reflow temperature
the component is projected into the CCD camera for specified for the solder paste not be exceeded. A good
processing. Binary imaging, which is the older of the two guide is to subject the PCB to a temperature ramp not
methods, locates a feature using the contrast between exceeding 4°C per second. The reflow profile guidelines
black and white images. Gray scale systems can are based on the temperature at the actual solder pad
usually interpret 256 levels of contrast. Both systems to PCB land pad solder joint location.
use an algorithm to determine the center of the
component. Binary imaging requires less computing The actual temperature at the solder joint is often
capability than gray scale imaging. different than the temperature settings in the reflow
system due to the location of the system thermocouple
Gray scale imaging places BTC components based on placement. The reflow system needs to be profiled
land location while binary imaging places BTC using thermocouples at various locations on the PC
components based on the component outline. In some board. Thermocouples should be placed on one of the
cases the tolerance between the BTC outline and the largest as well as the smallest components on the PCB.
location of the printed board lands is significant. It is suggested that the peak temperature differential
between the smallest and largest package be 10°C or
Gray scale imaging is more desirable for placing BTC less for average size PC boards.
components because it eliminates placement error due
to variations in the component outline.

Figure 7-9 Metal Defined Land Solder Joint

73
See J-STD-020 for reflow recommendations. BTCs are
typically moisture sensitive and fall into level From Table 7-2, it is important to note that the sample
classifications defined by JEDEC. Specific levels are BTC only achieves a maximum temperature of 240°C
stated on moisture sensitive labels shipped with BTC even though the oven temperature is set to 260°C. This
devices. Commercial BTC devices may be compatible is consistent with the reflow requirements of 250°C
with SnPb and/or lead-free solder processing and the maximum for the BTC body temperature. Analyses of
supplier is responsible for defining the maximum reflow the solder joint obtained from this profile indicated
profile limit (e.g., 215-245°C peak body temperature). excellent joint formation. Table 7-3 shows the profile
See IPC-1756. variation between a tin/lead profile and those used for
lead-free SAC alloys.
7.2.6.1 Example of Thermal Profile Development
Solder paste is applied and a sample BTC is mounted 7.2.6.2 Unique Profile for Each Printed Board
on a specific board intended to be assembled using a Assembly
lead-free solder paste. The board was a four layer There is some misunderstanding by some people that
multilayer board, 1.5 mm thick, 75 mm by one convection oven profile will work for all boards and
95 mm in size, and was to be sent through a reflow hence there is no need for developing a unique profile
oven using a lead-free assembly. Thermocouples were for each board. This is simply not true because each
placed on the BTC lands and on the bottom of the FR-4 board has a different thermal mass and one may have
board to monitor the temperatures at these locations. A different loading patterns (distance between boards as
third thermocouple to monitor the oven environment they are loaded in the oven). Even the same
temperature was also attached on top of the FR-4 board. double-sided board, depending upon component
The temperature profile was monitored in seven placement and distribution of copper planes on each
different oven zones, approximately 30 seconds apart. side, may require a different profile for each side. A
The data gathered and the temperature profile used to specific profile for each printed board assembly may be
mount the sample BTC to this board is shown in Table needed since a different thermal mass could be
7-2, Table 7-3 and Figure 7-10. To achieve this profile, associated with each board. This is recommended so
the oven environment was set to 260°C maximum with that a proper profile is assured.
a maximum zone slope of 2.0°C/sec.
Table 7-2
Typical Reflow Profile for Eutectic (63Sn/37Pb) Solder Paste
Profile Elements Straight Line Profile Low Soak Profile
Ramp rate 0.8 – 1.2 °C/s (RT to Peak temp) 1.5 – 2.0 °C/s (RT to 145°C)
Dwell @ 145 to 160°C N/A 30 – 120 seconds
2nd Ramp rate N/A 1.5 – 2.0 °C/s (to Peak temp)
Time above liquidus (183 °C) 45 – 75 seconds
Peak temperature range 210 – 225 °C typical (240 C max)
Ramp-down rate to RT 1 – 3 °C/s typical, (4 °C/s max)
Note: For details, please refer to solder paste manufacturer’s recommendation

Table 7-3 Profile Comparison Between SnPb and SAC Alloys

Profile Topic SnPb Alloy Lead-free Alloy (SAC)
Alloy Solidus temperature 183°C 217-220°C
Alloy soldering temp range 210-220°C 235-245°C
Minimum peak reflow temperature ** 205°C 230°C
Component ramp up rate 1-4°C / second * 1-4°C / second *
Component ramp down rate 2-4°C / second * 2-4°C / second *
Soak or preheat activation temperature 100-180°C * 140-220°C *
Soak or preheat activation time 60-120 seconds * 60-150 seconds *
Dwell time above liquidus 60-90 seconds 60-90 seconds
Dwell time at peak temp. 20 seconds max 20 seconds max
* Verify with the supplier
** Coolest Temperature on the board

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Figure 7-10 Profile for Tin/Lead Solder Reflow

Figure 7-11 Profile for SAC Alloy Solder Reflow

There is also a misconception that if you do need to 7.2.7 Reflow Process Impact on Material Flux has two
change a profile, simply change the belt speed. Having key attributes. First it must remove contamination and,
to change only the belt speed is certainly easy, but it second, it must protect the solderable surfaces after
may not be the right approach. Changing the belt speed contamination removal. A common mistake is to use a
changes the temperature of the board in every zone. time/temperature profile that consumes the flux before
Consideration must be made for the thermal profile to the solder melts. Ideally, the flux would be consumed
ensure the large thermal masses achieve accurate just as the solder begins to melt. Activation time should
reflow while not causing an excessive temperature range from 90 to 120 seconds. Flux usually becomes
condition on the small thermal masses. active at around 130 ºC for tin lead solder pastes.
Typically, solder paste activation for lead-free solder will
be higher, in the 150°C range; however, it is
75
 Table 7-4 Typical Reflow Profile for Lead-Free (SAC305 or SAC405) Solder Paste
Profile Elements Convection or IR
Ramp rate (RT to Peak temp) 0.8 – 1.2 °C/s
Time above liquidus (217 °C) 35 – 80 seconds
Peak temperature range 235 – 240 °C typical (260 °C max)
Ramp-down rate to RT 1 – 2 °C/s typical (6 °C/s max)
Note: For details, please refer to solder paste manufacturer’s recommendation

recommended to work with your solder paste supplier standard attachment processes. The upper end of the
for recommendation on that specific solder paste. range will permit reflow of high lead alloys, which are
used to attach pins to PGA packages. Users faced with
Component termination finish will affect solderability. reflow of a specialty alloy have been successful in
There are a number of component terminal finishes mixing two primary fluids to tailor a vapor phase system
being used today, including tin/lead, gold, tin and for a specific stable boiling point. Higher temperatures
palladium. It is important to select a flux and solder alloy will permit shorter times, which may be advantageous
that works well with the finish being used on the BTCs. with some solder pastes.

Components can be damaged by the incorrect The primary vapor phase should be inert and not
application of heat. All components have a heat introduce contaminants that must be removed later.
exposure limit. Most tin/lead compatible surface mount Solder paste chemicals that dissolve in the fluid are
components should tolerate a peak temperature of carried in the high boiling vapor then deposited on the
220ºC for up to 60 seconds. Lead-free BTCs will be surface of the boards. Such residues tend to be difficult
rated to a higher temperature which is approximately to remove. Minimizing solder paste residue in the
240-260 ºC. Thermal shock, caused by the rapid primary fluid will maximize the lifetime of the fluid,
application of heat, can crack certain components. prevent boiling point elevation due to dissolved paste
However, since the peak temperature of reflow ovens ingredients, and simplify cleaning.
varies, the intent is to heat the solder in a controlled
established profile to a solder joint temperature of The secondary vapor blanket was originally CFC-113, a
210-220 ºC for tin-lead products and for 235-245ºC for lower boiling fluorinated material, which formed a low
lead-free products. cost sacrificial "lid" over the more costly primary fluid.
The constant exposure to the high boiling primary fluid
Warpage is another consideration as BTCs packages at the interface of the two fluids could cause the
become larger. Flatness is important to proper seating secondary fluid to undergo thermal decomposition at the
of the package and solder joint reliability. The higher interface, generating HCl (hydrochloric) and HF
temperature reflow profile required for lead-free (hydrofluoric) acid vapors. These corrosive vapors often
soldering may cause excessive PCB warpage and attacked the soldering equipment over time. While in
should be evaluated. theory the vapors could be absorbed in flux residues
and cause problems for high reliability products, this
7.2.8 Vapor Phase Vapor phase reflow can be was rare in comparison to the attack on the equipment.
operated as a single fluid system or a two fluid system,
utilizing a primary and a secondary fluid. The process With the phase out of CFC-113, a low boiling
was developed using the two fluid approach in batch perfluorocarbon was introduced to replace it. This
equipment; but modern in-line systems are normally second generation secondary blanket fluid was more
operated with only one fluid. Whichever system is used, stable than CFC-113 for prolonged exposure to the high
the maximum temperature reached by assemblies in boiling vapor phase fluids. As surface mount technology
vapor phase (VP) reflow depends on the choice of the grew, most users converted to the higher throughput
primary fluid. Primary fluids are available in a number of in-line machines, which used the single fluid approach.
temperature ranges, with 218-222 ºC being common Defluxing after vapor phase reflow should be done with
with tin lead products and 235-245 ºC for lead-free either a bipolar solvent formulation or include an
products. While all the primary fluids can be classed as aqueous cleaning formulation that can ensure removal
perfluorocarbons, the basic structure (amine, cyclic or of all the solder paste residues, with the choice of
ether) will determine the key properties of in-use cleaning process based on the composition of the
stability solder paste chemicals solubility and overall solder paste. Secondary factors influencing the decision
process economics. The choice of a fluid is normally would be compatibility, and the component to PWB
based on the melting point of the solder alloy to be surface spacing. In addition, most companies gave
reflowed. serious thought to considering the potential chemical
loss from using this type of equipment since many
For the range cited, the lower temperatures are suitable perfluoro compounds are very long-lived global warming
for the typical tin/lead or tin/lead-silver alloys used for compounds.

76
7.2.9 Cleaning vs. No-Clean Residue from the surface vias; some voiding is seen but does not hurt thermal
mount process can create resistive connections dissipation or reliability.
between pads on BTC packages. If a low residue, Factors that determine the post-reflow BTC package
no-clean solder paste is used, PCB cleaning is not standoff from the board include the BTC package
required and has little effect on a BTC. With the weight, the volume solder paste, the land size and land
elimination of materials containing CFCs, most configuration (solder mask defined or nonsolder mask
companies have moved to a no-clean or aqueous defined). However, for packages with a large I/O count,
flux-based system. the package weight may have less effect on the standoff
height.
“No clean” fluxes and solders simply mean that there
are no harmful residues left on the board that could For QFN components the solder joint standoff is a direct
cause corrosion or damage to the components if left on function of amount of paste coverage on the
the board. Residues have sometimes been shown to be thermal pad and the type of vias used for BTCs with
a collection point for outside contamination on the board exposed pad at the bottom. Board mounting
surface. Because there are so many different types of studies have shown that the package standoff increases
no-clean solder pastes available, application specific by increasing the paste coverage and by using
evaluations should be performed to identify if any plugged vias in the thermal pad region. The standoff
remaining residue still needs to be removed from the height varies by the amount of solder that wets or
boards in final production. flows into the PTH via. An open via provides an easy
path for solder to flow into the PTH and
The cleaning process itself must be analyzed to ensure decreases package standoff height while the plugged
that no residual cleaning material is left behind under via impedes the flow of solder into the via due to
the parts. Because of the low profiles and the geometry the plugged via’s closed barrel end. In addition, the
of the BTC, cleaning solution may penetrate under the number of vias and their finished hole size will also
part but may not always completely rinse out. influence the standoff height for open via design.
Depending on the chemistry used, this could introduce
long-term reliability concerns. Refer to IPC-CH-65 and The standoff height is also affected by the type and
IPC-9201 for guidance in cleaning assemblies. reactivity of solder paste used during assembly,
PCB thickness and surface finish, and reflow profile. To
7.2.10 Package Standoff The package standoff is one achieve 50 micron thick solder joints, which help in
of the prime parameters determining the reliability of the improving the board reliability, it is recommended that
BTC solder joints. Package standoff for a BTC is the solder paste coverage be at least 50% for plugged
defined as the distance between the land on the bottom vias and 75% for encroached via.
of the package substrate and the land on the top of the The fillet formation is also a function of PCB land size,
board surface. This distance varies depending on the printed solder volume, and the package standoff height.
volume of solder paste. When BTCs are soldered onto The land size recommended for most BTCs, along with
the board the flux and solvent within the printed paste 1:1 stencil aperture, will provide sufficient solder for fillet
material separate from the alloy. The post-reflow formation if the package standoff is not excessive. Since
standoff height will be approximately 50% of the original there is only limited solder available, higher
solder paste thickness. The standoff height on all BTCs standoff—controlled by paste coverage on the thermal
should be verified during the set up of your process. It is pad—may not leave enough solder for fillet formation.
recommended to establish the process to reproduce the Conversely, if the standoff is too low, large convex
standoff height for specific components. shape fillets may form. This is shown in Figure 7-13.
The standoff height is also affected by the type and The figure also shows that although the contact ends
percent of powder in the solder paste, PCB surface are not plated solder fillets were still formed when these
finish, and reflow profile. Standoff heights are inversely parts are mounted on the PCB with a protruding land
proportional to the land diameters, i.e., as land pattern and 1:1 aperture for peripheral leads. Since
diameters increase, stand off heights decrease. For center pad coverage and via type were shown to have
non-solder mask defined (NSMD) lands, a solder mask the greatest impact on standoff height the volume of
relief around the land may reduce the standoff height, solder necessary to create optimum fillet varies.
because the solder will wet out along the conductors as Package standoff height and PCB pads size will
well as along the edges of the land. This is shown in establish the required volume.
Figure 7-12.
If solder protrusion cannot be avoided, the components
Additionally, the figure shows lead-free, SAC-305 solder may have to be assembled on the top side (or final pass)
paste did not readily flow down ground land thermal assembly, as the protruded solder will impede
dissipation vias. The X-ray pictures confirm that only acceptable solder paste printing on the other side of the
minimal solder actually flowed down the ground land PCB.

77
Figure 7-12 SAC Alloy Flow Characteristics

effectively under the part. Test vehicle evaluation is

recommended to determine if these materials are
appropriate or required for the application and mission
life of the electronics assembly.

7.3.3 Depaneling of Boards and Modules

During a mechanical depaneling process stress may be
placed on solder joints in the area being punched or
routed. Suppliers of mechanical routing equipment
should recommend specifications for keep out areas.
Laser routing is an attractive for singulation as it is
noncontact; however, laser systems are more costly.
Figure 7-13 Post Assembly Contact and DAP Solder Joint
7.4 Inspection Techniques
Profile.
Inspection of a BTC on a PCB is typically accomplished
7.3 Post-SMT Processes by using transmission type X-ray equipment. In most
There are several processes that must be considered cases, 100 percent inspection is not performed.
after the reflow operation. Some of these are shown in Typically X-ray inspection is used to establish process
the following sections and require various degrees of parameters, and then to monitor the production
careful handling in order to maintain the integrity of the equipment and process. There are many different types
assembly. of X-ray inspection equipment available and
functionality varies. X-ray inspection system features
7.3.1 Conformal Coatings range from manual to automated X-ray inspection (AXI).
Special consideration should be taken when using
conformal coatings with BTC type packages. Different systems also provide single or multiple
Allowing coating material to wick underneath the dimensional inspection capabilities. Depending on size
package may cause early solder joint failures due to the and weight, a BTC will self align to the land pad using
“Z” axis expansion of the coating material during surface tension during the solder reflow process.
thermal excursions. As a result, it is unlikely that a BTC will be marginally
misaligned. If misalignment does occur it is likely to be
7.3.2 Use of Underfills and Adhesives by an entire pad. This effect makes it possible to do a
Underfills and adhesives (edge and/or corner bonding) gross visual alignment check after reflow.
may extend the solder joint life during vibration and Visual checks can be aided by the use of PCB fiducial
shock. The use of soldermask in the PCB design, may marks which also aid manual placement of units during
make the standoff distance between the PCB and BTC any rework.
too small for most underfill materials to spread
78
7.4.1 X-Ray Usage X-ray inspection is generally used thickness and features of the board upon which it sits.
when there is a high proportion of hidden solder joints BTC's with copper heat sinks, for example, will typically
that are not visually accessible, and when there are a require higher tube voltage and tube current/power
significant number of un-testable solder joints. settings. On the other hand, BTC's with aluminum heat
Examples of un-testable solder joints are redundant sinks will typically require less since aluminum has a
connections, and back-to-back BTCs where the fanout lower atomic number than copper and is therefore more
vias are inaccessible and space does not allow for transparent to X-rays.
additional test points. X-ray methods can complement
the test process chosen, and can provide faster 7.4.2 Scanning Acoustic Microscopy Scanning
feedback to the manufacturing line, however solder acoustic microscopy (SAM), also called scanning
bonding is not necessarily observable through X-ray acoustic tomography (SAT), is a nondestructive failure
and other testing might be necessary to prove analysis tool. It uses sound waves to scan the internal
metallurgical bonding. layers of an assembly. This technique can also locate
delamination or voids inside a BTC package as well as
Depending on the capability of the X-ray system being locating similar anomalies in underfill after the BTC has
used, X-ray can detect solder related defects such as been attached to the substrate.
bridging, open solder joints, insufficient solder, and
excessive solder volume but, in general, Xray is not The SAM illustration in Figure 7-17 shows locating a
considered to be a reliable inspection technique to flip-chip assembly with the sample being inspected
confirm good solder joints, especially those marginal being immersed in liquid during the SAM analysis. Voids
solder joints that may lead to intermittent contact. Other or areas of delamination that are open to liquid ingress,
defect types such as missing solder, misregistration, however, cannot be detected with this method.
and package popcorning can also be identified. In
addition to defect detection, X-ray can be used to The resolution of delamination or void detection
provide trend analysis for solder volume and solder joint depends on the acoustic frequency used for analysis.
shape. Resolution increases with increasing frequency,
however there is less penetration at the higher
7.4.1.1 X-Ray Image Acquisition Real Time X-ray frequencies. A 230 MHz transducer can bring detection
inspection systems utilize an X-ray source and a resolution down to around a 25 mm gap. A single point
detector system which converts the invisible X-ray observation is called a SAM, a line scan is called a
image into a video display signal. These systems b-SAM, and an area scan is called a c-SAM.
provide immediate imaging results of samples. The
images produced from these systems should not be 7.4.3 BTC Standoff Measurement
distorted or include false artifacts induced by the X-ray BTC standoff measurements are important for process
system itself. Figure 7-14, 7-15 and 7-16 illustrates a control and should be checked during process
comparable level of image quality that should be development and subsequent process validation. Feeler
expected from a manual X-ray inspection system. Real gauges provide a nondestructive method of determining
time systems are available in a broad range of sizes the approximate finished standoff of the BTC after
from small desktop systems to large console floor reflow. Feeler gauges can be used at each corner after
models. They are also available with a broad range of reflow and the combined results can be used to
X-ray tube voltages and tube currents or powers. determine an average standoff measurement. This
method is not as accurate as cross-sectioning, but it is
There is not a specific X-ray tube voltage or much less expensive and nondestructive provided that
current/power needed to inspect BTCs. The settings the operator does not attempt to force a feeler gauge
required will, in part, depend on the sensitivity of the under the device. Doing so could result in breaking
particular X-ray system employed, the structure and solder joints.
characteristics of the BTC under inspection, and the

Figure 7-14 X-Ray Images Using Various Techniques to Detect Missing Solder

79
  Solder Joint Shape – evidence of proper reflow
 Solder Joint Surface Texture – smooth vs. irregular
 Overall Solder Joint Appearance – flux residue, etc.
 Solder Joint Defects – solder shorts, opens, cold
solder

Endoscope inspection technology is best suited for

inspecting only the exterior row BTC solder joints. A
limitation of this technology is the inability to view
interior rows with the same level of quality and clarity.
It is sometimes possible to focus on interior solder joints
but not at the same level of detail as the exterior rows.

7.4.5 Destructive Analysis Methods If the

nondestructive measures used to identify a malfunction
do not succeed in eliciting the cause of failure, then
destructive analysis techniques may be used. Such
Figure 7-15 Typical X-ray After Process techniques will render the analyzed assembly unusable.
Once the cause of the failure has been identified the
information can be used to implement corrective actions
to eliminate the problem.

7.4.5.1 Cross-Sectioning If nondestructive methods fail

to identify the cause of an anomaly, it may be necessary
to use destructive methods to isolate the problem area.
One method traditionally employed for failure analysis is
cross-sectioning, enabling an operator to analyze a
specific section of the component, substrate and solder
joint.

If more than one area is suspect then it needs to be

determined whether those areas can be accessed
sequentially on the same component. If not, then the
areas will need to be prioritized according to the
possibility of finding the problem or more than one
component will need to be analyzed.

Next, if the problem area is a part of a larger assembly,

it may need to be isolated into a small more
Figure 7-16 Wire-bond X-Ray to Leadframe Illustration manageable portion by cutting it out of the larger
assembly. Care must be taken to ensure that the area
The feeler gauge measurement method does require of analysis is not tampered with or destroyed during the
adequate space around the BTC for unrestricted access. cutting and polishing process.
The standoff height of a BTC can give some indication
that the solder joint reflowed completely and uniformly. For proper sectioning, the sample should be molded in
Since each package has its own stand-off resin to alleviate chipping or destruction of the sample
characteristics, users should develop a part assembly during cross-sectioning. If fine polishing of the area of
profile in order to make the use of feeler gauges interest is going to be required, then the sample should
applicable. be sectioned a reasonable distance away from the
interface of interest leaving sufficient distance for fine
7.4.4 Optical Inspection Endoscopy is an optical polishing of the interface.
inspection method that permits visual inspection of tiny
objects in a small, confined area. This technology has In some cases, the entire component may need to be
been adapted and applied to BTC solder joint inspection. ground through and looked at for the integrity of various
Adding localized fiducial locations also can help in interfaces. A common failure analyzed through
identifying accurate position for placing BTC devices. cross-sectioning is an open occurring in an assembly.
Such opens may occur at the solder interface. See
BTC solder joints can be inspected and analyzed for a Appendix A for detailed instructions for performing
variety of critical factors such as: cross-sectioning.
 Overall Solder Joint Quality – evidence of proper
wetting

80
Figure 7-16 Scanning Acoustic Microscopy
for mechanical probing is restricted or not practical.
7.4.5.2 Dye Penetrant Similar to testing BGAs, BTCs can be tested with a
Dye penetrant methods can be used during process probe if a conductor and via is added as a test point.
set-up and in failure analysis to detect solder joint Electrical testing is used to evaluate the functionality of
cracking and wetting problems, and package the electronic assembly. There are two commonly used
delamination. In this process, the sample is immersed in electrical test approaches: incircuit test (ICT) and
a low viscosity liquid dye which penetrates most cracks, functional test (FT).
delaminated areas, or open voids. The sample
component can then be peeled away and examined for ICT utilizes a dedicated bed-of-nails fixture to probe the
the presence of dye in the solder joints or at material completed assembly. This test method is used to detect
interfaces. faults caused by the manufacturing process and also to
isolate the majority of nonfunctional components. The
If a fluorescent dye is used, the sample is inspected faults found by ICT include solder bridging, solder
under UV light. The dye enhances the visibility of flaws opens, component mis-orientation, wrong component,
that might otherwise be difficult to detect. The presence component not functional and conductor short.
of dye on a solder land indicates poor wetting to the
land, and can be used to estimate the portion of the Another approach is to place a low cost in-circuit tester
land that was not wetted; however, very thin cracks may near the end of the assembly line and use it as a
be so small that liquids cannot completely enter manufacturing defect analyzer (MDA). Boards are
because the surface tension of the liquid will not allow it. tested immediately after the components are placed and
See Appendix B for detailed instructions for performing soldered. Problems are quickly relayed back to
dye penetrant testing. manufacturing so corrective action can take place while
the product is being assembled.
7.5 Testing and Product Verification
Testing methodology will vary depending on complexity ICT can be supplemented by a complete functional test
of the assembly and product application. at the end of assembly. This test for product
During the initial stages of prototype and preproduction functionality can, depending on type of product and the
development a great deal of data is necessary acceptability requirements, be as simple as a "go/no-go"
in order to fine-tune the process for a particular test or as complex as a complete exercising of all circuit
assembly. A good design will provide feedback from functionality. FT is used to detect device faults on the
some of the test sequences that can be used to institute assembly at speed. With the higher temperatures on
process improvement procedures. lead-free solder pastes, there may be an increase in
oxidized test lands or test vias. Typically, with tin/lead
7.5.1 Electrical Testing alloys you may print and reflow solder pastes to provide
Electrical testing may require the adoption of boundary a soldered test point for the ICT probes. Lead-free
scan to verify solder joint integrity if net access solder pastes do not spread as well and may cause
81
issues with ICT. It is recommended to run a quick This section establishes the practicable process
experiment during the development stage of the development and maintenance criteria as well as
process to understand the impact of lead-free solder attempting to address the issues related to an
pastes on this process. acceptable assembly process.

7.5.2 Test Coverage 7.6.1 Voids in BTC Solder Joints

Given the current complexity in electronic assemblies, Voiding should be minimized by solder process
the level of "coverage" of test has become an industry development and recurring process controls. The
issue. The more complex a board or assembly, the thermal pad joint of BTCs can have substantial voiding
more difficult it is to fully test. Indeed, it may be difficult mainly due to the relatively large area of the joint. Most
to test even a reasonable portion of the assembly in a vendors recommend a minimum of 50% coverage of the
reasonable, i.e., cost effective, period of time. solderable area of the thermal pad; however, thermal
calculations should determine the actual required
While test of an assembly may be aided by minimum coverage area to allow for proper heat transfer
incorporating test into the silicon devices, this strategy is (see Figure 7-18). Solderable surface area does not
not applicable to bare boards. Thus the challenge of test include open, filled or solder mask encroached vias
is to provide test coverage at a high level of confidence unless they are overplated or filled with solderable
within a reasonable period of time. material.

An effective process monitoring system consists of If the various process parameters such as reflow profile
overlapping tools that create a large bandwidth of and paste printing guidelines discussed in this
coverage. Multiple tools and methods are required since document are followed, voids can be greatly minimized.
there is not one single tool or method that provides the As has been stated, a good stencil design tries to
desired coverage. Optical inspection, X-ray, SAM, ICT achieve 50 to 60% paste coverage of the thermal pad.
and FT are examples of overlapping coverage. These Proper stencil aperture design with respect to any vias
verification methods should be used to monitor products located in the thermal pad can also minimize voids.
and process; they should not be used solely to screen Based on agreement between user and supplier, Table
and separate good and bad product. 7-5 can be used as a process guideline for void
occurrence in different applications. The resulting
7.5.3 Burn-In Testing thermal pad contact percentage is based on the goal of
Burn-in is an operational and environmental test of the the stencil design intending to have 50% coverage of
complete assembly at the upper limits of the application. the thermal pad. Table 7-5 shows the maximum
This test typically finds more component related potential voiding expected for the indicated stencil
problems than solder joint defects. The use of burn-in design and via conditions.
testing is still in use for component evaluation. Burn-in
on electronic assembly is decreasing in favor of some The results shown in Table 7-5 are consistent with
form of accelerated test exposure to screen out those shown in Figure 7-18 through Figure 7-21.
marginal results. The examples and X-ray images indicate that the most
desirable pattern is one that avoids solder paste over
7.5.4 Product Screening Tests
Environmental stress screening (ESS) is used to screen
ongoing production for poor product quality and latent
defects. The purpose of ESS is to accelerate the latent
defects to actual failures, thus eliminating these latent
defects from causing failures in the field. Care must be
taken that the ESS procedures are not sufficiently
severe to damage good product and produce new latent
defects. Solder fatigue life on BTCs shall be evaluated
on the thermal cycling of these ESS tests, other tests,
and the operating life thermal environments.

7.6 Assembly Process Control Criteria for Plastic

BTCs
BTC solder joints have a tendency to voiding from the
release of volatiles in the solder paste during the solder
reflow process. The degree of voids permitted in the
BTC assembly attachment process and the impact on
reliability is of interest to members of the electronics
industry. The detailed requirements for end product Figure 7-18 Typical thermal plane voiding
acceptance shall be in accordance with J-STD-001;
workmanship requirements shall follow the
requirements of IPC-A-610.

82
Table 7
-5 Guidelines for Void Criteria in Thermal/Ground Planes of BTCs
Design Application No Vias in Plane Open Vias in Plane Capped Via in Plane
Stencil Design Solid 50% Potential Voiding 70 % Potential Voiding 35 % Potential Voiding
Stencil Design Segmented 35% Potential Voiding 45% Potential Voiding 25% Potential Voiding
Stencil Design Dot Pattern 15% Potential Voiding 35% Potential Voiding 15% Potential Voiding
Assembly Contact Solid Stencil 25% of Pad Level A 15% of Pad Level A 32.5% of Pad Level A
Assembly Contact Segmented Stencil 32.5% of Pad Level B 22.5% of Pad Level A 37.5% of Pad Level B
Assembly Contact Dot Pattern Stencil 42.5% of Pad Level C 32.5% of Pad Level B 43.5% of Pad Level C
Note: Levels A, B, and C reflect the design producibility. Level A = General; Level B = Moderate; Level C = High

via location and using the dot pattern appears to provide and requires a known reference for radiometric
greater attachment potential through less voiding. calibration of the X-ray film or detector. In most cases
the effort is better spent on identifying and eliminating
It is also important to understand the relationship the cause of the voids. BTC solder joints are prone to
between paste applied on large thermal pads and any more voiding than other solder joints due to the nature
thermal vias in those pads. Figure 7-19 shows solder of the thermal pad joint itself. BTC solder joints are
paste printed over plugged thermal vias using segments formed mainly between two parallel surfaces and
on the left and Dots on the right. The corresponding depending on the ability of volatiles or other trapped
X-ray images in Figure 7-20 showed far less voiding for gasses to escape can result in voiding.
solder paste dots compared to solder paste segments.
All of these options have pros and cons when mounting
Figure 7-19 shows relatively large solder voids when BTC packages on the board. While via tenting from top
using the solder paste segment approach compared to side may result in smaller voids, the presence of solder
using solder paste dots. Another set of examples are mask on the top side of the board may hinder proper
provided in Figure 7-21 and Figure 7-22. paste printing. On the other hand, both via tenting from
bottom or via plugging from bottom may result in larger
The appearance of a void after reflow assembly is an voids due to out-gassing. Finally, open vias allow the
indicator that the reflow process has taken place. solder to wick inside the vias and reduce the size of the
However, a change in void size or frequency of voids voids. However, it also results in lower standoff of the
may be an indication that the manufacturing parameters package, which is controlled by the solder underneath
need to be adjusted. Two reported causes of voids are the exposed pad.
trapped flux that has not had enough time to be
released from the solder paste, and contaminants on 7.6.2 Solder Bridging Solder bridging is unacceptable.
improperly cleaned circuit boards. Voids appear in an Electrical testing, optical inspection (endoscope) or
X-ray image as a lighter area inside the solder joint. X-ray inspection is necessary to detect solder bridging.
Poor solder paste printing, inaccurate placement,
Some X-ray systems can distort the size of voids due to manual "tweaking" after placement and solder
parallax issues. It is possible to accurately measure the splattering during reflow are typical causes of solder
true volume of a void but the procedure can be involved bridging.

Figure 7-19 Solder Paste Segments vs. Solder Paste Dots Printed over Plugged Thermal Vias

83
Figures 7-20 X-ray Images Showing Solder Segment and Solder Dot Voiding Results

Figure 7-21 Solder Paste Printing Strategy: Segments (left) vs. Solder Dots (right)

Figure 7-22 Solder Segments vs. Solder Dots - Void Potential

7.6.3 Opens and substrate solderability problems can also cause

opens. Excessive mechanical stress can also cause
Solder opens are also unacceptable. A combination of solder joints to crack and create opens.
electrical testing, optical inspection (endoscope) or
X-ray inspection is usually necessary to detect solder 7.6.4 Cold Solder The reflow profile should reach
opens. Poor solder paste printing, inaccurate placement temperatures high enough to ensure that the solder
and manual ‘tweaking" after placement, are typical melts completely and proper wetting of the land surface
assembly related causes of solder opens. Coplanarity occurs. A cold solder joint can reduce mechanical

84
integrity and can cause the component to fail electrically molten solder contact. See Figure 7-23 and 7-24. It is
or function intermittently. Optical inspection after recommended that Test S, Surface Mount Process
crosssectioning is the best way to inspect for cold solder Simulation Test as defined in JSTD- 002, be used for
joints. the testing of BTC packages.

7.6.5 Defect Correlation/Process Improvement The

manufacturing process produces solder joints that are
either acceptable or unacceptable. This can be
etermined through inspection using methods and tools
discussed previously. In many cases a visual inspection
of a BTC is the first clue to any problems. An operator
can look at the edge of the BTC on all four sides.

To directly observe the solder connections under a BTC,

X-ray or optical inspection (endoscope) is necessary.
These methods can be used to inspect for obvious
defects such as bridges and missing solder joints.

Quantitative measurement of the solder bond X-ray

image can be performed using image analysis software.
Such software is useful but not necessarily required for
the inspection of BTCs. The advantage of the software
is in its ability to identify and display subtle variations in
the size and shape of the solder bond image which is Figure 7-23 Dip and Look Test
not easily observed by an operator. These subtle
variations are a signature of the process used to
manufacture the part and can be used to monitor the
process and to correct for deficiencies. A number of
signatures can be correlated with known process
deficiencies.

7.6.6 Effect of Insufficient and/or Uneven Heating

A common process problem is insufficient or uneven
heating of the BTC. This problem occurs more often
during rework but can also be seen in production when
working with multilayer boards with many ground or
power planes. The problem can also happen on
double-sided boards when a shielded component is on
the backside near the location of the BTC. The problem
occurs when a thermal conductor removes the heat
from the BTC preventing thorough wetting of the solder.
The X-ray image of this problem is characterized by a
variation in the size of the solder joint at different Figure 7-24 Process Simulation Test
locations under the package.
7.6.8 Solder Ball Defects Solder balls, which form for a
Insufficient heating is generally characterized in an variety of reasons during reflow, are a reliability concern,
X-ray image by small partially reflowed solder joints in especially when fine pitch devices are involved.
the center or to one side of the package. Insufficient
heating may also be characterized by a jaggedness 7.7 Repair Processes
around the perimeter of these solder joints; indicating
that the solder partially reflowed but not long enough to 7.7.1 Rework/Repair Philosophy In general, the
completely wet to the land. Misalignment of the BTC rework station for BTCs are typical of systems currently
with respect to the land is also an indicator of used for rework of BGAs. The system should have a
inadequate heating. The X-ray image of misalignment is split light system, an XY table for alignment and a hot
characterized by elongated solder joints which may or air reflow system with top and bottom heater for
may not have a consistent orientation component removal. If the BTC is being removed from
tightly packed boards such as cell phones, a laser
7.6.7 BTC Component Solderability Testing rework system may have an advantage since they will
Solderability evaluations using standard 'Dip and Look' not heat the neighboring components as would be the
techniques can result in false negative test results for case when using hot air systems.
some BTC devices. BTC packages which have
non-symmetrical pad patterns and/or configurations can
result in unintended flux interactions and a lack of

85
The standard industry practice for rework consists of handling of the PCB during the bake cycle should also
various steps including: be taken into account.

 PCB bake 125ºC for 24 hours 7.7.2.2 PC Board Preheat

 PCB preheated to 125ºC Once the PCB has finished the baking process, the
 Reflow of component solder PCB under rework is then placed in the rework holder
 Removal of component <via machine vacuum, and preheated to a temperature of 125°C. Localized
manual plunger or tweezers> heating of the area under rework is recommended (use
 Cleaning and prep of PCB lands 4°C/second maximum ramp rate).
- Screening or dispensing of solder paste
onto PCB Specialized vacuum collets come in contact with the
- “Bumping” of solder paste onto device rework component. These collets incorporate a hot gas
 Placement and reflow of new component shroud that heats up the part to a temperature required
 Inspection of solder joints for reflowing the solder interconnects.
Once the solder reflows, the vacuum lifts the unit from
To remove the faulty component from the board, heat the PCB. The nozzle size and hot gas flow should be
from hot air or lasers should be applied from the optimized to keep the heat flow localized to the
top and bottom heaters. An air nozzle with the correct component being removed, while uniformly heating the
size should be used to conduct the heat to the component.
BTC component such that the vacuum pick up tool can
properly remove the component. The laser does not 7.7.3 BTC Assembly Defect Repair
require different size nozzles for removal. In the event of defects occurring after component
attachment, the board assembly will require rework to
Once the BTC component is removed, the site is remove and replace the device. Since most of the
cleaned and dressed to prepare for the new component soldered joint is inaccessible, correction of the defect
placement. A de-soldering station can be used for will generally require the complete removal and
solder dressing. remounting or replacement of the component. Usual
applications for BTC devices involve mounting on small,
A mini-stencil with the same stencil thickness, aperture thin, densely populated PCBs. These factors, coupled
opening and pattern as the normal stencil is placed on with the small size of the components themselves, can
the component site. A mini-metal squeegee blade lead to challenges in reworking defects.
deposits solder paste in the specific area. Because of product dependent complexities, the
following is only a guideline and a starting point for the
The printed pad should be inspected to ensure even development of a successful rework process for these
and sufficient solder paste before component placement. packages.
Unlike in repair of BGAs, the correct amount of paste is
critical for successful rework of BTC. The rework process includes the following steps:

In situations where neighboring parts are in close 1. Board preparation

proximity with the BTC components and the ministencil 2. Component removal
method is not an option, apply solder paste carefully on 3. PCB land clean up
each land using a syringe. The volume of solder paste 4. Application of solder paste
will be difficult to control unless an automated dispenser 5. Component alignment and placement
is used as in the case with higher end dispensing 6. Component attachment
systems available in laser rework systems. 7. Inspection of rework

A vacuum nozzle is used to pick the new package up. 7.7.3.1 Component Removal
The split light system displays images of both the BTC In order to facilitate the removal of the component from
leads and the footprint on the PCB. The two the PCB, the solder joints attaching component to the
superimposed images are aligned manually (or board should be reflowed. Ideally the reflow profile used
automatically in higher end systems) by adjusting the for removing the component should be the same as that
XY table. Once the PCB and the package are aligned, used for component attachment. Figure 7-25 shows a
the package is placed down on the PCB. The replaced typical component removal setup.
component is then soldered to the PCB.

7.7.2 Removal of BTC

7.7.2.1 PC Board Bake

It is recommended to bake the PCB for approximately
24 hours at 125°C prior to rework in order to drive off
residual moisture that could cause other component
failures during the rework reflow process. Proper
86
 solder joint), with or without the use of built-in preheat.
In addition to using traditional preheaters, the laser can
be programmed for post-heat operations (just a few
milliseconds) to achieve desired solder joint quality.

Because laser soldering time is measured in

milliseconds (as opposed to seconds), the intermetallic
thickness is less than 1 μm, greatly improving solder
joint reliability for many applications.

7.7.3.3 PCB Land Preparation for Reattachment

Once the component has been removed, the site should
be adequately prepared to receive the replacement
device.

Cleaning the site is done in two steps:

(1) Desoldering - Desoldering is achieved through the

Figure 7-25 Solder is heated to liquidus state and the BTC use of a ‘desoldering braid’ in conjunction with a
is withdrawn before solder re-solidification blade-type soldering iron typical of that shown in
Figure 7-26. The width of the blade should match
The time the solder alloy is above liquidus can be the maximum width of the component footprint, and
reduced as long as the reflow is complete. During reflow, the blade temperature should be low enough to
localized heating of the PCB from the bottom side using avoid any damage to the circuit board.
a heating source is recommended. There are several
heating methods for bottom side heating including, but Non-contact heated vacuum systems are also used
not limited to, hot air and IR. Reflow of the solder joint is in high-end rework stations since the procedure
achieved by directing heat to the topside of the allows for the cleaning of the PCB lands using a
component; this can be accomplished using a heat gun vacuum system so as not to scratch the board or
or IR radiation. During the reflow of the solder joints, a damage the land.
vacuum cup operating within the confines of the gas
shroud attaches to the top side of the component. Once (2) Cleaning - The site should be wiped clean using a
the reflow of the solder joints has taken place, either a lint free cloth and solvent. The solvent is usually
vacuum-assisted suction cup or some mechanical lifting specific to the type of solder paste used in the
technique such as tweezers can be employed to lift the original assembly.
component off of the PCB. Use ESD-safe components
which are properly grounded, when using manual lifting
devices. . Given the small size of the components, the
vacuum pressure should be kept below 0.5 kg/cm2. This
will prevent the component being lifted out before all the
joints have been reflowed and avoid pad lift.

Note: Because of the potential for internal damage

during repeated thermal exposure, removed
components should not be reused.

7.7.3.2 Laser Enabled Rework for BTC Assemblies

Laser technology has gone through a tremendous Figure 7-26 Desoldering of the BTC Mounting Site
change, from traditional YAG and CO2 lasers to
7.7.3.4 Application of Solder Paste When reworking
semiconductor technology of diode lasers. Many
BTC components there are two main approaches to
applications exist where laser soldering will be more
attaching the device onto the already-populated PCB.
cost-effective than traditional methods discussed above.
One involves the selective solder application on to the
Laser soldering has proved to be costeffective selective
PCB while the other involves the selective application of
soldering of components when contact or convection
the solder onto the replacement part. The application of
reflow is not technically feasible.
the solder paste is accomplished by one of several
methods including solder paste printing, solder paste
Unlike hot air/gas rework systems, laser soldering does
dispensing or hand soldering.
not need special fixtures that add to variable cost.
Focused laser soldering parameters are controlled in
Pad geometries of the BTC component present a
four stages; preheat temperature, laser power (8 to 30
challenge in producing an even solder line thickness on
W), wave length (800 to 900 nanometers), and time in
reflow. A number of critical features of the print stencil
milliseconds (generally less than a second for a typical
should be considered. Stencil alignment accuracy and
87
consistent solder volume transfer is critical for uniform
reflow solder processing. The stencil thickness, as well
as the etched pattern geometry, determines the precise
volume of solder paste deposited. Stencils are usually
made of brass or stainless steel, with stainless steel
being more durable.

As a guide it is recommended to use a 125 micron

(0.005”) stencil thickness for the BTC components.

Laser formed stencil apertures are normally trapezoidal,

as shown in Figure 7-27 where dimension A is greater
than dimension B. This form factor helps to ensure a
uniform release of the solder paste and minimizes
solder paste smearing.

Figure 7-28 Example of Window Pane Pattern on Stencil

 The stencil aperture sizes need to be closely

controlled in the case of peel and release type of
Figure 7-27 Typical Laser Ablated Stencil Aperture
Geometry
stencils as the geometries are critical
 The recommended stencil thickness should be
Due to the smaller land geometries and dense between 0.075mm and 0.127mm (0.002 and 0.005
component population of the PCBs, accurate and in)
uniform screen-printing of solder paste onto an already  Stencils can be made from a variety of materials but
populated board is very difficult. It is recommended that are typically made from brass, stainless steel or
the solder paste be applied directly onto the base of the polyimide. see Figure 7-29.
component before placement.
The process is shown in Figures 7-30 and 7-31 where:
Land geometries along with the existence of a large
area ground pad of the BTC presents a challenge for  The component is placed and secured onto a stencil
making sure that the stencil is designed properly for fixture
solder paste application in order to produce an even  Solder paste is then applied using a metal
solder thickness upon reflow. A number of print stencil squeegee blade
features are critical. See 7.4.3.
Note: The minimal standoff height of BTC package may
 For optimum paste release the area and aspect not be leave enough gap for efficient post reflow
ratios should be greater than 0.66 and 1.5 soldering cleaning
respectively.
 For stay in place stencils on the PCB the aspect
ratio is not important as it is not released from the
PCB.
 It is recommended that the stencil aperture should
be 1:1 to PCB pad sizes as both the area and
aspect ratio targets can be achieved using this
guideline.
 For the larger exposed solder pads (such as the
center ground) found on some BTC designs the
stencil opening in this area needs to be divided into
an array of smaller openings. Dividing the larger
exposed pads into the smaller screen openings
reduces the risk of solder voiding and allows the
solder joints for the smaller terminal pads to be at
the same height as the larger ones. It is
recommended that a “window pane” stencil opening
patterns for the pads for the large exposed a pad as Figure 7-29 Typical Metal stencil for printing onto
in Figure 7-28 below: component

88
 device and space on the board. However, hand
soldering cannot access unexposed bottom side
terminations. In addition the geometries involved require
a very high degree of hand soldering precision and
excellent tooling else damage to the component and
nearby components is likely. For these reasons, hand
soldering is not a recommended practice for solder
paste application on BTCs.
Figure 7-30 BTC device is clamped into stencil fixture
Application onto the part- solder“bumping”:
Due to the smaller geometries, dense component
population of the PCBs, accurate and uniform screen
printing of solder paste using a print and release stencil
design is difficult and requires a high degree of
operator dexterity and skill. In these cases it is
recommended that the solder paste be applied directly
on top the base of the component before placement.
Either metal stencils, paste dispensing or polyimide
“peel and release” stencils can be used. Once the
device is “bumped” the component can be precision
placed and reflowed similar to other area array devices.
See Figure 7-33
Figure 7-31 Solder paste is transferred through stencil
apertures onto the undersurface features of the BTC.

therefore, the manufacturer recommends that the

operator use a ‘Type 3, 4, or 5 no clean solder paste
(See J-STD-005).

Application via dispensing: Solder paste dispensing

can be used for dispensing solder paste in a very
controlled fashion onto the PCB. Typically a
programmable X-Y-Z axis controller such as a robot
moves into the correct position where a precise volume
of paste is dispensed. Very accurate placement and
controllable volumes of paste are the result of this
technique.

Application via hand soldering: Hands soldering of

leadless packages can be achieved in some cases for
the peripheral pads. Access to these pads depends on
the existing of a solder surface on the side of the
package, access to an exposed pad underneath the
Figure 7-33 Solder Bumping Method Using a Stencil

7.7.3.5 Component Alignment and Placement

The accuracy of component placement of the package
is equipment and process method dependent. It is
challenging to place the parts in many cases as the
package sizes of BTC devices tend to have a small
footprint. While BTC do have the ability to self align to
an extent due to their small mass, this is
counterbalanced by the greater surface tension of lead
free solders. Slightly misaligned parts should self-align
during reflow as a result of surface tension within the
liquid solder. Grossly misaligned parts are likely to result
in shorting and bridging.

There are a variety of methods one can use to place the

parts including the use of a split beam optical system as
part of the rework system or a stay in place alignment
stencil.
Figure 7-32 Typical Dispensing System

89
A spilt beam system is used to place either a “bumped” PCB .After solder paste is rolled in to the apertures and
component--a component which has solder applied to the stencil wiped of any remnant solder paste, a
its bottom side (see Figure 35)--or to place a component bumped part is then align and placed in to those
in to solder paste which has been printed/dispensed apertures by hand. The part is then reflowed as
onto the PCB (see Figure 34). This type of split-beam previously described.
optical system is used to align the component to the to
the solder pad array on the PCB as the BTC leads are 8 RELIABILITY
located on the underside of the package. This imaging This section provides insight into the method of stress
system will provide an image of the leads that are testing in order to validate that a part, board or
superimposed and by adjustment overlaid onto the assembly will work for a specific period of time within an
corresponding footprint of the PCB and therefore align acceptable failure limit. Information is concentrated on
the component with the pad array. This alignment is the solder joint and the metallurgical bond between the
done at magnification. The placement machine must attachment surfaces.
have the capability of allowing for fine adjustments in X,
Y and the rotational axis. Once aligned and placed, the 8.1 Accelerated Reliability Testing The validation and
reflow profile used should be optimized to mimic the qualification tests should follow the guidelines given in
original assembly profile. IPC-SM-785, Guidelines for Accelerated Reliability
Testing of Surface Mount Solder Attachments and/or
IPC-9701, Performance Test Methods and Qualification
Requirements for Surface Mount Solder Attachments.
For some products, the accelerated temperature cycling
(ATC) needs to be combined with mechanical shock
and/or vibration testing.

Accelerated reliability testing is carried out on design

prototypes, typically to failure or until a predetermined
reliability goal is achieved. The appropriate reliability
goal can be determined with an appropriate acceleration
model (see IPC-D-279). Once failure occurs, the
resulting failure modes are analyzed as to the
underlying failure mechanism(s). If it fails expectations
then corrective action is necessary. Either the assembly
process needs to be improved or the product needs to
be redesigned. In either case retesting may be
necessary after the corrective action has been
implemented.
Figure 7-34 Alignment stencil on PCB
Recognizing that a matrix was needed to determine the
exact requirements and the testing necessary for
performance under various conditions the IPC Product
Reliability Committee developed the following
table ’’Product Categories and Use Environments.’’
Table 8-1 attempts to relate seven product categories
by typical application to the thermal, mechanical,
atmospheric, and electrical performance requirements
that they must meet during typical manufacturing
processes, storage, and during operation.

8.2 Damage Mechanisms and Failure of Solder

Attachments
The reliability of an electronic assembly depends on the
reliability of the sum of the individual elements of the
mechanical thermal and electrical interfaces (or
attachments) between these elements. One interface
type, the surface mount solder attachment, is unique
Figure 7-35 “Bumped” part placed and reflowed since the solder joint not only provides the electrical
interconnection, but is also the sole mechanical
A second method which can be used for rework attachment of the electronic components to the printed
involves the use of a stay-in-place stencil which acts as board. It often provides the critical heat transfer function
the alignment guide of the part onto the PCB. In this as well. A solder joint in isolation is neither reliable nor
method the stencil is aligned to land patterns ofthe unreliable; it becomes so only in the context of
device being placed, placed and adhered to the application.

90
 Table 8-1 Accelerated testing for end use environments

& = in addition
(1) T represents the maximum temperature swing but does not include power dissipation effects; for power dissipation calculate T; power
dissipation can make pure temperature cycling accelerated testing significantly inaccurate. It should be noted that the cyclic temperature range,
T is not the difference between the possible minimum, Tmin and maximum, Tmax, operational temperature extremes; T is typically
significantly less.
(2) All accelerated test cycles shall have temperature ramps, 20°C/minute and dwell times at temperature extremes shall be 15 minutes measured on
the test boards. This will give ~24 test cycles/day.
(3) The failure/damage mechanism for solder changes at lower temperature; for assemblies seeing significant cold environment operations, additional
“COLD” cycling, from perhaps -40 to 0°C, with dwell times long enough for temperature equilibration and for a number of cycles equal to the
“COLD” °C operational cycles in actual use is recommended.
(4) The failure/damage mechanism for solder is different for large cyclic temperature swings traversing the stress-to-strain -20 to +20°C transition
region; for assemblies seeing such cycles in operation, additional appropriate “LARGE T” testing with cycles similar in nature and number to
actual use is recommended.

The characteristics of these three causes thermal expansion mismatches or

elements—component, substrate, and solder PCB/component warping or bending. These higher
joint—together with the use conditions, the design life, stresses combine with less strong solder to base
and the acceptable failure probability determine the material connections due to inadequate wetting or
reliability of the surface mount solder attachment. The interfacial structural weaknesses to cause brittle
general characteristics of most lead free solders as interfacial failure.
compared to tin/lead solders, include (1) significantly
greater strength, (2) significantly slower creep rates, (3) 8.2.1 Differences in Accelerated Testing of SAC vs.
greater difficulties of proper spread, and (4) significantly Tin/Lead SAC solder joints may develop additional
higher soldering temperatures. failure modes and damage mechanisms during
accelerated test, such as temperature cycling, as
The consequence of the greater strength and the slower compared to tin/lead solders. The reasons for this are
creep rates are higher stresses on the whole solder founded in the facts that SAC solders are stiffer and
attachment structure during either temperature changes
91
have much lower creep rates; both of these conditions is rarely the case and problems with ‘embrittlement’
generate higher stresses. have occurred with less than 3 wt.% of Au.

8.2.2 Mixed Alloy Soldering Since the only solder in It is important to put the issues into the correct
the board to package interconnect comes from the perspective. Au- and Ag-embrittlement occurs with the
solder paste there is no risk of mixed alloy soldering that thick and somewhat uncontrolled deposits that can
exists in BGAs. However, since any assembly may have result from electroplating of Au and Ag; they do not
both BGAs and BTCs the possibility of mixed alloy occur with immersion plating of either Au for ENIG or
exists, thus alloy selection should consider, mounting imAg as a surface treatment.
land finish, BTC terminal finish and BGA ball solder
alloy compatibility. 8.2.7 Stand-off Height
Increasing stand-off height is one way to enhance the
8.2.3 Mold Compound Material solder joint reliability of bottom termination components.
Mold component selection has an impact on the The design of the center pad (thermal pad), its coverage
package reliability. Selection of mold material should be and the number and size of vias on it has been shown
based on meeting package reliability requirements like to have the largest impact on standoff height. Increased
moisture sensitivity level and meeting the board level standoff can be achieved by using a thicker stencil.
reliability. Board level reliability directly depends on the There are limits to this option due to aperture area and
CTE of the mold compound. Mold compound with lower aspect ratio requirements for paste release and floating
CTE preformed worse in reliability testing than ones risk of the center pad. Also, since multiple types of
with higher CTE close to the board material. The mold components are mounted on the same board, using a
compound modulus also impacts the stiffness of the thicker stencil for one or two components is not
package. Higher modulus will result in stiffer package desirable.
and lower fatigue life.
One alternative is to increase the thickness of the
8.2.4 Die Size plating on the thermal pad on the underside of the
Die size has significant impact on board level reliability. package. This has been used by Amkor in the Bump
As the die to package ratio decreases the board level MLF concept as shown in Figure 8-1. A plating
reliability increases. With smaller die the board level thickness of 100 microns increased the stand-off height
reliability is better because the die edge, which has a of the package solder joints by 100 microns. This
low CTE, is farther away from the peripheral solder resulted in a 2X increase in the board reliability of the
joints. package as shown in Figure 8-2.

8.2.5 Full vs. Half Etched Leadframe

Package pads can come with two options: a full pad and
a half etched pad. The package pad is the same and
both cannot be soldered on the side to create a fillet
there is no impact on reliability. Since the package is
going through singulation process after plating the
exposed side leads are not plated. The copper on the
side lead is oxidized and is not solderable during reflow.
In some cases when a side lead fillet is created data
indicates improvement in reliability.

8.2.6 Gold/Silver/Palladium Embrittlement As the

joint standoff is very small in BTCs compared to BGAs, Figure 8-1 Plate-up Bumped Option
noble metal embrittlement could be a reliability issue.
8.3 PCB Design Considerations
Gold, palladium, as well as silver-embrittlement, work in Several design characteristics impact the solder joint
combination. “Au/Ag-embrittlement” is the weakening of reliability.
the solder structure by too many weak interfaces with
the crystalline AuSn-IMC platelets and the solder. 8.3.1 Land size Another influence on reliability is the
Larger number of such IMC platelets result in higher geometry of the solder joint that is derived from the land
density of such interfaces and an increased SJ metallization on the board. Since BTCs are leadless
weakness. There is an interfacial loading that comes devices, the solder joint shape relates to the land. A
from a CTE-difference between these IMCs and the larger land under a BTC package provides better
surrounding solder volume. There is little practical reliability as shown on the Weibull plot in Figure 8-3.
difference in the effect of either Comparing a 7 mm package with 28 terminations and
AuSn-IMCs, AgSn-IMCs or any combination of them. with land sizes of 0.28 mm x 0.6 mm and a 48 terminal
package with land size of 0.23 mm x 0.4 mm QFNs,
The widely-used 3 to 4 wt.% of noble metal in the solder results in a 2X improvement in fatigue life. The larger
joint is basically a rule-of-thumb. It applies to the total land results in a larger solder joint and longer path for a
solder volume and assumes that the IMCs are uniformly complete crack to formation.
distributed throughout the solder volume. This, however,
92
 An approach demonstrated as effective for Inspecting
BTCs for unsoldered connections and cold solder joints
requires:
1) Solder Paste Inspection (SPI) to determine whether
sufficient solder paste is present.
2) Automated Optical Inspection (AOI) to inspect fillets
formed on device sides or flanks.

Automated X-ray inspection (AXI) can also cover the

inspection for sufficient solder. In that case, an
SPI system is not necessary, but AOI is still required. It
is important to note that AXI alone does not have the
required detection rate to protect against BTC assembly
defects like unsoldered connections and cold solder
joints.

8.3.2.2 Inspectable Side Fillets Require BTCs with

Wettable Flanks
In the method discussed above, the AOI system is used
Figure 8-2 Cracks in QFN Solder Joints After Temperature to establish whether proper BTC assembly was
Shock achieved by allowing for the evaluation of solder fillets
visible along the sides (flanks) of the device. To achieve
externally visible solder fillets after reflow assembly
requires wettable flanks at the BTC component edges.

Perimeter side edges of BTC (e.g. QFN components

according to JEDEC MO220), typically have exposed
copper on the cut or punch separation surfaces or
flanks. These exposed copper areas are wettable as
long as the copper is not significantly oxidized. After
even a few days of storage, however, copper surfaces
may oxidize to the point that sufficient solder wetting is
no longer possible with typical No-Clean fluxes. For this
reason, exposed copper areas of QFN leads that have
no special treatment to ensure solderability are not
expected to be wettable. See QFN example in Figure
8-4.

Figure 8-3 Land size Impact on Fatigue Life of 7 mm BTC

Package

8.3.2 Fillet formation

While BTC suppliers typically do not require fillets to be
formed on the toe of their packages, it is generally
agreed that these fillets can improve reliability. Solder
fillets are formed along the flank or perimeter toe edges
of BTCs. Toe fillet formation should not be expected
since some BTC suppliers do not protect exposed
Figure 8-4 QFN with Wettable Flanks
copper from oxidation after device singulation.
8.3.2.3 Specification for BTC Flank Wettability
The surface mount process parameter can also
JEDEC MO220 defines the basic characteristics of QFN
influence fillet formation. Some of the variables are
components which generally now should also apply to
PCB land size, solder paste volume, solder paste flux
all BTCs. In addition, the following are also required for
activity, reflow atmosphere and standoff height.
specification purposes related to BTC Flank Wettability:
When a fillet forms, it increases the joint length which
provides a longer path for the crack to form.
 Each IO lead must have a visible flank at the
side of the component (no pullback I/O leads).
8.3.2.1 Methods for Inspecting BTCs
 Each flank must be wettable.
 Mold compound is not allowed on any part of
the flank of the IO leads.
93
  Double or Multi rows with similarly blinded IO make it impossible to develop a generic model that
leads are not inspectable using the method considers all the variables. Products with conformal
described here. coatings should be evaluated using test vehicles having
the same coating and test vehicles without the coating
Flanks shall also meet the same solderability in order to assess the impact of the coating on reliability.
requirement as the rest of the device.
Appropriate DfR-measures to improve reliability can
8.3.3 Board Thickness take one of two forms, which are best employed in
Thinner printed boards result in better board level combination for improved reliability margins. These
reliability. The board material FR4 (~17 ppm/°C) has a measures are:
larger CTE than the package mold compound (~10
ppm/°C). Thinner PCBs reduce cyclic strains due to the 1) CTE-tailoring to reduce the global expansion
global CTE mismatch between the PCB and the mismatch;
package by flexing and increase solder joint fatigue life. 2) Increasing attachment compliancy to accommodate
Tests conducted on 10 mm -68 lead and 5 mm -32 lead the global expansion mismatch;
packages using 0.8 mm and 1.6 mm thick boards show 3) Eliminate the effect of the global expansion
at least 30% improvement in fatigue life for the thinner mismatch by mechanically coupling the component
board. See Figure 8-5. and the substrate with an appropriate underfill;

Further, a DfR procedure aiming at high-reliability

should also include:

4) Choosing base materials that have not too large a

local CTE-mismatch with solder; or
5) In case item (4) cannot be done, reduce the
continuous wetted length to reduce interfacial
stresses.

CTE-tailoring involves choosing the materials or

material combinations of the PCB and/or the
components to achieve an optimum DCTE. An optimum
DCTE for active components dissipating power is ~1-3
ppm/ 0C (depending on the power dissipated) with the
PCB having the larger CTE, and 0 ppm/0C for passive
components. Of course, since an assembly has a
multitude of components, full CTE- optimization cannot
be achieved for all components—it needs to be for the
Figure 8-5 Weibull Plot Showing Thinner Board Results in components with the largest threat to reliability. For
Higher Fatigue Life military applications with the requirement of hermetic —
and thus ceramic—components, CTE-tailoring has
8.4 Voids in Thermal Pad meant the CTE-constraining of the PCBs with such
Voids in thermal pads could cause reliability concern. materials as Kevlar™ and graphite fibers, or
There is no rule of what is the acceptable level of copper-Invar-copper and copper-molybdenum-copper
voiding. It is specific to the component and the use planes. Such solutions are too expensive for most
condition of the device. As long as the thermal pad is commercial applications for which glass-epoxy or
providing sufficient coverage for cooling requirements glass-polyimide are the materials of choice for the PCBs.
during maximum operation condition, then it is Thus, CTE-tailoring has to take the form of avoiding
acceptable. The requirements should derive from larger size components that are either ceramic (CGAs,
thermal modeling. MCMs), have plastic with Alloy 42 leadframes (TSOPs,
SOTs), or are plastic with rigid bonded silicon die
8.5 Design for Reliability (DfR) Process (PBGAs).
The fatigue behavior of surface mount solder joints has
been investigated experimentally in numerous studies. Increasing attachment compliancy for BTC solder
The results of the studies that were carried out in a attachments means increasing the solder joint height
manner to assure the same damage mechanism as the (see Section 8.2.7) or switching to a compliant leaded
mechanism operative in typical electronic products have attachment technology. For compliant leaded
yielded a mathematical solder fatigue model. This attachments increasing lead compliancy can mean
model has been expanded and augmented to its current changing component suppliers to those having lead
form, presented in IPC-D-279, as additional test results geometries promoting higher lead compliancy or
became available. switching to fine-pitch technology.

The model is for uncoated solder attachments. The

complexity and vast differences in conformal coatings
94
The DfR-process needs to emphasize a melting temperature is 228K or -45 ºC. Hence, creep
physics-of-failure perspective without neglecting the deformation can occur in solder at a given load
statistical distribution of failures. even at temperatures as low as -45 º C.
The relation between stress experienced by the solder
The process might involve the following steps: joint and the activation energy is expressed by the
general creep equation:
1) Identify Reliability Requirements: expected design
life and acceptable cumulative failure probability at
the end of this design life.
2) Identify Loading Conditions: use environments (e.g.,
IPC-SM-785) and thermal gradients due to power Where,
dissipation, which may vary and produce large
numbers of mini-cycles (Energy Star). ɛ = strain rate
3) Identify/Select Assembly Architecture: part and = constant
substrate selections, material properties (e.g., CTE),
= stress
and attachment geometry.
4) Assess Reliability: determine reliability potential of n = stress exponent
the designed assembly and compare to the Q = activation energy
reliability requirements using the approach shown k = Boltzmann constant
here (see IPC-9701), or some other suitable = temperature in degrees kelvin
technique; this process may be iterative.
5) Balance Performance, Cost and Reliability Creep strain is the result of thermally activated
Requirements. dislocation motion and/or movement of vacancies and
atoms when the material is subjected to a given load.
8.5.1 Wear-out Mechanisms Stress relaxation over time observed in solder joints is a
The primary failure mechanism that affects the reliability direct result of creep processes. Hence the damage
of any solder joint connection is damage accumulation accumulated in solder joints during temperature cycling
by thermo-mechanical processes such as creep and is a result of creep and fatigue processes. Deformation
fatigue. Failures are also caused by electro-migration due to creep has been observed in packages which
and thermal-migration of metal which result in opens. have been subjected to both cyclic loading as well as
Both the thermal-mechanical and electrical failures can static loading conditions.
be increased by chemical reactions or species which
can cause corrosion or enhance migration of metallic Static loading conditions can arise, for example, from
ions (shorts). A solder bump wear-out failure in the field the weight of a heat sink on a package. Depending on
has never been observed. This indicates both the how the board is placed, that is, sideways, right side up,
robustness of the solder bump and conservativeness of or inverted, the solder joints can experience shear,
the reliability models that will be subsequently compressive or tensile loads. The constant load in one
explained. direction can cause failure by creep processes.

8.5.2 Creep-fatigue Interaction 8.5.2.1 Electro-migration

Solder joints can see large strains during temperature In alloy systems, the mobility of each atomic species
cycling. The strains are generated by the difference in under an applied electric field is different based on the
the thermal expansion between the die and the effective valence and mass of the species.
substrate. The cyclic nature of the temperature variation Electro-migration has been observed on chips as well
causes the strains experienced by the solder joints to be as in solder joints. In a joint, migration of voids to chip or
cyclic and, therefore, the damage in the solder to be a board interface has been observed. Small voids can
function of the number of thermal cycles. By this coalesce causing a mechanical reliability concern or
definition, solder joints experience thermal creep-fatigue. current crowding can occur if the effective conductive
At uniform strain distributions, fatigue causes damage cross section is reduced. In both cases observing
by the initiation and propagation of micro-cracks. design rules with regard to current density and
Fracturing of solder joints is increased with high rates of dimension can solve the problem.
change of strain.
8.5.2.2 Corrosion
In general, components see thermal cycling which can Solder joint corrosion is usually caused by moisture and
range from 0.4 Tm to 0.8 Tm, where Tm is the absolute ionic contaminants. This can be prevented by proper
melting temperature of solder. As a rule of thumb, creep packaging design and process control. Due to the close
is an operative deformation mechanism whenever the proximity of flip chip solder joints, the cleanliness of the
temperature is above half the absolute melting solder joints is essential. Residues from corrosive
temperature of the material. processing chemicals must be minimized. Depending
For example, the melting temperature of 63/37 Sn/Pb on use conditions, the flip chip solder joints should be
solder is 456º Kelvin (183.6 º C), half the absolute either hermetically sealed , or encapsulated with a

95
 material that prevents a continuous moisture path. Table 8-3 Typical Heights (Joined)
Solder Bump Diameter Height Range
8.5.2.3 Thermo-migration Condition (μm) (μm) (μm)
Thermo-migration is caused by excessive thermal Option A 150 82 64-100
gradients across solder bumps incorporated on the Option B 125 77 64-95
terminations of BTC packages, especially at higher IC Option C 100 70 64-85
junction temperatures. In the thermo-migration process, Option D 150 >82 64-100
atoms diffuse in the direction of, or in opposition to, the
thermal gradient. Atoms in the solder bump can diffuse, footprint with similar characteristics and packaging but
leading to voiding at the interface of the solder and the varying DNP.
UBM (Under Bump Metallurgy). The bump will
eventually become electrically open. For a given bump 8.5.3.2 Effect of Thermal Expansion Mismatch
geometry, thermomigration is a function of thermal The neutral point or geometric center of solder bumps
gradient, ambient temperature, and alloy composition. remains stationary relative to the substrate during
thermal excursions. Determination of the neutral point is
8.5.3 Solder Thickness Mechanical Reliability critical for calculating DNP. Figure 8-6 illustrates the
There are numerous factors that can affect the result of near-interface failure due to thermal excursion
mechanical reliability of BTC attachments. Some of of dissimilar materials.
these are:

 Strain
 Temperature Hold Times
 Chip Underfill
 Solder Alloy Composition

8.5.3.1 Strain
The effect of strain is significant. Its impact on solder
bump fatigue is dependent upon several factors.
These are determined by the design, application and
manufacture of the device. Table 8-2 shows the CTE
difference between the chip silicon, alumina, leadframe,
printed board; all which can be part of a typical BTC
package. Strain is directly proportional to DNP, the
distance from the furthest, functional solder bump to the
neutral point on the chip.

Table 8-2 Coefficients of Thermal Expansion for Typical Figure 8-6 The crack formation is the result of the CTE
Materials mismatch
Material CTE (ppm/°C)
The geometrical shape of the solder joint can greatly
Silicon 2.8
affect the local strain. The top and bottom land
GaAs 6.0-7.0 diameters combined with the volume of solder will
Solder (Sn3Pb97) 28-29 determine the height of the joint, a prime influence on
reliability. Stress ‘‘riser’’ factors can influence crack
Chip underfill 18-35 initiation and propagation. Ideally a tall, slender solder
Alumina 6.0-7.0 column will distribute the strain in the solder joint and
extend fatigue lifetime. A short, squat solder joint may
FR-4 16-19 reduce product life.
Copper leadframe 17-18
8.5.3.3 Temperature Cycling Frequency
Testing of the life of components under actual use
Strain is inversely proportional to joint height. Table 8-3 conditions would take as long as the design life of the
furnishes typical heights for varying solder bump component. For this reason, packages are tested by
diameters. accelerating the thermal cycles, i.e., by increasing the
temperature range and decreasing the hold times at
The resources required to perform these test are often each end of the cycle. Increasing the temperature range
limited. Consequently, methods have evolved that use subjects the joints to greater strain, the extent of which
existing solder bump footprints with known fatigue is determined by the thermal expansion mismatch
histories to predict performance of a solder bump between the different materials. Hence, increasing the
temperature range should increase the damage stored

96
in the joints if enough time is allowed for the elastic effects will depend on process control in terms of well
stresses generated in the solder joints to relax out by sealed sites, cleaning of the attach sites, and controlling
converting the elastic strains into plastic deformations environmental exposure to avoid contaminants from the
by creep. If enough time is not allowed during the hold application environment. In general, this wear-out
times, which is typically the case with accelerated tests, mechanism is best controlled through design and
then the damage stored is not equal to what it would be process control.
if the solder joints were allowed to creep completely.
However, it needs to be noted that increasing the Electro-migration mechanisms are affected by current
temperature range of the test much beyond the density. If the designer keeps current density within the
temperatures in the field will cause a confounding of constraints of the materials being used, and there is
multiple damage mechanisms. strict process control on defects, electromigration
should not be a problem for most applications.
The design of the temperature cycle ideally should be
such that the stresses generated because of the 8.6.1 Reliability Factors
thermal expansion mismatch have enough time to relax Creep-fatigue is the primary mechanism for wear-out of
out. However, this is impossible for accelerated testing. BTC assemblies. Creep-fatigue is accumulated
Increasing the frequency of cycling can change the damages caused by cyclic thermal stressing by the
failure mechanism and/or suppress the damage stored environment or application and the creeping of the
per cycle in the solder joints. For example, changing the solder under these loads. This cycling behavior causes
temperature rapidly during thermal shock testing can plastic deformation within the BTC interconnects, which
cause high strain rates as well as high strains due to initiates a crack that will eventually grow to open or
component warpage to be imposed on the solder, which substantially degrade the interconnect. Most system
changes the failure mechanism. applications will have temperature changes which will
eventually fatigue the interconnects.
With near-eutectic solders it is necessary to have hold
times ranging from 5-10 minutes to achieve a significant, It is important that the user of BTC package
but still incomplete, creep in the joints. The stress technologies have a fundamental understanding of the
relaxation in high lead (90%Pb-10%Sn) solders is intrinsic material properties and on the design/process
slower than that observed in eutectic solders and driven dimensions for their application. The application
therefore the hold times at the temperature extremes environment factors involved in fatigue are temperature,
need to be greater. Thermal cycles represent the temperature cycle range, and hold times of the
number of thermal excursions a flip chip or chip scale temperature cycling. The BTC assembly will affect the
product will be exposed to during its lifetime. These reliability in terms of presence of under-fill, the
excursions consist of power on-off cycles and symmetry of interconnect pattern, misalignments and
environmental temperature fluctuations. Temperature variations of bump geometries and device size.
cycling tests the inelastic properties of the solder,
namely stress-relaxation as a function of temperature Under thermal cycling, the failures will first occur at
and time. locations farthest from the thermal expansion center
point. It is possible to develop detailed models, as most
8.6 Wear-out Mechanisms Review are based on some form of the Coffin-Manson equation
Bottom termination interconnects have many potential for low-cycle fatigue modified to account for the effects
failures, but there are primarily five degradation or of creep. A model for each BTC approach could be
wear-out mechanisms which affect metal interconnects. established if the geometry, material and application
These are: conditions are known. There are various published data
on bottom only termination type component reliability. It
 Creep is extremely important that a user establish this level of
 Fatigue knowledge to apply these technologies reliably.
 Corrosion
 Electro-migration 8.6.2 Benefits of Reinforcement
 Solid state diffusion BTC underfill can substantially enhance fatigue life.
When the underfill is applied correctly, it reduces the
These mechanisms can all lead to degradation and solder joint strain level by constraining the expansion of
eventual failure of BTC interconnects. They are very the BTC interconnect to be used in a wider range of
dependent on materials used, processing defects, environments and larger device sizes can be
reduced geometries, assembly stresses, and accommodated. Underfill material must be carefully
environmental conditions. Creep is caused by stresses selected, so that it adheres to the assembly surface, but
or displacements applied to the interconnect in one does not adversely stress the BTC interconnect joints.
direction. Properly selected materials can minimize this The material must have properties which allow easy
mechanism for most environments. Corrosion could application to avoid process defects, and it also must
become a concern in some applications. The BTC not contain or trap contaminants which could initiate
assemblies are used in a number of non-hermetic corrosion related problems.
applications. Reliable operation without corrosion

97
If an underfill fails, it will most likely lose adhesion to the Reliability is defined in IPC-SM-785 ‘Guidelines for
device and/or substrate. This would lead to failure due Accelerated Reliability Testing of Surface Mount
to fatigue, creep, or it could also increase chances of Solder Attachments’, by:
corrosion and other failure mechanisms.
Reliability is the ability of a product to function under
8.6.3 Event Related Failures The assembled BTC given conditions and for a specified period of time
assembly can experience unexpected thermal and/or without exceeding acceptable failure levels.
mechanical transients, which are isolated events related
to maintenance or just abnormal system operating In the short term, reliability is threatened by infant
conditions. These events could, if they are severe mortality failures due to insufficient product quality;
enough, cause catastrophic failure, or they can initiate these infant mortalities caused by defects can be
failure sites which will then fail at a later date. These eliminated prior to shipping by the use of appropriate
types of failures are best accommodated by selecting screening procedures.
the most robust technology that can be used. There are
some additional failure mechanisms which need to be Long-term failures are the result of premature wear-out
considered when using flip chip technology. damage caused by inadequate designs of the assembly.
It is for this reason that IPC-D-279 ‘Design Guidelines
Most BTC finishes are 63/37 tin/lead alloy, tin, gold or for Reliable Surface Mount Technology Printed Board
SAC, thus some BTC interconnects use alloy Assemblies’ has been developed.
combinations that include lead content to improve
ductility. This can lead to trace amounts of radioactive 8.7.1 Damage Mechanisms and Failure of Solder
elements which emit alpha particles which can cause Attachments
soft errors in semiconductor devices. It is important to The reliability of electronic assemblies depends on the
factor the lead and underfill, much lower level particle reliability of their individual elements and the reliability of
emissions for proximity to sensitive device features to the mechanical, thermal, and electrical interfaces (or
minimize this effect. Most semiconductor devices have attachments) between these elements. One of these
ESD protection placed near the pads and most interface types, surface mount solder attachment, is
available devices are not configured for flip chip unique since the solder joints not only provide the
interconnection. Rerouting layers will be applied to the electrical interconnections, but are also the sole
surface of the device to convert these devices to a BTC mechanical attachment of the electronic components to
array configuration. This will result in some metal runs in the printed board and often serve critical heat transfer
close proximity to device structures that are not functions as well.
protected.
A solder joint in isolation is neither reliable nor
8.7 Design for Reliability Issues and Concerns unreliable; it becomes so only in the context of the
The reliability of electronic assemblies requires a electronic components that are connected via the solder
definitive design effort that has to be carried out joints to the printed board. The characteristics of these
concurrently with the other design functions during the three elements - component, substrate, and solder joint
developmental phase of the product. There exists a together with the use conditions, the design life, and the
misconception in the industry, that quality manufacturing acceptable failure probability for the electronic assembly
is all that is required to assure the reliability of an determine the reliability of the surface mount solder
electronic assembly. attachment.

Consistent high quality manufacturing and all that this 8.7.2 Solder Joints and Attachment Types
implies in terms of Design for Manufacturability Solder joints are anything but a homogeneous structure.
(DfM), Design for Assembly (DfA), Design for Testability A solder joint consists of a number of quite different
(DfT), etc., is a necessary prerequisite to assure the materials, many of which are only superficially
reliability of the product. Only a Design for Reliability characterized. A solder joint consists of:
(DfR) can assure that the design, manufactured to good
quality, will be reliable in its intended application. Thus,  the base metal at the printed board
adherence to quality standards is necessary but not  one or more intermetallic compounds (IMC)
sufficient. For example, solder joint quality is generally  a layer from which the solder constituent forming
measured against criteria in both IPC-A-610 the PCB-side IMC(s) has been depleted
‘Acceptability of Electronic Assemblies with Surface  the solder grain structure, consisting of at least two
Mount Technologies’, for overall workmanship and phases containing different proportions of the solder
ANSI/J-STD-001 ‘Requirements for Soldered Electrical constituents as well as any deliberate or inadvertent
and Electronic Assemblies.’ However, meeting these contaminations
criteria does not assure reliable solder connections, only  a layer from which the solder constituent forming
quality solder connections. the component-side IMC(s) has been depleted
 one or more IMC layers of a solder constituent with
To clarify the difference between the two requires an the component base metal
explanation and a definition of reliability.

98
 the base metal at the component The global expansion mismatches result from
differential thermal expansions of an electronic
8.7.3 Solder Interface Grain Structure Effects component or connector and the printed board to which
The grain structure of solder is inherently unstable. The it is attached via the surface mount solder joints. These
grains will grow in size over time as the grain structure thermal expansion differences result from differences in
reduces the internal energy of a fine-grained structure. the CTEs and thermal gradients as the result of thermal
This grain growth process is enhanced by elevated energy being dissipated within active components. This
temperatures as well as strain energy input during cyclic global expansion mismatch will cyclically stress, and
loading. The grain growth process is thus an indication thus fatigue, the solder joints. The cyclically cumulative
of the accumulating fatigue damage. At the grain fatigue damage will ultimately cause the failure of one of
boundaries contaminants like lead oxides are the solder joints, typically a corner joint, of the
concentrated; as the grains grow these contaminants component causing functional electrical failure that is
are further concentrated at the grain boundaries, initially intermittent. See Figure 8-8.
weakening these boundaries. After the consumption of
~25% of the fatigue life microvoids can be found at the
grain boundary intersections; these micro-voids grow
into micro-cracks after ~40% of the fatigue life; these
micro-cracks grow and coalesce into macro-cracks
leading to total fracture as is schematically shown in
Figure 8-7

The different surface mount solder attachment

compositions can have significantly different failure
modes. Solder joints with essentially uniform load
distributions, e.g., QFNs, flip chip, BGA, CGA, show
similar behavior. Solder joints with non-uniform load
distributions, i.e., those on bottom termination only
components, leadless chip carriers, CSPs and all
leaded solder joints, show localized damage
concentrations with the damage in the form of
macro-cracking. The solder joints frequently connect
Fig 8-8 Solder crack due to CTE mismatch after 1000
materials of highly disparate properties, causing global cycles
thermal expansion mismatches and are made of a
material, solder, that itself often has properties 8.7.5 Local Expansion Mismatch
significantly different than the bonding structure The local expansion mismatch results from differential
materials, causing local thermal expansion mismatches. thermal expansions of the solder and the base material
The severity of these thermal expansion mismatches, of the electronic component or PCB to which it is
and thus the severity of the reliability threat, depends on soldered. These thermal expansion differences result
the design parameters of the assembly and the from differences in the CTE of the solder and those of
operational use environment. the base materials together with thermal excursions.

8.7.4 Global Expansion Mismatch

Figure 8-7 Depiction of the Effects of Accumulating Fatigue Damage in the Solder Joint Structure

99
Local CTE-mismatches typically range from ΔCTE~7 8.10.1 Solder Joint Defects
ppm/°C with copper to ~18 ppm/°C with ceramic The solder joint defects of greatest reliability concern
and ~20 ppm/°C with Alloy 42 and KovarTM. Local are those involving inadequate wetting for whatever
thermal expansion mismatches typically are smaller reason. Properly wetted solder joints have adequate
than the global expansion mismatches since the acting strength even for severe mechanical loading conditions
distance, the maximum wetted area dimension, as well as no diminished thermal cyclic fatigue reliability.
is much smaller, in the order of hundreds of microns. However, solder joints not properly wetted, can
prematurely fail both as the result of mechanical and
8.7.6 Internal Expansion Mismatch thermal cyclic loading. Voids in the solder joints are
An internal CTE-mismatch of ~6 ppm/°C results from generally regarded as not constituting a reliability threat.
the different CTEs of the Sn-rich and Pb-rich phases of However, there are some exceptions. Large voids
the solder. Internal thermal expansion mismatches reducing the solder joint cross-section enough to reduce
typically are the smallest since the acting distance, the a required thermal heat transfer function, such as those
size of the grain structure, is much smaller than either for the thermal pads on MLF and QFN devices, can
the wetted length or the component dimension in the cause premature device failure.
order of less than 25 μm.
8.10.2 Screening Recommendations
8.8 Solder Attachment Failure Effective screening procedures need to be capable of
The failure of the solder attachment of a component to causing the failure of latent solder joint defects,
the substrate to which it is surface mounted is i.e., weak inadequately wetted solder joints, without
commonly defined as the first complete fracture of any causing significant damage to high quality solder
of the solder joints of which the component solder joints. The best recommendation is random vibration
attachment consists. Given that the loading of the solder (6-10 grams for 10-20 minutes), preferably at low
joints is typically in shear, rather than in tension, the temperature, e.g., 40°C. This loading does not damage
mechanical failure of a solder joint is not necessarily the good solder joints, but overstresses weakly bonded
same as the electrical failure. Electrically, the ones. Thermal shock can also be successfully used,
mechanical failure of a solder joint results, at least however some damage to good solder joints can be
initially, in the occasional occurrence of a short-duration expected, particularly for larger components.
(<1 μs) high-impedance event during either mechanical
or thermal disturbance. From a practical point of view,
the solder joint failure is defined as the first observation
of such an event.

For some applications this failure definition might be

inadequate. For high-speed signals with sharp rise
times, signal deterioration prior to the complete
mechanical failure of a solder joint might require a more
stringent failure definition. Similarly, for applications
which subject the electronic assemblies to significant
mechanical vibration and/or shock loading, a failure
definition that considers the mechanical weakening of
the solder joints as the result of the accumulating
fatigue damage might be necessary.

8.9 Validation and Qualification Tests

Performance test methods and qualification
requirements are specified in IPC-9701; IPC-9701A
includes guidelines for lead free solder joint reliability
testing. However, in the current absence of generally
useful reliability acceleration models, there currently are
no qualification requirements for lead free solder joint.
The validation and qualification tests should follow the
guidelines given in IPC-SM-785, Guidelines for
Accelerated Reliability Testing of Surface Mount Solder
Attachments. However, for large components
with significant heat dissipation, for components of
asymmetric construction, and for small global CTE
mismatches, temperature cycling tests are inadequate
to provide the required information; full functional
cycling including external temperature and internal
power cycling is necessary.
8.10 Screening Procedures

100
9 DEFECT AND FAILURE ANALYSIS CASE 9.1.2 Insufficient Solder Failures
STUDIES
This section provides information on BTC package
attachment defects.
The illustrations are provided to assist the user as a
process effects condition The illustrations may be used
as a trouble-shooting guide and controlled experiment
characteristics in order to determine potential solutions
for eliminating any problems.

9.1 Solder Attachment Failures

9.1.1 Solder Attachment Failure Conditions

Figure 9-3 Cross section of BTC open joint due to

insufficient solder paste volume during printing

Figure 9-1 Optical image of acceptable QFN edge

terminations. Solder fillets should exist if the design
incorporates pads that extend beyond the package width.

Figure 9-4 Cross section of BTC reliability failure after

1000 cycles due to insufficient solder paste volume
during printing

Figure 9-2 Optical image of acceptable QFN edge

terminations. Solder fillets should be visible to a
minimum of 75% of the width of the termination.

101
9.1.3 Land, Nonsolderable
Package Failures

Figure 9-5 Nonsolderable land on LGA package

Figure 9-8 Cross section image of QFN with an open joint
caused by nonwetting of the solder to the bottom land of
the QFN

9.2.1 Package Warpage

Figure 9-6 3-D X-ray shows non-wet joints on a QFN

Figure 9-9 Cross section of LGA with a corner joint failure.

The paste wicked to the package

Figure 9-7 Optical image of unacceptable QFN edge

terminations. The solder rise is limited and an open joint
can be seen. The package is also ‘floating’ above the
surface of the pads.

Figure 9-10 Concave warpage on 15x15 mm BTC

102
9.3 Dewetting Failures 9.4 Cracked Solder Joint Failure
9.3.1 Dewetting on QFN
9.4.1 Cracks in Solder Joints

Figure 9-13 Defect Condition of QFN edge joints showing

insufficient solder in a joint
Figure 9-11 Good wetting on QFN thermal pad after
printing and reflow

Figure 9-14 Cracks in QFN solder joints after temperature

shock

Figure 9-12 Dewetting on QFN thermal pad after printing

and reflow

103
9.5 Component Failures
9.5.1 Tilted Component 9.5.2 Lead Configuration Conditions

Figure 9-15 Tilted BTC causing high joint height open on

Figure 9-17 Full lead option on BTS component
the left

Figure 9-16 Tilted BTC causing good height on the right Figure 9-18 Half etched option on BTS component

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9.5.3 Joint Configuration Condition
9.5.4 Solder Joint Volume

Figure 9-19 Small fillet due to nonwetting of the side

copper Figure 9-21 Large fillet due to increase of solder volume

Figure 9-20 Side fillet on bottom termination component

good wetting to copper lead Figure 9-22 No Side fillet on bottom termination
component

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9.6 Voids 9.6.2 Voids in Solder Joints Microsection and X-Ray
9.6.1 Voids in Solder Joint Through Xray

Figure 9-25 BTC component with a large edge joint.

The joint did not have any cracking after shock test

Figure 9-23 Target Condition of QFN edge joints

where showing a moderate level of voiding within
joints is acceptable. All joints have reflowed.

Figure 9-26 16-pin QFN with voids in the joint and

the thermal pad but well within action level

Figure 9-24 Acceptable Condition of QFN edge

joints showing an increased level of voiding within
the joints but well within any action level.

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9.6.3 Voids in Thermal Pad

Figure 9-27 QFN component with increase level of

voiding to above 30%. Could be a reliability concern

Figure 9-28 Acceptable Condition of QFN edge

joints showing an increased level of voiding within
the joints but well within any action level.

107
10 GLOSSARY AND ACRONYMS PBBO Polybrominated Biphenyl Oxide
PBDE Polybrominated Diphenyl Ether
AABUS As Agreed Upon Between User And Supplier. PBGA Plastic Ball Grid Array
ASIC Applications Specific IC PCA Printed Circuit Assembly
ASM Array Surface Mount PCB Printed Circuit Board
ASMP Application Specific Module Packaging PCM Phase Change Materials
BGA Ball Grid Array PLCC Plastic Leaded Chip Carrier
BOC Board-On-Chip PSA Pressure Sensitive Adhesives
BT Bismaleimide-Triazine PTH Plated Through-Hole
BTC Bottom Termination Components QFN Quad Flat No-Lead
CBGA Ceramic Ball Grid Array QFP Quad Flat Pack
CGA Column Grid Array RDS Rectangular Die Size
COB Chip-On-Board RF Radio Frequency
CPU Central Processing Unit RFID Radio Frequency Identification
CSP Chip Scale Packages RMS root mean, square
CTE Coefficient Of Thermal Expansion RoHS Restriction of Hazardous Substances
CTF Critical To Function SDRAM Synchronous Dynamic random access memory
DAP Die Attach Pad SMD Solder Mask Defined
DBDPE Decabromodiphenyl Ether SMOBC Solder Mask Over Bare Copper
Df Dissipation Factor SMT Surface Mounting Technology
DFN Dual Flat No-lead SO-DIMM Small Outline Dual In-Line Memory Module
DfR Design For Reliability SOIC small outline integrated circuit
DIG Direct Immersion Gold SON Small Outline No-lead
Dk Dielectric Constant SPC Statistical Process Control
ENEPIG Electroless Nickel/Electroless Palladium/Immersion SRAM Static random access memory
Gold SSO Simultaneously Switching Output
ENIG Electroless Nickel Immersion Gold TAB Tape-Automated Bonding
FAT Flux Activation Time TBBPA Tetrabromobisphenol A
FBGA Fine Pitch Ball Grid Array Td Decomposition Temperature
FC Flip Chip TFBGA Thin Profile Fine Pitch Ball Grid Array
FPT Fine Pitch Technology Tg Transition Temperature
HASL Hot Air Solder Level TIM Thermal Interface Materials
HAST Highly Accelerated Stress Testing UFPT Ultra Fine Pitch Technology
HDB High Density Printed Boards UtRAM Uni-transistor Random Access Memory
I/O Input/Output UUT Unit Under Test
IMC Intermetallic Compound UV Ultraviolet
IR Infrared VFBGA Very Thin-Profile Fine-Pitch Ball Grid Array
LCP Liquid Crystal Polymer
LFBGA Low-Profile Fine-Pitch Ball Grid Array 11 BIBLIOGRAPHY AND REFERENCES
LGA Land Grid Array 1. D. Bernard and B. Willis, Common Process Defect
LMC Least Material Condition Identification of QFN Packages Using Optical and X-Ray
MCM Multichip Module Inspection. SMTAI Proceedings, 2007
MCM-L Multichip Module-Laminate 2. F. Schuler, M. Rosch, Johannes Horber, Klaus Feldmann,
MCP Multichip Package Reliability Aspects of Electronic Devices for Advanced
MD Metal Defined Packages, Circuit World, Vol 34, No 3, 2008.
MDS Multi Device Subassembly 3. A. Syed, and W. J. Kang, Board Level Assembly And
MLC Multilayer Ceramic Reliability Considerations For Qfn Type Packages, SMTAI
MMB Moisture Membrane Bag Proceedings, 2003
MMC Maximum Material Condition Engelmaier, W., ‘‘Surface Mount Solder Joint Reliability:
MSL Moisture Sensitivity Level Issues, Design, Testing, Prediction,’’Workshop Notes,
NSMD Non Solder Mask Defined Engelmaier Associates, Inc., Mendham, NJ, 1995.
OEM Original Equipment Manufacturer
OSP Organic Solderability Preservative
PBB Polybrominated Biphenyl

108
 Appendix A
Metallographic Preparation
should be chosen which can be cleaned off of
Introduction the specimen easily and completely, so that the
encapsulating epoxy can bond to the sample
Preparing tin-lead solder joints for metallographic surface.
evaluation requires extra care. The samples are 5) Ceramic Precautions: Due to their hardness,
composed of high hardness (Copper-Tin) intermetallic aluminum oxide ceramic specimens require the use of
compound particles dispersed in a very soft (Lead, diamond bonded cutting equipment during both cutting
Lead-Tin) matrix. This heterogeneous mass is coated and grinding. Also, beryllium and beryllium oxide
on a hard basis material of copper or iron alloy. The materials produce toxic dust and must never be cut dry.
lead-tin matrix can recrystallize at temperatures
achieved during the curing of some epoxy mounting A2 Mounting The specimen should be encapsulated
materials or hardening of some thermoplastic mounting in some rigid medium for grinding and polishing, so as
materials. Polyester or acrylic mounting materials with to achieve a flat, uniform surface and to protect the
as LOW a temperature rise during cure or setup as solder joint. Caution must be used to ensure that the
possible are recommended. Great care is required in mounting procedure does not change the solder joint
revealing the undeformed, undamaged structure under microstructure. Overplating with copper or nickel can
the superficial layer. help to protect highly deformable materials. Two
mounting methods are:
General comments on metallographic sample
preparation, mounting, and polishing can be found in 1. Quick Mounting: This method utilizes a
IPC-TM-650, 2.1.10 and 2.1.1.2, in IPC-MS-810, thermoplastic material such as
‘‘Guidelines for High Volume Microsection,’’ and in polymethylmethacrylate, and typically is not entirely
Leco Corporation’s ‘‘Metallography Principles and transparent. Filling of small cavities and adhesion to
Procedures’’ which also contains reprints of ASTM the sample may be inferior to the results of slow
E407-70 and ASTM E340-68. In addition, pages 5–12 in mounting. However, one mount can usually be
the ITRI publication 580 are instructive in dealing with prepared in approximately 5–15 minutes. The heat
tin-lead solder joint destructive physical analysis (DPA). generated by quick mount
2. Slow Mounting: This method typically utilizes
A1 Cutting The initial step for metallographic epoxides as the mounting media Vacuum
preparation is the isolation of the component or solder mpregnation techniques can be used to remove air
joint for mounting. This entails the use of a jeweler’s bubbles and improve flow of the encapsulant into
saw, router, abrasive saw, or similar cutting device to confined spaces. Some encapsulants must be
remove the specimen. Several factors should be cured at temperatures ranging from 60 to 90°C,
considered during this initial step: while others are room temperature curing, but can
generate even higher temperatures by exothermic
1) Cut Location: Care must be taken to remove the reactions. Experimentation with empty molds will
specimen without cutting too close to the solder joint reveal whether this is a problem. Curing in a water
of interest. The cut should, however, be close bath helps to remove excess heat. Mounting time
enough that excessive grinding is not required. If in scan vary from 1 to 8 hours depending upon the
doubt, leave a little extra material. Usually 2.5 mm product and the curing conditions
of material around the area of interest is sufficient.
2) Fixturing: Care must be taken to ensure that A3 Preparation for Mounting When mounting a
damage is not done to the specimen while holding it specimen, it is important that it be oriented properly.
for cutting. Proper orientation depends upon your grinding and
3) Cutting Speed: A smooth, consistent feed rate and polishing equipment and technique. Practice will
pressure should be maintained to avoid damaging determine what works, and what does not. Here are two
the specimen. Vibration of the specimen during basic mounting methods:
cutting must be avoided.
4) Cutting Fluids: Oil, water, or other types of coolant 1. Verical Mounting: The sample is held vertical
should be used with abrasive blades, especially relative to the bottom of the mold either by gluing it
diamond blades. The cutting fluid serves two main to the mold floor or by using special clips. The
purposes: encapsulant can then be poured into the mold until
a Removal of the cutting debris, allowing for it is full.
efficient material removal.
b Removal of heat generated during cutting.
When a situation requires dry cutting, extreme
care must be taken to avoid generating heat
which may affect the specimen, particularly
solder joints or polymeric materials. A coolant
109
2. Half-Mounts: The sample is placed horizontally into channels in the soft lead or lead-tin matrix when the
a mold which is half full of previously cured particles break free and roll downstream. Manually
encapsulant. The mold is then filled with or automatically moving or rotating the sample
encapsulant and allowed to cure. The sample is counter to the wheel rotation will minimize grooves
then ground from the side, and may not fit into some and channels.
automatic machines. If this is a problem, then
vertical mounting should be used. Note: The A5 Polishing The next stage of metallographic
grinding and polishing sections of this procedure preparation following the grinding step is polishing the
were written from the point of view of manually sectioning plane. Polishing is a less severe continuation
grinding and polishing the sample. Most of the of the specimen surface abrasion. Polishing media can
concepts are applicable, however, to automatic include diamond, aluminum oxide, silicon oxide, or
processing. Attempts have been made to reconcile chromium oxide. Polishing media particle size
the differences between the two procedures. progresses from about 9 μm to as fine as 0.05 μm to
produce a uniform, scratch free surface. This is usually
A4 Grinding The third step of sample preparation divided into coarse (9 to 1 μm) and fine (1 to 0.05 μm)
involves removing material from the specimen to polishing. Again several factors should be considered
expose the areas of interest. Grinding is an abrasive during this step:
process to slowly remove deformed surface material
and reveal underlying, nondeformed regions. Grinding is 1. Cleanliness: WASH THE SAMPLE FREQUENTLY.
typically done using silicon carbide papers, progressing It is extremely important that the sample and
from 120 to 1000 grit depending on the amount of anything that comes near it (including hands and
material removal required. Several factors should be work benches) be as clean as possible at all times
considered during this step: during polishing. The sample should be washed and
rinsed with warm soapy water before beginning to
1. Pressure: Sample hardness dictates, to some polish the sample and after each step. Brief
extent, the amount of pressure required. Pressure ultrasonic cleaning is the most effective way to
should be kept light to avoid excess deformation of clean out small cavities such as cracks or voids.
the specimen surface. 2. Polishing Cloth Selection: The primary difference
2. Time: The grinding time for each piece of grinding between grinding and polishing is that while grinding
paper should be kept short. Excessive grinding time grit is fixed in place, polishing uses freely flowing
can cause faceting as the grinding paper wears particles in a slurry. This slurry is held on a cloth
down and the particles get dull. Faceting is usually which determines the extent of the surface relief
corrected by switching to a new, sharp piece of and the polish quality. Lower nap cloths will produce
grinding paper. a flatter surface than high nap cloths, but may not
3. Cutting Fluid: As with the cutting operation, fluid is remove all scratches as effectively. Special low nap
used to remove debris and prevent the specimen fine polishing cloths can produce a very flat, nearly
from overheating. Water is the most common scratch-free surface.
cutting fluid. 3. Polish Extenders: Extenders play an analogous role
4. Ceramic Materials: Due to the hardness of ceramics, in polishing to that of the cutting fluid in grinding,
components, packages and substrates made of removing debris and minimizing heat generation. An
ceramics such as aluminum oxide (alumina) or extender also ensures proper dispersion of the
beryllium oxide (beryllia) require the use of diamond polishing media. Care must be taken to use the
bonded cutting wheels and grinding disks. proper amount of extender. Too much extender will
Mechanical processes such as grinding and allow the sample to float, causing excessive relief.
polishing of beryllia pieces create a dust defined as Too little extender may allow the encapsulant to
a hazardous material; this dust must be suppressed soften and absorb polishing media, especially
by sufficient coolant and cutting fluid. OSHA and diamond particles. The extender used is a function
EPA handling requirements will supersede any of the polishing medium, and is usually either
technical handling or use requirements. The beryllia deionized water or a special polishing oil.
dust mixed with the fluid is defined as a hazardous 4. Pressure: Polishing pressure should be very light.
material; this aspect must be considered during Excessive pressure causes excessive surface relief
disposal. 5. Direction: Coarse polishing can be done either of
5. Viewing Window: Often during precision grinding it two ways. Trial and error will indicate which is best
is helpful to look clearly at the sample from above. for you, and results may vary for different types of
This can be accomplished by grinding and polishing samples. Omni-directional polishing involves
a flat area on the surface of the epoxy perpendicular rotating the sample around the polishing wheel
to the sectioning plane. Some automatic equipment either counter to, or with the wheel rotation. In this
does not allow mounting of these irregularly shaped way the polishing is performed in all directions.
samples, however. Uni-directional polishing is where the sample is held
6. The hard intermetallic compounds such as Cu6Sn5, stationary, and the polishing scratches are all
Cu3Sn, Ni3Sn2, Ni3Sn7, AuSn, AuSn2, AuSn4, aligned in one direction. This is particularly useful
FeSn, FeSn2, and Ag3Sn can cause grooves and on layered structures. Fine polishing is almost

110
 always performed omni-directionally. Most Table A1-1 Etchants used to highlight Intermetallic
automatic machines function only in the compounds
omni-directional mode. Various Etchants
95 ml H20 7 grams 100 ml 100 ml
A6 Etching Etching is the final step in metallographic FeCl3 H20 NH4OH, 35%
sample preparation. The specimen should be examined 10 ml 10%
Chromic Acid 75 ml HCl 100 ml 100 ml H202,
before the etching step is performed for defects, H202, 3% 3%
inclusions, porosity, cracks, intergranular corrosion, 2 ml HCl 200 ml
intermetallic compound development, and other H20
anomalies. Etching removes a thin layer of abraded 5 ml H2SO4
surface deformation, revealing the microstructural
details of the specimen. Etching requires the use of an
acid or a base to chemically attack the sample surface. 3. Solder: Solder can be chemically etched using a
Many enchants are available for etching a variety of dilute (5% maximum) hydrochloric acid solution, but
materials. The disposal of the wastes generated may be acceptable results can usually be obtained by
a problem due to the presence of heavy metals such as extensive final polishing using extremely light
the chromates and of toxics such as beryllia dust. See pressure. Solder is extremely reactive to most
ASTM E407-70 for safety cautions. The chemicals used etches, and care must be taken not to destroy its
should be USP or NF or better. See ITRI publication structure.
580 for etchants specific to tin and its alloys and for 4. Copper:
photomicrographs of the resulting sample surfaces.  50 ml Ammonium Hydroxide
 50 ml Water
1. Lead-Tin phases: Nital (1–5 ml HNO3 100 ml  3 to 5 gm Ammonium Persulfate
ethanol (95%) or methanol (95%) Immerse 5–40 5. Stainless Steel or Kovar:
seconds in 5% HNO3 solution. To remove stain,  10 gm Copper Sulfate
immerse 25 seconds in 10% HCl-Methanol solution.  50 ml Hydrochloric Acid
2. A variety of etches for Copper-Tin IMC are shown in  50 ml Water
Table A-1:

111
 Appendix B
Dye Penetrant
formulations have specific vacuum reaction
Dye penetrant analysis of BTC packages on printed characteristics.
wiring assemblies can be used to confirm assembly
process parameters and solder joint quality/integrity. Step 4: Dry the Dye Wipe the BTC package with a
The following procedure utilizes a fluorescent dye that laboratory wipe to remove excess dye. Bake the BTC
enhances defect flaws when inspected under UV light. package at 100ºC for a minimum of 30 minutes. Bake
the BTC package at 50 °C to 100 ºC for a minimum of
Step 1: BTC Package Cleaning Prepare the selected 10-30 minutes. The bake time/temperature duration
BTC package of interest by cleaning with an Acetone may require adjustment for your specific dye formulation,
solvent rinse. Fully submerge the BTC package in the BTC packages being tested and/or assemblies with
Acetone and subject the package/solution to 60 second large thermal masses.
duration in an ultrasonic cleaner. Remove the BTC
package from the Acetone solvent solution, use clean Step 5: Freeze the BTC Package It is recommended
compressed air to blow any residual solution from the that the BTC Package be submerged in liquid Nitrogen
component, and bake at 100ºC for 20 minutes to ensure freezing the package allowing for easier pry removal.
that the package is free from residual liquid solvent. Caution should be exercised as liquid nitrogen will burn
This cleaning process is intended to ensure that the skin if direct contact is achieved. A use proper safety
BTC package is free from flux residue and other precaution (gloves, eye protection etc.) is required. The
materials that may impede the penetration of the dye. duration of the BTC package being submerged in the
Liquid N2 is dependant on the package thermal mass.
Step 2: Apply the Dye Submerge the BTC package in
dye penetrant. If full submersion of the BTC package is The liquid N2 will “boil” as the room temperature BTC
not possible or removal of the BTC package from the package is submerged. As the package reaches
printed wiring assembly not possible, lay the printed equilibrium with the liquid nitrogen the boiling action will
wiring assembly flat and apply the penetrant to the edge cease.
of the BTC package to allow the dye to wick beneath
the package body. Ensure that sufficient dye has been Step 6: Remove the BTC Package and Pry Remove
added such that the entire underside of the BTC the BTC package from the liquid nitrogen bath and pry.
package has been covered The BTC package should pry off easily provided the pry
tools are adequate for the package size. Caution should
Step 3: Vacuum After the BTC package has been be exercised during the pry step to insure that a
submerged, apply an external vacuum to draw out air vertical/tensile force and not a horizontal/shear force is
that may be entrapped under the package body. A 60 applied to the BTC package. A shearing force will affect
second duration under vacuum is acceptable; however, the quality of the solder joint fracture surface.
longer durations can be used. Caution should be
exercised during the application of the vacuum as the Step 7: Inspection of Fractured Solder Joints Inspect
dye penetrant will likely boil and splatter. Adjustment of the resulting surfaces and document results. It is
the vacuum intensity can be conducted to minimize the important to inspect both fracture surfaces (PCB and
dye solution boiling. The boiling action of the dye will BTC) for presence of the dye. Figure B1-1 illustrates a
impact the efficiency of the dye to wick and penetrate BTC component and PCB land after undergoing the
small cracks in the BTC package. Note : different dye Dye and Pry procedure:

112
Figure B1-1 BTC Component (left) and PCB (right) after part removal

113