THE DATASHEET OF

SI5335A-B02204-GMR

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 Si5335
W E B -C U STO M I ZA B L E , A NY -F R E Q U E N C Y, A NY -O U T PU T Q UAD
C L O C K G E N E R ATO R / B U FF ER
Features
 Low power MultiSynth™ technology  Independent output voltage per driver:
enables independent, any-frequency 1.5, 1.8, 2.5, or 3.3 V
synthesis of four frequencies  Single supply core with excellent
 Configurable as a clock generator or PSRR: 1.8, 2.5, 3.3 V
clock buffer device  Up to five user-assignable pin
 Three independent, user-assignable, pin- functions simplify system design:
selectable device configurations SSENB (spread spectrum control),
 Highly-configurable output drivers with RESET, Master OEB or OEB per pin,
up to four differential outputs, eight and Frequency plan select
single-ended clock outputs, or a (FS1, FS0)
Ordering Information:
combination of both  Loss of signal alarm
 Low phase jitter of 0.7 ps RMS  PCIe Gen 1/2/3/4 common clock See page 41.
 Flexible input reference: compliant
External crystal: 25 or 27 MHz  PCIe Gen 3 SRNS Compliant
CMOS input: 10 to 200 MHz  Two selectable loop bandwidth Pin Assignments
SSTL/HSTL input: 10 to 350 MHz settings: 1.6 MHz or 475 kHz
Differential input: 10 to 350 MHz  Easy to customize with web-based
 Independently configurable outputs utility
support any frequency or format:  Small size: 4 x 4 mm, 24-QFN Top View

RSVD_GND
LVPECL/LVDS/CML: 1 to 350 MHz  Low power (core):

VDDO0
CLK0B
CLK0A
HCSL: 1 to 250 MHz

VDD
45 mA (PLL mode)

P2
CMOS: 1 to 200 MHz 12 mA (Buffer mode) 24 23 22 21 20 19
SSTL/HSTL: 1 to 350 MHz  Wide temperature range: –40 to XA/CLKIN 1 18 CLK1A

+85 °C XB/CLKINB 2 17 CLK1B

Applications P3 3
GND
GND
16 VDDO1

GND 4 Pad
15 VDDO2
 Ethernet switch/router  Processor and FPGA clocking
P5 5 14 CLK2A
 PCI Express Gen 1/2/3/4  MSAN/DSLAM/PON
 PCIe jitter attenuation  Fibre Channel, SAN P6 6
7 8 9 10 12
13 CLK2B
11
 DSL jitter attenuation  Telecom line cards

P1
VDDO3
VDD

CLK3B

CLK3A
LOS

 Broadcast video/audio timing  1 GbE and 10 GbE

Description
The Si5335 is a highly flexible clock generator capable of synthesizing four completely
non-integer-related frequencies up to 350 MHz. The device has four banks of outputs
with each bank supporting one differential pair or two single-ended outputs. Using
Skyworks Solutions' patented MultiSynth fractional divider technology, all outputs are
guaranteed to have 0 ppm frequency synthesis error regardless of configuration,
enabling the replacement of multiple clock ICs and crystal oscillators with a single
device. The Si5335 supports up to three independent, pin-selectable device
configurations, enabling one device to replace three separate clock generators or
buffer ICs. To ease system design, up to five user-assignable and pin-selectable
control pins are provided, supporting PCIe-compliant spread spectrum control, master
and/or individual output enables, frequency plan selection, and device reset. Two
selectable PLL loop bandwidths support jitter attenuation in applications, such as PCIe
and DSL. Through its flexible ClockBuilder Pro web configuration utility, factory-
customized, pin-controlled devices are available in two weeks without minimum order
quantity restrictions.
Measuring PCIe clock jitter is quick and easy with the Skyworks Solutions PCIe Clock
Jitter Tool. Download it for free at https://www.skyworksinc.com/en/Application-
Pages/PCI-Express-Learning-Center.

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Si5335
Functional Block Diagram

Osc VDDO0
PLL Bypass
CLK0A
XA / CLKIN ÷MultiSynth0
CLK0B
XB / CLKINB PLL
PLL Bypass OEB0
VDDO1
CLKIN
CLK1A
÷MultiSynth1
CLK1B
Programmable PLL Bypass OEB1
Pin Function VDDO2
P1
Options: CLK2A
P2 ÷MultiSynth2
P3 OEB0/1/2/3 CLK2B
P5 OEB_all Control
PLL Bypass OEB2
P6 SSENB VDDO3
FS[1:0] CLK3A
RESET ÷MultiSynth3
CLK3B
LOS
OEB3

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 Si5335
TA B L E O F C O N T E N T S

Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Typical PCIe System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2. MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3. ClockBuilder Web-Customization Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6. Multi-Function Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8. Frequency Select/Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8. Loop Bandwidth Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9. Applications of the Si5335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3. Configurable Universal Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.1. Si5335 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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Si5335
1. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA –40 25 85 °C
2.97 3.3 3.63 V
Core Supply Voltage VDD 2.25 2.5 2.75 V
1.71 1.8 1.98 V
Output Buffer Supply VDDOn 1.4 — 3.63 V
Voltage
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

100 MHz on all outputs,
Core Supply Current
IDDCG 25 MHz refclk, — 45 60 mA
(Clock Generator Mode)
clock generator mode
Core Supply Current
IDDB 50 MHz refclk — 12 — mA
(Buffer Mode)
LVPECL, 350 MHz — — 30 mA
CML, 350 MHz — 12 — mA
LVDS, 350 MHz — — 8 mA
HCSL, 250 MHz
— — 20 mA
2 pF load
SSTL, 350 MHz — — 19 mA
CMOS, 50 MHz
— 6 9 mA
Output Buffer Supply Current IDDOx 15 pF load1
CMOS, 200 MHz1,2
— 13 18 mA
3.3 V VDD0
CMOS, 200 MHz1,2
— 10 14 mA
2.5 V
CMOS, 200 MHz1,2
— 7 10 mA
1.8 V
HSTL, 350 MHz — — 19 mA
Notes:
1. Single CMOS driver active.
2. Measured into a 5” 50  trace with 2 pF load.

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 Si5335

Table 3. Performance Characteristics

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

PLL Acquisition Time tACQ 1.6 MHz loop bandwidth — — 25 ms

475 kHz or 1.6 MHz loop

PLL Tracking Range fTRACK 5000 20000 — ppm
bandwidth

fBW1 High bandwidth option — 1.6 — MHz

PLL Loop Bandwidth
fBW2 Low bandwidth option — 475 — kHz

MultiSynth Frequency fRES Output frequency < Fvco/8 0 0 1 ppb

Synthesis Resolution
CLKIN Loss of Signal Detect tLOS — 2.6 5 µs
Time
CLKIN Loss of Signal Release tLOSRLS 0.01 0.2 1 µs
Time
POR to Output Clock Valid tRDY — — 2 ms

Input-to-Output Propagation tPROP Buffer Mode — 2.5 4 ns

Delay (PLL Bypass)
Reset Minimum Pulse Width tRESET — — 200 ns

Output-Output Skew1 tDSKEW FOUT > 5 MHz — — 100 ps

Spread Spectrum PP SSDEV FOUT = 100 MHz — –0.45 –0.5 %

Frequency Deviation2
Spread Spectrum Modulation SSDEV FOUT = 100 MHz 30 31.5 33 kHz
Rate3
Notes:
1. Outputs at integer-related frequencies and using the same driver format.
2. Default value is 0.5% down spread.
3. Default value is 31.5 kHz for PCI compliance.

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Si5335

Table 4. Input and Output Clock Characteristics

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Clock (AC Coupled Differential Input Clocks on Pins 1 and 2)1
Frequency fIN LVDS, LVPECL, 102 — 350
MHz
HCSL, CML
Differential Voltage VPP 350 MHz input 0.4 — 2.4
VPP
Swing
Rise/Fall Time3 tR/tF 20%–80% — — 1.0 ns
DC
(PLL < 1 ns tR/tF 40 — 60 %
mode)
Duty Cycle3 DC
(PLL
< 1 ns tR/tF 45 — 55 %
bypass
mode)
Input Impedance1 RIN 10 — — k
Input Capacitance CIN — 3.5 — pF
Input Clock (AC-Coupled Single-Ended Input Clock on Pin 1)
Frequency fIN CMOS, HSTL, SSTL 102 — 200 MHz
CMOS Input Voltage
VI 200 MHz 0.8 — 1.2 Vpp
Swing
CMOS Rise/Fall Time tR/tF 10%–90% — — 4 ns
CMOS Rise/Fall Time tR/tF 20%–80% — — 2.3 ns
HSTL/SSTL Input VI(HSTL/
200 MHz 0.4 — 1.2 VPP
Voltage SSTL)
HSTL/SSTL Rise/Fall
tR/tF 10%–90% — — 1.4 ns
Time
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"
on page 19.
2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on
pins 1 and 2 faster than 0.3 V/ns.
4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See
"3.10.6. CML Outputs" on page 31.
5. Includes effect of internal series 22  resistor.

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 Si5335
Table 4. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

DC
(PLL < 1 ns tR/tF 40 — 60 %
mode)
Duty Cycle DC
(PLL
< 1 ns tR/tF 45 — 55 %
bypass
mode)
Input Capacitance CIN — 3.5 — pF
Output Clocks (Differential)
LVPECL, LVDS, CML 1 — 350 MHz
Frequency fOUT
HCSL 1 — 250 MHz
VDDO–
VOC common mode — — V
LVPECL 1.45 V
Output Voltage peak-to-peak single-
VSEPP 0.55 0.8 0.96 VPP
ended swing
VOC common mode 1.125 1.2 1.275 V
LVDS Output Voltage
(2.5/3.3 V) peak-to-peak single-
VSEPP 0.25 0.35 0.45 VPP
ended swing
VOC common mode 0.8 0.875 0.95 V
LVDS Output
Voltage (1.8 V) peak-to-peak single-
VSEPP 0.25 0.35 0.45 VPP
ended swing
VOC common mode 0.35 0.375 0.400 V
HCSL Output Voltage peak-to-peak single-
VSEPP 0.575 0.725 0.85 VPP
ended swing
VOC Common Mode — See Note 4 — V
CML Output Voltage Peak-to-Peak Single-
VSEPP 0.67 0.860 1.07 VPP
ended Swing
20% to 80%
Rise/Fall Time tR/tF LVPECL, LVDS, — — 450 ps
HCSL, CML
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"
on page 19.
2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on
pins 1 and 2 faster than 0.3 V/ns.
4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See
"3.10.6. CML Outputs" on page 31.
5. Includes effect of internal series 22  resistor.

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Si5335
Table 4. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

LVPECL, LVDS,
Duty Cycle DC 45 — 55 %
HCSL, CML
Output Clocks (Single-Ended)
CMOS 1 — 200 MHz
Frequency fOUT
SSTL, HSTL 1 — 350 MHz
CMOS 20%–80%
tR/tF 2 pF load — 0.45 0.85 ns
Rise/Fall Time
CMOS 20%–80%
tR/tF 15 pF load — — 2.0 ns
Rise/Fall Time

CMOS VOH 4 mA load VDDO – 0.3 — V

Output Voltage5 VOL 4 mA load — 0.3 V
CMOS
— 50 — 
Output Resistance5
HSTL, SSTL
20%–80% tR/tF See Figure 16. — 0.35 — ns
Rise/Fall Time
VOH 0.5xVDDO+0.3 — — V
HSTL Output Voltage VDDO = 1.4 to 1.6 V
VOL — — 0.5xVDDO –0.3 V
VOH SSTL-3 0.45xVDDO+0.41 — — V
VDDOx = 2.97 to
VOL 3.63 V — — 0.45xVDDO–0.41 V

VOH SSTL-2 VDDOx = 0.5xVDDO+0.41 — — V

SSTL Output Voltage
VOL 2.25 to 2.75 V — — 0.5xVDDO–0.41 V
VOH SSTL-18 0.5xVDDO+0.34 — V
VDDOx = 1.71 to
VOL 1.98 V — — 0.5xVDDO–0.34 V

HSTL, SSTL
— 50 — 
Output Resistance
Duty Cycle DC 45 — 55 %
Notes:
1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"
on page 19.
2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer
mode, but loss-of-signal (LOS) status is not functional.
3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on
pins 1 and 2 faster than 0.3 V/ns.
4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See
"3.10.6. CML Outputs" on page 31.
5. Includes effect of internal series 22  resistor.

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 Si5335

Table 5. Control Pins*

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Condition Min Typ Max Unit

Input Control Pins (P1, P2, P3, P5*, P6*)
Pins P1, P2, P3 –0.1 — 0.3 x VDD V
Input Voltage Low VIL
Pins P5 and P6 — — 0.3 V
Pins P1, P2, P3 0.7 x VDD — 3.73 V
Input Voltage High VIH
Pins P5* and P6* 0.85 — 1.2 V

Input Capacitance CIN — — 4 pF

Input Resistance RIN — 20 — k

Output Control Pins (LOS, Pin 8)

Output Voltage Low VOL ISINK = 3 mA 0 — 0.4 V

Rise/Fall Time 20–80% tR/tF CL < 10 pf, pull up  1 k — — 10 ns

*Note: For more information, see "3.6.1. P5 and P6 Input Control" on page 24.

Table 6. Crystal Specifications for 25 MHz

Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL — 25 — MHz

Load Capacitance (on-chip differential) cL — 18 — pF

Crystal Output Capacitance cO — — 5 pF

Equivalent Series Resistance rESR — — 100 

Crystal Max Drive Level dL 100 — — µW

Table 7. Crystal Specifications for 27 MHz

Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL — 27 — MHz

Load Capacitance (on-chip differential) cL — 18 — pF

Crystal Output Capacitance cO — — 5 pF

Equivalent Series Resistance rESR — — 75 

Crystal Max Drive Level dL 100 — — µW

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Si5335

Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)1,2,3
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

GbE Random Jitter CLKIN = 25 MHz
JGbE — 0.7 1 ps RMS
(12 kHz–20 MHz)4 All CLKn at 125 MHz5
GbE Random Jitter CLKIN = 25 MHz
RJGbE — 0.38 0.79 ps RMS
(1.875–20 MHz) All CLKn at 125 MHz5
CLKIN = 19.44 MHz
OC-12 Random Jitter
JOC12 All CLKn at — 0.7 1 ps RMS
(12 kHz–5 MHz)
155.52 MHz5
PCI Express 1.1 Common
Clocked (with spread Total Jitter6 — 20.1 33.6 ps pk-pk
spectrum)
RMS Jitter6, 10 kHz to
PCI Express 2.1 Common — 0.15 1.47 ps RMS
1.5 MHz
Clocked (no spread spec-
trum) RMS Jitter6, 1.5 MHz to
— 0.58 0.75 ps RMS
50 MHz
PCI Express 3.0 Common
Clocked (no spread RMS Jitter6 — 0.15 0.45 ps RMS
spectrum)
PCIe Gen 3 Separate PLL BW of 2–4 or
Reference No Spread, 2–5 MHz, — 0.11 0.32 ps RMS
SRNS CDR = 10 MHz
PLL BW of 2–4 or
PCIe Gen 4,
2–5 MHz, — 0.15 0.45 ps RMS
Common Clock
CDR = 10 MHz

Period Jitter JPER N = 10,000 cycles7 — 10 30 ps pk-pk

Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Skyworks
Solutions for support to validate your configuration and ensure the best jitter performance. In many configurations,
CMOS outputs have little to no effect upon jitter.
3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the
differential clock input slew rates greater than 0.3 V/ns.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
7. For any output frequency > 10 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
11. Download the Skyworks Solutions PCIe Clock Jitter Tool at https://www.skyworksinc.com/en/Application-Pages/PCI-
Express-Learning-Center.

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 Si5335
Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)1,2,3 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

N = 10,000 cycles
JCC Output MultiSynth — 9 29 ps pk8
Cycle-Cycle Jitter
operated in integer or
fractional mode7
Output and feedback
Random Jitter
RJ MultiSynth in integer or — 0.7 1.5 ps RMS
(12 kHz–20 MHz)
fractional mode7
Output MultiSynth
operated in fractional — 3 15 ps pk-pk
mode7
Deterministic Jitter DJ
Output MultiSynth
operated in integer — 2 10 ps pk-pk
mode7
Output MultiSynth
operated in fractional — 13 36 ps pk-pk
Total Jitter TJ = DJ+14xRJ mode7
(12 kHz–20 MHz) (See Note 9) Output MultiSynth
operated in integer — 12 20 ps pk-pk
mode7
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Skyworks
Solutions for support to validate your configuration and ensure the best jitter performance. In many configurations,
CMOS outputs have little to no effect upon jitter.
3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the
differential clock input slew rates greater than 0.3 V/ns.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
7. For any output frequency > 10 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
11. Download the Skyworks Solutions PCIe Clock Jitter Tool at https://www.skyworksinc.com/en/Application-Pages/PCI-
Express-Learning-Center.

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Si5335

Table 9. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 475 kHz)1,2
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

CLKIN = 70.656 MHz
DSL Random Jitter
RJDSL1 All CLKn at — 0.8 2 ps RMS
(10 kHz–400 kHz)
70.656 MHz4
CLKIN = 70.656 MHz
DSL Random Jitter
RJDSL2 All CLKn at — 0.9 2 ps RMS
(100 kHz–10 MHz)
70.656 MHz4
CLKIN = 70.656 MHz
DSL Random Jitter
RJDSL3 All CLKn at — 1.95 2.2 ps RMS
(10 Hz–30 MHz)
70.656 MHz4
PCI Express 1.1
Common Clocked Total Jitter5 — 20 34 ps pk-pk
(with spread spectrum)
RMS Jitter5, 10 kHz to
PCI Express 2.1 — 0.3 0.5 ps RMS
1.5 MHz
Common Clocked
(no spread spectrum) RMS Jitter5, 1.5 MHz to
— 0.5 1.0 ps RMS
50 MHz
PCI Express 3.0
Common Clocked RMS Jitter5 — 0.15 0.45 ps RMS
(no spread spectrum)
PCIe Gen 3 Separate PLL BW of 2–4 or
Reference No Spread, 2–5 MHz, — 0.11 0.32 ps RMS
SRNS CDR = 10 MHz
PLL BW of 2–4 or
PCIe Gen 4,
2–5 MHz, — 0.15 0.45 ps RMS
Common Clock
CDR = 10 MHz

Period Jitter JPER N = 10,000 cycles6 — 10 30 ps pk-pk

Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Skyworks
Solutions for support to validate your configuration and ensure the best jitter performance. In many configurations,
CMOS outputs have little to no effect upon jitter.
3. DJ for PCI and GbE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
6. For any output frequency > 5 MHz.
7. Measured in accordance with JEDEC standard 65.
8. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
9. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
10. Download the Skyworks Solutions PCIe Clock Jitter Tool at https://www.skyworksinc.com/en/Application-Pages/PCI-
Express-Learning-Center.

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 Si5335
Table 9. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 475 kHz)1,2 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

N = 10,000 cycles
JCC Output MultiSynth — 9 29 ps pk7
Cycle-Cycle Jitter
operated in integer or
fractional mode6
Output and feedback
Random Jitter
RJ MultiSynth in integer or — 1 2.5 ps RMS
(12 kHz–20 MHz)
fractional mode6
Output MultiSynth
operated in fractional — 3 15 ps pk-pk
6
mode
Deterministic Jitter DJ
Output MultiSynth
operated in integer — 2 10 ps pk-pk
6
mode
Output MultiSynth
operated in fractional — 13 36 ps pk-pk
Total Jitter TJ = DJ+14xRJ mode6
(12 kHz–20 MHz) (See Note 8) Output MultiSynth
operated in integer — 15 30 ps pk-pk
mode6
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Skyworks
Solutions for support to validate your configuration and ensure the best jitter performance. In many configurations,
CMOS outputs have little to no effect upon jitter.
3. DJ for PCI and GbE is < 5 ps pp
4. Output MultiSynth in Integer mode.
5. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.
6. For any output frequency > 5 MHz.
7. Measured in accordance with JEDEC standard 65.
8. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
9. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
10. Download the Skyworks Solutions PCIe Clock Jitter Tool at https://www.skyworksinc.com/en/Application-Pages/PCI-
Express-Learning-Center.

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Si5335

Table 10. itter Specifications, Clock Buffer Mode (PLL Bypass)*

(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

0.7 V pk-pk differential input
Additive Phase Jitter clock at 350 MHz with — 0.165 — ps RMS
tRPHASE
(12 kHz–20 MHz) 70 ps rise/fall time
0.7 V pk-pk differential input
Additive Phase Jitter clock at 350 MHz with — 0.225 — ps RMS
tRPHASEWB
(50 kHz–80 MHz) 70 ps rise/fall time

*Note: All outputs are in Clock Buffer mode (PLL Bypass).

Table 11. Typical Phase Noise Performance

Offset Loop 25 MHz XTAL 27 MHz Ref In 19.44 MHz Ref In 100 MHz Ref In Units
Frequency Bandwidth to 156.25 MHz to 148.3517 MHz to 155.52 MHz to 100 MHz
100 Hz 1.6 MHz –90 –87 –110 –115 dBc/Hz
475 kHz N/A* –91 –91 –113 dBc/Hz
1 kHz 1.6 MHz –120 –117 –116 –122 dBc/Hz
475 kHz N/A* –112 –111 –122 dBc/Hz
10 kHz 1.6 MHz –126 –123 –123 –128 dBc/Hz
475 kHz N/A* –124 –122 –127 dBc/Hz
100 kHz 1.6 MHz –132 –130 –128 –136 dBc/Hz
475 kHz N/A* –122 –121 –124 dBc/Hz
1 MHz 1.6 MHz –132 –132 –128 –136 dBc/Hz
475 kHz N/A* –133 –131 –135 dBc/Hz
10 MHz 1.6 MHz –145 –145 –145 –152 dBc/Hz
475 kHz N/A* –152 –153 –152 dBc/Hz
*Note: XTAL input mode does not support the 475 kHz loop bandwidth setting.

Table 12. Thermal Characteristics

Parameter Symbol Test Condition Value Unit

Thermal Resistance JA Still Air 37 °C/W
Junction to Ambient
Thermal Resistance JC Still Air 25 °C/W
Junction to Case

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 Si5335

Table 13. Absolute Maximum Ratings1

Parameter Symbol Test Condition Value Unit

DC Supply Voltage VDD –0.5 to 3.8 V
Input Voltage VIN Pins: XA/CLKIN, –0.5 to 1.3 V
XB/CLKINB, P5, P6
Pins: P1, P2, P3 –0.5 to 3.8 V
Storage Temperature Range TSTG –55 to 150 °C
ESD Tolerance HBM 2.5 kV
(100 pF, 1.5 k)
ESD Tolerance CDM 550 V
ESD Tolerance MM 175 V
Latch-up Tolerance JESD78 Compliant
Junction Temperature TJ 150 °C
Peak Soldering Reflow Temperature2 260 °C
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. Refer to JEDEC J-STD-020 standard for more information.

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Si5335
2. Typical PCIe System Diagram

Main Peripheral
Board Board

PCIe
Core
PCIe
Link FPGA
FPGA B

Backplane
PCIe
A Link
PCIe PCIe
Core Switch

125MHz
LVDS FPGA
PCIe C
Si5335 100MHz HCSL Link PCIe
Clock 25MHz LVPECL Core
Generator
25MHz LVPECL
Peripheral
Board

Figure 1. PCI Express Switching Application Example

Figure 1 shows the Si5335 in a PCI Express application using the common clock topology. The Si5335 provides
reference clocks to the three FPGAs, each of which requires a different clock signaling format (LVDS, LVPECL),
I/O voltage (1.8, 2.5, 3.3 V), or frequency (25, 100, 125 MHz). In addition, the Si5335 provides a PCIe compliant,
100 MHz HCSL reference clock to the PCIe switch.

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 Si5335
3. Functional Description

Osc
PLL Bypass VDDO0
CLK0A
XA / CLKIN ÷MultiSynth0
CLK0B
XB / CLKINB PLL
PLL Bypass OEB0
VDDO1
CLKIN
CLK1A
÷MultiSynth1
CLK1B
Programmable PLL Bypass OEB1
Pin Function VDDO2
P1
Options: CLK2A
P2 ÷MultiSynth2
P3 OEB0/1/2/3 CLK2B
P5 OEB_all Control
PLL Bypass OEB2
P6 SSENB VDDO3
FS[1:0] CLK3A
RESET ÷MultiSynth3
CLK3B
LOS
OEB3

Figure 2. Si5335 Functional Block Diagram

3.1. Overview
The Si5335 is a high-performance, low-jitter clock generator or buffer capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz. The device supports free-run operation using an external 25
or 27 MHz crystal, or it can lock to an external clock for generating synchronous clocks. The output drivers support
four differential clocks or eight single-ended clocks or a combination of both. The output drivers are configurable to
support common signal formats, such as LVPECL, LVDS, HCSL, CML, CMOS, HSTL, and SSTL. Separate output
supply pins allow supply voltages of 3.3, 2.5, 1.8, and 1.5 V to support the multi-format output driver. The core
voltage supply accepts 3.3, 2.5, or 1.8 V and is independent from the output supplies. Using its two-stage
synthesis architecture and patented high-resolution MultiSynth technology, the Si5335 can generate four
independent frequencies from a single input frequency. In addition to clock generation, the inputs can bypass the
synthesis stage enabling the Si5335 to be used as a high-performance clock buffer.
Spread spectrum* is available on each of the clock outputs for EMI-sensitive applications, such as PCI Express.
The device includes an interrupt pin that monitors for both loss of PLL lock (LOL) and loss of input signal (LOS)
conditions while configured in clock generator mode. In clock generator mode, the LOS pin is asserted whenever
LOL or LOS is true. In clock buffer mode (i.e., when the PLL is bypassed), the LOS pin is asserted whenever the
input clock is lost. The LOL condition does not apply in clock buffer mode.
*Note: See " Document Change List" on page 46 for more information.

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Si5335
3.2. MultiSynth Technology
Next-generation timing architectures require a wide range of frequencies which are often non-integer related.
Traditional clock architectures address this by using a combination of single PLL ICs, 4-PLL ICs and discrete XOs,
often at the expense of BOM complexity and power. The Si5335 uses patented MultiSynth technology to
dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops
(PLLs) in a single device, greatly minimizing size and power requirements versus traditional solutions. Based on a
fractional-N PLL, the heart of the architecture is a low phase noise, high-frequency VCO. The VCO supplies a high
frequency output clock to the MultiSynth block on each of the four independent output paths. Each MultiSynth
operates as a high-speed fractional divider with Skyworks Solutions' proprietary phase error correction to divide
down the VCO clock to the required output frequency with very low jitter.
The first stage of the MultiSynth architecture is a fractional-N divider which switches seamlessly between the two
closest integer divider values to produce the exact output clock frequency with 0 ppm error. To eliminate phase
error generated by this process, MultiSynth calculates the relative phase difference between the clock produced by
the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock
waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter
performance. Based on this architecture, the output of each MultiSynth can produce any frequency from 1 to
350 MHz.

MultiSynth

Fractional-N Phase
fVCO Divider Adjust fOUT

Phase Error
Calculator

Divider Select
(DIV1, DIV2)
Figure 3. Skyworks Solutions' MultiSynth Technology
3.3. ClockBuilder Web-Customization Utility
ClockBuilder is a web-based utility available at https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-
Pro-Software that allows hardware designers to tailor the Si5335’s flexible clock architecture to meet any
application-specific requirements and order custom clock samples. Through a simple point-and-click interface,
users can specify any combination of input frequency and output frequencies and generate a custom part number
for each application-specific configuration. There are no minimum order quantity restrictions.
ClockBuilder enables mass customization of clock generators. This allows a broader range of applications to take
advantage of using application-specific pin controlled clocks, simplifying design while eliminating the firmware
development required by traditional I2C-programmable clock generators.
Based on Skyworks Solutions’ patented MultiSynth technology, the device PLL output frequency is constant and all
clock output frequencies are synthesized by the four MultiSynth fractional dividers. All PLL parameters, including
divider settings, VCO frequency, loop bandwidth, charge pump current, and phase margin are internally set by the
device during the configuration process. This ensures optimized jitter performance and loop stability while
simplifying design.

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 Si5335
3.4. Input Configuration
The Si5335 input can be driven from either an external crystal or a reference clock. Reference selection is made
when the device configuration is specified using the ClockBuilder™ web-based utility available at
https://www.skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software.
3.4.1. Crystal Input
If the crystal input option is used, the Si5335 operates as a free-running clock generator. In this mode of operation
the device requires a low-cost 25 or 27 MHz fundamental mode crystal connected across XA and XB as shown in
Figure 4. Given the Si5335’s frequency flexibility, the same 25 or 27 MHz crystal can be reused to generate any
combination of output frequencies. Custom frequency crystals are not required. The Si5335 integrates the crystal
load capacitors on-chip to reduce external component count. The crystal should be placed very close to the device
to minimize stray capacitance. To ensure stable oscillation, the recommended crystal specifications provided in
Tables 6 and 7 must be followed. See AN360 for additional details regarding crystal recommendations.

Si5335

XA/CLKIN
XTAL
XB/CLKINB

Figure 4. Connecting an XTAL to the Si5335

3.4.2. Differential Input Clocks
The multi-format differential clock inputs of the Si5335 will interface with today’s most common differential signals,
such as LVDS, LVPECL, CML, and HCSL. The differential inputs are internally self-biased and must be ac-coupled
externally with a 0.1 µF capacitor. The receiver will accept a signal with a voltage swing between 400 mV and
2.4 VPP differential. Each half of the differential signal must not exceed 1.2 VPP at the input to the Si5335 or else
the 1.3 V dc voltage limit may be exceeded.
3.4.2.1. LVDS Inputs
When interfacing the Si5335 device to an LVDS signal, a 100  termination is required at the input along with the
required dc blocking capacitors as shown in Figure 5.

Must be ac coupled
Keep termination close to
input pin of the Si5335
0.1 uF
Si5335
50
Pin 1
100
Pin 2
50
LVDS
0.1 uF

Figure 5. LVDS Input Signal

3.4.2.2. LVPECL Input Clocks
Recommended configurations for interfacing an LVPECL input signal to the Si5335 are shown in Figure 6. Typical
values for the bias resistors (Rb) range between 120 and 200  depending on the LVPECL driver. The 100 
resistor provides line termination. Because the receiver is internally self-biased, no additional external bias is
required.

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Si5335
Another solution is to terminate the LVPECL driver with a Thevenin configuration as shown in Figure 6b. The
values for R1 and R2 are calculated to provide a 50 termination to VDD-2V. Given this, the recommended resistor
values are R1 = 127 and R2 = 82.5  for VDD = 3.3 V, and R1 = 250 andR2 = 62.5 for VDD = 2.5 V.

Keep termination close to

input pin of the Si5335
3.3 V, 2.5 V 0.1 uF
Si5335
50
Pin 1
100
Pin 2
50
LVPECL
0.1 uF
Rb Rb
Must be ac coupled

LVPECL Input Signal with Source Biasing Option

Keep termination close to VDD VDD
input pin of the Si5335 Must be ac coupled
R1 R1
VDD= 3.3 V, 2.5 V
0.1 uF Si5335
50 Pin 1

50 Pin 2
LVPECL
0.1 uF
R2 R2

VT = VDD – 2 V
R1 // R2 = 50 Ohm

LVPECL Input Signal with Load Biasing Option

Figure 6. Recommended Options for Interfacing to an LVPECL Input Signal

Since the differential receiver of the Si5335 is internally self biased, an LVPECL signal may not be dc-coupled to
the device. Figure 7 shows some common LVPECL connections that should not be used because of the dc levels
they present at the receiver’s input.

VDD VDD V DD V DD
DC Coupled with
AC Coupled with
Thevenin Termination R1 R1 R1
R1 Thevenin Re-Biasing

50 50

50 50
LVPECL LVPECL
R2 R2 Rb Rb R2 R2

Not Recommended
Figure 7. Common LVPECL Connections that May be Destructive to the Si5335 Input

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 Si5335
3.4.2.3. CML Input Clocks
CML signals may be applied to the differential inputs of the Si5335. Since the Si5335 differential inputs are
internally self-biased, a CML signal may not be dc-coupled to the device.
The recommended configurations for interfacing a CML input signal to the Si5335 are shown in Figure 8. The
100  resistor provides line termination, and, since the receiver is internally-biased, no additional external biasing
components are required.

Keep termination close to

input pin of the Si5335

0.1 uF

50
Si5335
Pin 1
100
Pin 2
CML 50

0.1 uF

Must be ac coupled

Figure 8. CML Input Signal

3.4.2.4. HCSL Input Clocks
A typical HCSL driver has an open source output, which requires an external series resistor and a resistor to
ground. The values of these resistors depend on the driver but are typically equal to 33  (Rs) and 50  (Rt). Note
that the HCSL driver in the Si5335 requires neither Rs nor Rt resistors. Other than two ac-coupling capacitors, no
additional external components are necessary when interfacing an HCSL signal to the Si5335.

Must be ac coupled

3.3V, 2.5V, 1.8V 0.1 uF

Rs
Si5335
50
Pin 1

Rs Pin 2
50
HCSL
0.1 uF
Rt Rt

Figure 9. HCSL Input Signal to Si5335

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Si5335
3.4.3. Single-Ended CMOS Input Clocks
For synchronous timing applications, the Si5335 can lock to a 10 to 200 MHz CMOS reference clock. A typical
interface circuit is shown in Figure 10. A series termination resistor may be required if the CMOS driver impedance
does not match the trace impedance.

Keep R se and Rsh close to

the receiver

0.1 uF
Rse Si5335
CMOS Input Signal 50
Pin 1

1.8 V CMOS Rsh

3.3 V CMOS
Pin 2
Rse = 249  Rse = 499 
Rsh = 464  Rsh = 274 

2.5 V CMOS 0.1 uF

Rse = 402 
Rsh = 357 

Figure 10. Interfacing CMOS Reference Clocks to the Si5335

3.4.4. Single-Ended SSTL and HSTL Input Clocks
HSTL and SSTL single-ended inputs can be input to the differential inputs, pins 1 and 2, of the Si5335 with the
circuit shown in Figure 11.
Some drivers may require a series 25  resistor. If the SSTL/HSTL input is being driven by another Si5335 device,
the 25  series resistor is not required as this is integrated on-chip. The maximum recommended input frequency
in this case is 350 MHz.

Keep termination close to

input pin of the Si5335 VTT

50
0.1 uF Si5335
0.4 to 1.2 V pk-pk 50
Pin 1
Differential
VDD
Input
Pin 2

R1
0.1 uF
VTT

R2
0.1 uF
SSTL_2, SSTL_18, HSTL
R1 = 2.43 k
R2 = 2 k

SSTL_3
R1 = 2.43 k
R2 = 2 k
Figure 11. Single-Ended SSTL/HSTL Input Clocks to the Si5335

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 Si5335
3.4.5. Applying a Single-Ended Clock to the Differential Input Clock Pins
It is possible to interface any single-ended clock signal to the differential input pins (XA/CLKIN, XB/CLKINB). The
recommended interface for a signal that requires a 50  load is shown in Figure 12. On these inputs, it is important
that the signal level be less than 1.2 VPP SE and greater than 0.4 VPP SE. The maximum recommended input
frequency in this case is 350 MHz.

Keep termination close to

input pin of the Si5335
0.1 uF
Si5335
0.4 to 1.2V pk-pk 50
Pin 1
50
Pin 2

0.1 uF

Figure 12. Single-Ended Input Signal with 50  Termination

3.5. Input and Output Frequency Configuration
The Si5335 utilizes a single PLL-based architecture, four independent MultiSynth fractional output dividers, and a
MultiSynth fractional feedback divider such that a single device provides the clock generation capability of 4
independent PLLs. Unlike competitive multi-PLL solutions, the Si5335 can generate four unique non-integer
related output frequencies with 0 ppm frequency error for any combination of output frequencies. In addition, any
combination of output frequencies can be generated from a single reference frequency without having to change
the crystal or reference clock frequency between frequency configurations.
The Si5335 frequency configuration is set when the device configuration is specified using the ClockBuilder Pro
web-based utility. Any combination of output frequencies ranging from 1 to 350 MHz can be configured on each of
the device outputs. Up to three unique device configurations can be specified in a single device, enabling the
Si5335 to replace 3 different clock generators or clock buffers.
3.6. Multi-Function Control Inputs
The Si5335 supports five user-defined input pins (pins 3, 5, 6, 12, 19) that are customizable to support the
functions listed below. The pinout of each device is customized using the ClockBuilder utility. This enables the
device to be custom tailored to a specific application. Each of the different functions is described in further detail
below.

Table 14. Multi-Function Control Inputs

Pin Function Description Assignable Pin Name
OEB_all Output Enable All. P1, P2, P3, P5*, P6*
All outputs enabled when low.
OEB0 Output Enable Bank 0. P1, P2, P3, P5*, P6*
CLK0A/0B enabled when low.
OEB1 Output Enable Bank 1. P1, P2, P3, P5*, P6*
CLK1A/1B enabled when low.
OEB2 Output Enable Bank 2. P1, P2, P3, P5*, P6*
CLK2A/2B enabled when low.
OEB3 Output Enable Bank 3. P1, P2, P3, P5*, P6*
CLK3A/3B enabled when low.

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Si5335
Table 14. Multi-Function Control Inputs (Continued)
FS0 Frequency Select. P1
Selects active device frequency plan from factory-configured
profiles. See “3.8. Frequency Select/Device Reset” for more
information.
FS1 Frequency Select. P1 (for 2-plan devices)
Selects active device frequency plan from factory-configured P2 (for 3-plan devices)
profiles. See “3.8. Frequency Select/Device Reset” for more
information.
RESET Reset. P1, P2, P3
Asserting this pin (driving high) is required to change
FS1,FS0 pin setting. Reset is not required if FS1,FS0 pins are
unassigned.
SSENB Spread Spectrum Enable. P1, P2, P3, P5*, P6*
Enables PCI-compliant spread spectrum clocking on all 100
MHz clock outputs when low.
*Note: See “3.6.1. P5 and P6 Input Control” for recommended termination circuits for these pins.

3.6.1. P5 and P6 Input Control

Control input signals to P5 and P6 cannot exceed 1.2 V. When these inputs are driven from CMOS sources, a
resistive attenuator is required for pins 5 and 6, as shown in Figure 13.

Keep Rse and Rsh close to pin 5 and pin 6

Si5335
Rse
CMOS input signal 50 Pin 5, Pin 6

Rsh

1.8 V CMOS 2.5 V CMOS 3.3 V CMOS

Rse = 1 k 1.96 k 3.09 k
Rsh = 1.58 k 1.58 k 1.58 k

Figure 13. P5, P6 Control Pin Termination

3.7. Output Enable
Each of the device’s four banks of clock outputs can be individually disabled using OEB0, OEB1, OEB2 and OEB3,
respectively. Alternatively, all clock outputs can be disabled using the master output enable OEB_all. When a
Si5335 clock output bank is disabled, the output disable state is determined by the configuration specified in the
ClockBuilder web utility. When one or more banks of clock outputs are enabled or disabled, clock start and stop
transitions are handled glitchlessly.
3.8. Frequency Select/Device Reset
The device frequency plan is customized using the ClockBuilder web utility. The Si5335 optionally supports up to
three unique, pin-selectable configurations per device, enabling one device to replace up to three separate clock
ICs. To select a particular frequency plan, set the FS pins as outlined below:
For custom Si5335 devices configured to support two frequency plans, the FS1 pin should be set as follows:

FS1 Profile

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 Si5335
0 1
1 2

For custom Si5335 devices configured to support three frequency plans, the FS1 and FS0 pins should be set as
follows:

FS1 FS0 Profile

0 0 Reserved
0 1 1
1 0 2
1 1 3

If a change is made to the FS pin settings, the device reset pin (RESET) must be held high for the minimum pulse
width specified in Table 3 on page 5 to change the device configuration. The output clocks will be momentarily
squelched until the device begins operation with the new frequency plan.
If the RESET pin is not selected in ClockBuilder as one of the five programmable pins, a power-on reset must be
applied for an FS pin change to take effect.
3.9. Loss-of-Signal Alarm
The Si5335 supports a loss of signal (LOS) output indicator for monitoring the condition of the crystal/clock
reference input. The LOS condition occurs when there is no input clock to the device or the PLL has lost lock (in
clock generator mode). When an input clock is removed, the LOS pin will assert and the output clocks may drift up
to 5% (in clock generator mode). When the input clock with an appropriate frequency is reapplied, the LOS pin will
deassert. In clock buffer mode, LOS is driven high when the input clock is lost.

LOS Output State Description

0 Input clock present and
PLL is locked
1 Input clock not present and
PLL is not locked

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Si5335
3.10. Output Stage
The output stage consists of programmable output drivers as shown in Figure 14.

Output
Stage
VDDO0
CLK0A
CLK0B

From Synthesis Stage

VDDO1
CLK1A

or Input Stage
CLK1B

VDDO2
CLK2A
CLK2B

VDDO3
CLK3A
CLK3B

Figure 14. Output Stage

The Si5335 devices provide four outputs that can be differential or single-ended. When configured as single-
ended, the driver generates two signals that can be configured as in-phase or complementary. Each of the outputs
has its own output supply pin, allowing the device to be used in mixed supply applications without the need for
external level translators. The CML output driver generates a similar output swing as the LVPECL driver but
consumes half the current. CML outputs must be ac-coupled.
3.10.1. CMOS/LVTTL Outputs
The CMOS output driver has a controlled impedance of about 50 , which includes an internal series resistor of
approximately 22 . For this reason, an external Rs series resistor is not recommended when driving 50  traces.
If the trace impedance is higher than 50 , a series resistor, Rs, should be used. A typical configuration is shown in
Figure 15. A CMOS output driver can be configured with ClockBuilder as a single- or dual-output driver. Dual
otuput configurations support in-phase or complementary outputs. The output supports 3.3, 2.5, and 1.8 V CMOS
signal levels when the appropriate voltage is supplied to the external VDDO pin and the device is configured
accordingly.

3.3, 2.5, or 1.8 V

VDDOx
LVTTL/
Si5335 CMOS

CLKxA
50
CMOS CLKxB

50

Figure 15. Interfacing to a CMOS Receiver

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 Si5335
3.10.2. SSTL and HSTL Outputs
The Si5335 supports both SSTL and HSTL outputs, which can be single-ended or differential. The recommended
termination scheme for SSTL is shown in Figure 16. The VTT supply can be generated using a simple voltage
divider as shown below (note that Rt = 50 ).

SSTL (3.3, 2.5, or 1.8 V)

HSTL (1.5 V) VTT VTT

VDDOx SSTL_3
Rt Rt
SSTL_2
Si5335 SSTL_18
50 HSTL
SSTL CLKxA
or CLKxB
HSTL
50
VDDO

R1
VTT
SSTL_2, SSTL_18, HSTL SSTL_3
0.1 µF R2
R1 = 2 k R1 = 2.43 k
R2 = 2 k R2 = 2 k

Figure 16. Interfacing the Si5335 to an SSTL or HSTL Receiver

3.10.3. LVPECL Outputs
The LVPECL driver is configurable in both 3.3 V or 2.5 V standard LVPECL modes. The output driver can be ac-
coupled or dc-coupled to the receiver.
3.10.3.1. DC-Coupled LVPECL Outputs
The standard LVPECL driver supports two commonly used dc-coupled configurations. Both of these are shown in
Figure 17a and Figure 17b. LVPECL drivers were designed to be terminated with 50  to VDD–2 V, which is
illustrated in Figure 17a. VTT can be supplied with a simple voltage divider as shown.
An alternative method of terminating LVPECL is shown in Figure 17b, which is the Thevenin equivalent to the
termination in Figure 17a. It provides a 50  load terminated to VDD–2.0 V. For 3.3 V LVPECL, use R1 = 127 and
R2 = 82.5 ; for 2.5 V LVPECL, use R1 = 250 and R2 = 62.5 The only disadvantage to this type of termination
is that the Thevenin circuit consumes additional power from the VDDO supply.

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Si5335

Keep termination close to

3.3 V, 2.5 V the receiver
VDDOx
50
Si5335 3.3 V LVPECL
2.5 V LVPECL
50
CLKxA
LVPECL CLKxB VTT = VDDO – 2.0
50

50

a. DC-Coupled Termination of 50  to VDDO – 2.0 V

VDDO VDDO Keep termination close to

3.3 V, 2.5 V the receiver
VDDOx R1 R1

Si5335 3.3 V LVPECL

2.5 V LVPECL
CLKxA 50
LVPECL CLKxB
50
3.3 V LVPECL
VT = VDDO – 2.0 V R1 = 127 
R2 R2
R1 // R2 = 50  R2 = 82.5 

2.5 V LVPECL
R1 = 250 
R2 = 62.5 

b. DC-Coupled with Thevenin Termination

Figure 17. Interfacing the Si5335 to an LVPECL Receiver Using DC Coupling

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 Si5335
3.10.3.2. AC Coupled LVPECL Outputs
AC coupling is necessary when a receiver and a driver have compatible voltage swings but different common-
mode voltages. AC coupling works well for dc-balanced signals, such as for 50% duty cycle clocks. Figure 18
describes two methods for ac coupling the standard LVPECL driver. The Thevenin termination shown in Figure 18a
is a convenient and common approach when a VBB (VDD – 1.3 V) supply is not available; however, it does
consume additional power. The termination method shown in Figure 18b consumes less power. A VBB supply can
be generated from a simple voltage divider circuit as shown in Figure 18b.

VDDO VDDO Keep termination close to

3.3 V, 2.5 V the receiver
VDDOx R1 R1
Si5335 0.1 µF 3.3 V LVPECL
2.5 V LVPECL
CLKxA 50
LVPECL CLKxB
50

0.1 µF
R2 R2 VDDO – 1.3 V 3.3 V LVPECL
Rb Rb
R1 // R2 = 50  R1 = 82.5 
R2 = 127 

2.5 V LVPECL
Rb = 130  (2.5 V LVPECL)
R1 = 62.5 
Rb = 200 
(3.3 V LVPECL)
a. AC-Coupled with Thevenin Termination R2 = 250 

Keep termination close to

3.3 V, 2.5 V the receiver
0.1 µF
VDDOx
50
Si5335 3.3 V LVPECL
2.5 V LVPECL
50
CLKxA
LVPECL CLKxB VBB
50
0.1 µF

50

VDDO – 1.3 V VDDO

Rb Rb

R1
Rb = 130  (2.5 V LVPECL)
Rb = 200  (3.3 V LVPECL) VBB

0.1 µF R2

b. AC Coupled with 100  Termination

Figure 18. Interfacing to an LVPECL Receiver Using AC Coupling

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Si5335
3.10.4. LVDS Outputs
The LVDS output option provides a very simple and power-efficient interface that requires no external biasing when
connected to an LVDS receiver. An ac-coupled LVDS driver is often useful as a CML driver. The LVDS driver may
be dc-coupled or ac-coupled to the receiver in 3.3 V or 2.5 V output mode.
3.10.4.1. AC-Coupled LVDS Outputs
The Si5335 LVDS output can drive an ac-coupled load. The ac coupling capacitors may be placed at either the
driver or receiver end, as long as they are placed prior to the 100  termination resistor. Keep the 100 
termination resistor as close to the receiver as possible, as shown in Figure 19. When a 1.8 V output supply
voltage is used, the LVDS output of the Si5335 produces a common-mode voltage of ~0.875 V, which does not
support the LVDS standard. In this case, it is best to ac-couple the output to the load.

Keep termination close to

3.3 V or 2.5 V the receiver
VDDOx

Si5335
50
CLKxA LVDS
LVDS CLKxB 100 

50

DC-Coupled LVDS Output

Keep termination close to

3.3 V, 2.5 V, or 1.8 V the receiver
VDDOx
0.1 µF
Si5335 50
CLKxA
LVDS CLKxB 100 

50
0.1 µF

AC-Coupled LVDS Output

Figure 19. Interfacing to an LVDS Receiver

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 Si5335
3.10.5. HCSL Outputs
Host clock signal level (HCSL) outputs are commonly used in PCI Express applications. A typical HCSL driver has
an open source output that requires an external series resistor and a resistor to ground. The Si5335 HCSL driver
has integrated these resistors to simplify the interface to an HCSL receiver. No external components are necessary
when connecting the Si5335 HCSL driver to an HCSL receiver.

3.3, 2.5, or 1.8 V

VDDOx

Rs 50
CLKxA HCSL
HCSL
Rs CLKxB

50

Rt Rt

Si5335
Figure 20. Interfacing the Si5335 to an HCSL Receiver
3.10.6. CML Outputs
Current mode logic (CML) is transmitted differentially and terminated to 50  to Vcc as shown in Figure 20. A CML
receiver can be driven with either an LVPECL, CML, or LVDS output. To drive a CML receiver, an Si5335 output
configured in LVPECL or CML mode generates a single-ended output swing of 550 mV to 960 mV. However, to
reduce power consumption by approximately 15 mA per output driver pair (compared to an LVPECL-configured
output), the Si5335's CML output mode can be selected without affecting the output voltage swing. For even lower
power consumption, depending on the input signal swing required, CML receivers can be driven with an Si5335
output configured in LVDS mode. CML output format is not available when the Si5335 is in PLL bypass (clock
buffer) mode.

Driving a CML Receiver Using the LVPECL Output

Si5335 550 mV to 960 mVp-p CML

0.1 µF
Receiver
50
50
Vcc
0.1 µF
LVPECL 50
50

Rb Rb

Rb = 130 
(2.5 V LVPECL)

Rb = 200 
(3.3 V LVPECL)

Driving a CML Receiver Using the CML or LVDS Output

CML
670 mV to 1070 mVp-p (CML) Receiver
Si5335 250 mV to 450 mVp-p (LVDS)
0.1 µF

50
50
Vcc
0.1 µF
CML or 50
LVDS 50

Figure 21. Terminating an LVPECL or an LVDS Output to a CML Receiver

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Si5335
4. Power Consumption
In clock generator mode, the Si5335 Power consumption is a function of the following:
 Supply voltage
 Frequency of output Clocks
 Number of output Clocks
 Format of output Clocks
Because of internal voltage regulation, the current from the core VDD is independent of the VDD voltage and hence
the plot shown in Figure 5 can be used to estimate the VDD core (pins 7 and 24) current.
The current from the output supply voltages can be estimated from the values provided in Table 2, “DC
Characteristics,” on page 4. To get the most accurate value for VDD currents, the Si5338-EVB with ClockBuilder
Desktop software should be used.
To do this, go to the “Power” tab of ClockBuilder Desktop and press “Measure”. In this manner, a specific
configuration can be implemented on the EVB and the actual current for each supply voltage measured. When
doing this it is critical that the output drivers have the proper load impedance for the selected format.
When testing for output driver current with HSTL and SSTL, it is required to have load circuitry as shown in "3.10.2.
SSTL and HSTL Outputs" on page 27. The Si5338 EVB has layout pads that can be used for this purpose. When
testing for output driver current with LVPECL the same layout pads can be used to implement the LVPECL bias
resistor of 130  (2.5 V VDDx) or 200  (3.3 V VDDx). See the schematic in the Si5338-EVB data sheet and
AN408 for additional information.

80

75 4 Active Outputs, Fractional Output MS

4 Active Outputs, Integer Output MS
3 Active Outputs, Fractional Output MS
70
3 Active Outputs, Integer Output MS
2 Active Outputs, Fractional Output MS
65
2 Active Outputs, Integer Output MS
Typical VDD Core Current (ma)

1 Active Output, Fractional Output MS

60 1 Active Output, Integer Output MS

55

50

45

40

35

30
0 50 100 150 200 250 300 350 400

Output Frequency (MHz)

Figure 22. Core VDD Supply Average Current vs Output Frequency

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 Si5335
5. Spread Spectrum
To help reduce electromagnetic interference (EMI), the Si5335 supports spread spectrum modulation in clock
generator mode only. The output clock frequencies can be modulated to spread energy across a broader range of
frequencies, lowering system EMI. Spread spectrum modulation is generated digitally in the output MultiSynth
dividers, which means that the spread spectrum parameters are virtually independent of process, voltage, and
temperature variations.
If the SSENB function is assigned to a pin in ClockBuilder and asserted (driven low), PCIe-compliant spread
spectrum is applied to all 100 MHz output clocks with a default spreading rate of 31.5 kHz and 0.5% down spread.
If no 100 MHz output clocks are defined but the SSENB is assigned and asserted, none of the output clocks will
have spread spectrum clocking applied. Some custom spread-spectrum clocking profiles are available. If the
Si5335's default PCIe spread spectrum profile is not suitable for your application, submit your custom spread
spectrum requirements for review by visiting the Skyworks Solutions Technical Support web page at at
https://www.skyworksinc.com/support-ia, or contact your local Skyworks Solutions sales representative for more
information.

Clock with
Reduced SSC Off
Amplitude and
EMI

Clock with
SSC On
(downspread)

Carrier Frequency f

Figure 23. Spread Spectrum Clocking Impact on Output Power Spectrum

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Si5335
6. Jitter Performance
The Si5335 provides consistently low jitter for any combination of output frequencies. The device leverages a low
phase noise single PLL architecture and Skyworks Solutions’ patented MultiSynth fractional output divider
technology to deliver period jitter of 10 ps pk-pk (typ). The Si5335 provides superior performance to conventional
multi-PLL solutions which may suffer from degraded jitter performance depending on frequency plan and the
number of active PLLs.
7. Power Supply Considerations
The Si5335 has 2 core supply voltage pins (VDD) and 4 clock output bank supply voltage pins (VDDO0–VDDO3),
enabling the device to be used in mixed supply applications. The Si5335 does not typically require ferrite beads for
power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power
supply noise on output jitter. Figure 24 shows that the additive jitter created when a significant amount of noise is
applied to the device power supply is very low.

10
9 VDDO
Additive Jitter (ps pk-pk)

8 VDD
7
6
5
4
3
2
1
0
0.0001 0.001 0.01 0.1 1
Modulation Frequency (MHz)
Figure 24. Peak-to-Peak Additive Jitter from 100 mV Sine Wave on Supply

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 Si5335
8. Loop Bandwidth Considerations
For synchronous reference clock applications, two user-selectable loop bandwidth settings (1.6 MHz and 475 kHz)
are available to allow designers to optimize their timing system to support jitter attenuation of the reference clock.
In general, the 1.6 MHz setting provides the lowest output jitter and should be selected for most applications. The
1.6 MHz option provides faster PLL tracking of the input clock but less jitter attenuation of the input clock than the
475 kHz loop bandwidth option. The 1.6 MHz loop bandwidth option must be selected for all applications which use
a crystal reference input on the XA/XB pins (pins 1 and 2) and for all applications which provide a low jitter input
clock reference to the Si5335.
The 475 kHz setting reduces the clock generator's loop bandwidth, which has the benefit of attenuating some of
jitter that would normally pass through the 1.6 MHz setting. As the PLL loop bandwidth decreases, the intrinsic jitter
of the device increases and is reflected in higher jitter generation specifications, but total output jitter is the best
measure of system performance. Total output jitter includes both the generated jitter as well as the transferred jitter.
This lower loop bandwidth option can be useful in some applications, such as PCIe, DSL or other systems which
may utilize backplane distributed reference clocks. In these systems, the input clock may have appreciable low
frequency jitter (e.g., < 1.6 MHz). The source of the reference clock jitter can arise from suboptimal PCB trace
layouts, impedance mismatches and connectors. Input clock jitter may also be generated from an IC which has
poor power supply rejection performance, resulting in switching power supply noise and jitter coupling onto the
clock input of the Si5335. In these applications, designers may opt to use the 475 kHz loop bandwidth to help
attenuate the input clock jitter. Proper selection of PLL loop bandwidth involves a number of application-specific
considerations. Refer to “AN513: Jitter Attenuation—Choosing the Right Phase-Locked Loop Bandwidth” for more
information.
Please also refer to “AN624: Si5335 Solves Timing Challenges in PCI Express, Computing, Communications and
FPGA-Based Systems”.

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Si5335
9. Applications of the Si5335
Because of its flexible architecture, the Si5335 can be configured to serve several functions in the timing path. The
following sections describe some common applications.
9.1. Free-Running Clock Generator
Using the internal oscillator (Osc) and an inexpensive external crystal (XTAL), the Si5335 can be configured as a
free-running clock generator for replacing high-end and long-lead-time crystal oscillators found on many printed
circuit boards (PCBs). Replacing several crystal oscillators with a single IC solution helps consolidate the bill of
materials (BOM), reduces the number of suppliers, and reduces the number of long-lead-time components on the
PCB. In addition, since crystal oscillators tend to be the least reliable aspect of many systems, the overall failure-in-
time (FIT) rate improves with the elimination of each oscillator.
Up to four independent clock frequencies can be generated at any rate within its supported frequency range and
with any of supported output types. Figure 25 shows the Si5335 configured as a free-running clock generator.

ref
XTAL Osc PLL MS0 F0

MS1 F1

MS2 F2

MS3 F3
Si5335

Figure 25. Si5335 as a Free-Running Clock Generator

9.2. Synchronous Frequency Translation
In other cases, it is useful to generate an output frequency that is synchronous (or phase-locked) to another clock
frequency. The Si5335 is the ideal choice for generating up to four clocks with different frequencies with a fixed
phase relationship to an input reference. Because of its highly precise frequency synthesis, the Si5335 can
generate all four output frequencies with 0 ppm error to the input reference. The Si5335 is an ideal choice for
applications that have traditionally required multiple stages of frequency synthesis to achieve complex frequency
translations. Examples are in broadcast video (e.g., 148.5 MHz to 148.3516483 MHz), WAN/LAN applications (e.g.
155.52 MHz to 156.25 MHz), and Forward Error Correction (FEC) applications (e.g., 156.25 MHz to
161.1328125 MHz). Figure 26 shows the Si5335 configured as a synchronous clock generator. Frequencies may
be entered into the ClockBuilder Web utility with up to seven decimal points to ensure that the exact frequencies
can be achieved.

Si5335
MS0 F0

CLKIN MS1 F1
PLL
MS2 F2

MS3 F3

Figure 26. Si5335 as a Synchronous Clock Generator or Frequency Translator

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 Si5335
9.3. Configurable Universal Buffer and Level Translator
Using the ClockBuilder web utility, the synthesis stage can be entirely bypassed allowing the Si5335 to act as a
configurable clock buffer with level translation. Because of its highly selectable configuration, virtually any output
format and I/O voltage combination is possible. The configurable output drivers allow four differential outputs, eight
single-ended outputs, or a combination of both. Figure 27 shows the Si5335 configured as a flexible clock buffer
supporting mixed I/O supplies.

Si5335
3.3 V LVDS

2.5 V CMOS
CLKIN
1.8 V LVPECL

3.3 V HCSL

Figure 27. Si5335 as a Configurable Clock Buffer with Level Translation

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Si5335
10. Pin Descriptions

Top View

RSVD_GND

VDDO0
CLK0B
CLK0A
VDD

P2
24 23 22 21 20 19

XA/CLKIN 1 18 CLK1A

XB/CLKINB 2 17 CLK1B

P3 3 16 VDDO1
GND
GND
GND 4 Pad
15 VDDO2

P5 5 14 CLK2A

P6 6 13 CLK2B
7 8 9 10 11 12

P1
VDDO3
CLK3B

CLK3A
VDD

LOS

Note: Center pad must be tied to GND for normal operation.

Table 15. Si5335 Pin Descriptions

Pin # Pin Name I/O Signal Type Description
XA/CLKIN, XB/CLKINB.
These pins are used as the main differential or single-ended clock
input or as the XTAL input. See "3.4. Input Configuration" on page
XA/CLKIN, 19 and Figures 10, 11, and 12 for connection details. Clock inputs
1,2 I Multi
XB/CLKINB to these pins must be ac-coupled. Keep the traces from pins 1,2 to
the crystal as short as possible and keep other signals and radiat-
ing sources away from the crystal. The single-ended input voltage
swing must be limited to 1.2 Vpp.
Multi-Function Input. 3.3 V tolerant.
This pin functions as a multi-function input pin. The pin function
3 P3 I Multi (OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, or RESET) is
user-selectable at time of configuration using the ClockBuilder web
configuration utility.
Ground.
4 GND GND GND
Must be connected to system ground for proper device operation.
Multi-Function Input.
These pins function as multi-function input pins. The pin functions
(OEB_all, OEB0, OEB1, OEB2, OEB3, or SSENB) are user-
5,6 P5, P6 I Multi selectable at time of configuration using the ClockBuilder configu-
ration utility. A resistor voltage divider is required when driven by a
signal greater than 1.2 V. See "3.6.1. P5 and P6 Input Control" on
page 24 for details.
Core Supply Voltage.
This is the core supply voltage, which can operate from a 1.8, 2.5,
7 VDD VDD Supply
or 3.3 V supply. A 0.1 µF bypass capacitor should be located very
close to this pin.

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 Si5335
Table 15. Si5335 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description
Loss of Signal.
A typical pullup resistor of 1–4 k is used on this pin. This pin can
be pulled up to a supply voltage as high as 3.6 V regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, and 24. The LOS
condition allows the pull up resistor to pull the output up to the
supply voltage. See "3.9. Loss-of-Signal Alarm" on page 25.
8 LOS O Open Drain
This pin functions as an input clock loss-of-signal and PLL lock
status pin in clock generator mode:
0 = Input clock present and PLL locked.
1 = Input clock not present or PLL not locked.
In clock buffer mode, LOS is asserted when the input clock is not
present.
Output Clock B for Channel 3.
May be a single-ended output or half of a differential output with
9 CLK3B O Multi
CLK3A being the other differential half. If unused, leave this pin
floating.
Output Clock A for Channel 3.
May be a single-ended output or half of a differential output with
10 CLK3A O Multi
CLK3B being the other differential half. If unused, leave this pin
floating.
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A 0.1 µF
11 VDDO3 VDD Supply
capacitor must be located very close to this pin. If CLK3 is not
used, this pin must be tied to VDD (pin 7, 24).
Multi-Function Input. 3.3 V tolerant.
This pin functions as a multi-function input pin. The pin function
12 P1 I Multi (OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, FS0, FS1, or
RESET) is user-selectable at time of configuration using the Clock-
Builder web configuration utility
Output Clock B for Channel 2.
May be a single-ended output or half of a differential output with
13 CLK2B O Multi
CLK2A being the other differential half. If unused, leave this pin
floating.
Output Clock A for Channel 2.
May be a single-ended output or half of a differential output with
14 CLK2A O Multi
CLK2B being the other differential half. If unused, leave this pin
floating.
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B.
15 VDDO2 VDD Supply
A 0.1 µF capacitor must be located very close to this pin. If CLK2 is
not used, this pin must be tied to VDD (pin 7, 24).
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK1A,B.
16 VDDO1 VDD Supply
A 0.1 µF capacitor must be located very close to this pin. If CLK1 is
not used, this pin must be tied to VDD (pin 7, 24).

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Si5335
Table 15. Si5335 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description
Output Clock B for Channel 1.
May be a single-ended output or half of a differential output with
17 CLK1B O Multi
CLK1A being the other differential half. If unused, leave this pin
floating.
Output Clock A for Channel 1.
May be a single-ended output or half of a differential output with
18 CLK1A O Multi
CLK1B being the other differential half. If unused, leave this pin
floating.
Multi-Function Input. 3.3 V tolerant.
This pin functions as a multi-function input pin. The pin function
19 P2 I Multi (OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, FS1, or RESET)
is user-selectable at time of configuration using the ClockBuilder
web configuration utility.
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK0A,B.
20 VDDO0 VDD Supply
A 0.1 µF capacitor must be located very close to this pin. If CLK0 is
not used, this pin must be tied to VDD (pin 7, 24).
21 CLK0B O Multi Output Clock B for Channel 0.
May be a single-ended output or half of a differential output with
CLK0A being the other differential half. If unused, leave this pin
floating.
22 CLK0A O Multi Output Clock A for Channel 0.
May be a single-ended output or half of a differential output with
CLK0B being the other differential half. If unused, leave this pin
floating.
23 RSVD_GND GND GND Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
24 VDD VDD Supply Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 µF
bypass capacitor should be located very close to this pin.
GND GND GND GND Ground Pad.
PAD This is the large pad in the center of the package. The device will
not function unless the ground pad is properly connected to a
ground plane on the PCB. See Table 17, “PCB Land Pattern,” on
page 43 for ground via requirements.

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 Si5335
11. Ordering Information

Si5335X BXXXXX GMR

Operating Temp Range: -40 to +85 °C

Package: 4 x 4 mm QFN, RoHS6, Pb-free
R = Tape & Reel (ordering option)
Non Tape & Reel shipment media is trays

B = Product Revision B
XXXXX = NVM code.
Custom NVM configuration code. A unique 5-digit ordering code
will be assigned by the ClockBuilder web utility .

Frequency/Configuration:
Si5335A - 1 MHz to 350 MHz output with XTAL input
Si5335B - 1 MHz to 200 MHz output with XTAL input
Si5335C - 1 MHz to 350 MHz output with Differential/Single-ended input clock
Si5335D - 1 MHz to 200 MHz output with Differential/Single-ended input clock

Evaluation Boards

Si5338 EVB Si5335 Evaluation Board

The Si5338-EVB with ClockBuilder Desktop software includes the ability to evaluate Si 5335 output
frequency and format configurations. The EVB does not currently include the ability to control the
programmable function pins (P1, P2, P3, P5, and P6).

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Si5335
12. Package Outline: 24-Lead QFN

Figure 28. 24-Lead Quad Flat No-lead (QFN)

Table 16. Package Dimensions

Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 4.00 BSC.
D2 2.35 2.50 2.65
e 0.50 BSC.
E 4.00 BSC.
E2 2.35 2.50 2.65
L 0.30 0.40 0.50
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
5. Terminal base alloy: Cu
6. Terminal plating/grid array material: Au/NiPd.
7. Visit https://www.skyworksinc.com/support-ia for more information.

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 Si5335
13. Recommended PCB Land Pattern

Table 17. PCB Land Pattern

Dimension Min Nom Max
P1 2.50 2.55 2.60
P2 2.50 2.55 2.60
X1 0.20 0.25 0.30
Y1 0.75 0.80 0.85
C1 3.90
C2 3.90
E 0.50
Notes
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no
more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground
plane is allowed if more vias are used to keep the inductance from increasing.
Solder Mask Design:
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to
be 60 µm minimum, all the way around the pad.
Stencil Design:
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly:
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Si5335
14. Top Marking
14.1. Si5335 Top Marking

Si5335
Xxxxxx
RTTTTT
YYWW
14.2. Top Marking Explanation

Line Characters Description

Line 1 Si5335 Base part number.

X = Frequency and configuration code. See "11. Ordering Information"

on page 41 for more information.
Line 2 Xxxxxx
xxxxx = NVM code assigned by ClockBuilder web utility.
See "11. Ordering Information" on page 41.

R = Product revision.
Line 3 RTTTTT
TTTTT = Manufacturing trace code.

Circle with 0.5 mm diameter;

Pin 1 indicator.
left-justified

Line 4 YY = Year.
WW = Work week.
YYWW
Characters correspond to the year and work week of package assem-
bly.

44 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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 Si5335
15. Device Errata
Please visit www.skyworksinc.com to access the device errata document.

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Si5335
DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1
 Updated Table 8 on page 10 and Table 9 on
Revision 0.4 to Revision 0.9 page 12.
 Updated Table 2, “DC Characteristics,” on page 4. Updated typical specifications for total jitter for PCI
Added core power supply specification in buffer mode. Express 1.1 Common clocked topology.
 Updated Table 3, “Performance Characteristics,” on Updated typical specifications for RMS jitter for PCI

page 5. Express 2.1 Common clocked topology.

Added TRESET specification.  Updated Table 10 on page 14.
Updated typical additive jitter (12 kHz–20MHz) from
 Updated Table 4, “Input and Output Clock
0.150 to 0.165 ps RMS.
Characteristics,” on page 6.
 Added " Document Change List" on page 46.
Corrected VI on pin 1 to 1.3 V (max).
Updated CML output voltage specification to 0.86 Vpp. Revision 1.1 to Revision 1.2
 Updated Table 6, “Crystal Specifications for  Removed down spread spectrum errata that has
25 MHz,” on page 9. been corrected in revision B.
Corrected CL to 18 pF (typical).  Updated ordering information to refer to revision B
 Updated Table 7, “Crystal Specifications for silicon.
27 MHz,” on page 9.  Updated top marking explanation in Section 14.2.
Corrected CL to 18 pF (typical).
 Updated "3.4. Input Configuration" on page 19. Revision 1.2 to Revision 1.3
Revised text in Section 3.4.2.  Added link to errata document.
 Updated "3.6.1. P5 and P6 Input Control" on page
24. Revision 1.3 to Revision 1.4
Added Figure 13 to replace Table 15.  Updated Features on page 1.
 Updated Figure 21 on page 31.  Updated Description on page 1.
 Updated Table 14 on page 23.  Updated specs in Table 8.
Corrected Assignable Pin Name column entries.  Updated specs in Table 9.
 Updated "3.10. Output Stage" on page 26.
Revised throughout and included termination circuit
diagrams and text.
 Removed references to P4 as a programmable pin
option throughout document. Pin 4 is now a ground
pin.
Revision 0.9 to Revision 1.0
 Updated Table 9 on page 12.
DSL random jitter from 2.1 ps RMS (typ) to 1.95 ps RMS
(typ) and from "—" (max) to 2.2 ps RMS (max).
 Corrected text in “9.2. Synchronous Frequency
Translation” to match the capabilities of the
ClockBuilder web utility.

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jitter attenuators and network
synchronizers with a single tool. With
CBPro you can control evaluation
boards, access documentation, request
a custom part number, export for
in-system programming and more!

www.skyworksinc.com/CBPro

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