DD

Unit 3 : Design of Combinational logic

circuits

Electronics and Communication Engineering

Geethanjali College of Engineering and Technology
Cheeryal (V), Keesara (M), Medchal Dt. – 501301

Email: [email protected]

Prepared by : Prof. K S Rao, E C E Dept

 Topics:
■ Introduction to Combinational Logic Circuits
■ Adders
■ Subtractors
■ Multiplexers
■ Realization of Switching Functions using Multiplexers
■ De-Multiplexers
■ Decoders
■ Encoders
■ Priority encoders
■ Comparators
■ Parity generators
■ Code converters
■ Static Hazards and Hazard Free Realizations
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 Reference Book:

Text Books:
Chapter 5 - Switching and Finite Automata
Theory by ZVI Kohavi, Second Edition

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 Combinational Logic
■ Logic circuits for digital systems may be combinational or
sequential.
■ A combinational circuit consists of input variables, logic
gates, and output variables. The output is based on the
present inputs only. The output is defined by a Truth table
or a Boolean equation.

In Sequential logic, the output is based on the Present inputs and the
previous state also. These are defined by state diagrams / state tables. 4
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Combinational Logic

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 Analysis procedure
To obtain the output Boolean functions from a logic
diagram, proceed as follows:
1. Label all gate outputs that are a function of input variables
with arbitrary symbols. Determine the Boolean functions
for each gate output.
2. Label the gates that are a function of input variables and
previously labeled gates with other arbitrary symbols. Find
the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of
the circuit are obtained.
4. By repeated substitution of previously defined functions,
obtain the output Boolean functions in terms of input
variables. 6
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 Example
F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1;
F1 = T 3 + T 2
F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

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 Design procedure
1. Define the problem
2. Determine the number of available input
variables and required output variables.
3. Assign symbols for the inputs and the outputs
4. Write the Truth table giving the relation
between the Inputs and the Outputs.
5. Obtain the simplified Boolean expression for
each output.
6. Draw the logic diagram ( as AOI / NAND / NOR
/ other Universal functions)
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 Half Adder
■ A combinational circuit that performs the addition of two bits
is called a Half Adder.
■ The truth table for the half adder is listed below:
x y Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
A Half S
1 1 1 0
Truth table B
Adder
C
S = x’y + xy’
C = xy Block Diagram

Boolean Expressions
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Implementation of Half-Adder (using
basic gates – AOI gates)

Logic Diagrams

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 Full-Adder
One that performs the addition of three bits (Augend
bit, addend bit and a previous carry) and generates
and Sum and Carry out, is a Full Adder.
x y C in (z) C out Sum
0 0 0 0 0
0 0 1 0 1 A Full Sum
0 1 0 0 1 B
Cin Adder
0 1 1 1 0 C out
1 0 0 0 1
Block Diagram
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Truth
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Simplified Expressions

S = x’y’z + x’yz’ + xy’z’ + xyz

C = xy + xz + yz
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Full adder implemented in SOP
(using basic gates – AOI gates)

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 Another implementation
Full-adder can also be implemented with two Half
Adders and one OR gate
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(xy’ + x’y) + xy = xy’z + x’yz + xy

Half adder -1 OR Gate

Half Adder -2

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 Adder circuits using NAND gates

Half adder using NAND gates

Full adder using NAND

gates

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 4 Bit Binary adder
Example:
This is also called
Ripple Carry Adder/
Parallel adder
because of the
construction.
Four Full adders are
connected in
cascade to get a
Four bit adder.

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 Half subtractor
A combinational circuit that performs the subtraction of two bits is
called a Half Subtractor.
The truth table for the half Sub tractor is listed below:
D = x’y + xy’ = x XOR y
B = x’y
Minuend

Subtrahend

Difference

Borrow out

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Full subtractor

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 Full subtractor circuit using two
Half Subtractors

Bin

Half Subtractor 2
Bout
Half Subtractor 1
Two half subtractors with an OR gate gives Full
subtractor.
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Full subtractor circuit using NAND
gates

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Full subtractor circuit using one NOT
gate and unlimited AND, OR gates.

Borrow

Difference

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 Carry Propagation

■ Ripple adder causes an unstable factor on carry bit, and

produces a longest propagation delay.
■ The signal from Ci to the output carry Ci+1, propagates
through an AND and OR gates, so, for an n-bit RCA, there
are 2n gate levels for the carry to propagate from input to
output.

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 Look ahead Carry Adder

■ Because the propagation delay will affect the output signals,

the signals are to be given enough time to get the precise
and stable outputs.
■ The principle of carry look-ahead is used in Adders to
improve the speed of the algorithm.

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 Boolean functions
Pi = Ai ⊕ Bi steady state value
G i = A iB i steady state value
Output sum and carry
Si = P i ⊕ Ci
Ci+1 = Gi + PiCi
Gi : carry generate Pi : carry propagate
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

■ C3 does not have to wait for C2 and C1 to

propagate.
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 Logic diagram of
carry look-ahead generator
■ C3 is propagated at the same time as C2 and C1.

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 4-bit adder with carry
lookahead
■ Delay time of n-bit CLAA = XOR + (AND + OR) + XOR

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 Binary Adder / subtractor
M (Mode) = 1🡪subtractor ; M (Mode) = 0🡪adder

Mode
bit

Carry out

Overflow

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 Binary subtractor
Subtraction is done in computers by adding 2’s complement
of the Subtrahend to the Minuend.
2’s complement is obtained by adding 1 to 1’s complement.
1’s complement is obtained by taking complement of the
given number.
In addition, if carry comes, it indicates that the sum is more than
15 i.e. unable to accommodate in 4 bits.
In subtraction using 2’s complement method, if carry comes, the
result is a positive number and carry is to be ignored. If carry does
not come, the result is a –ve number. To get the value, do the 2’s
complement of the number again and add –ve sign.
XOR gates are used to give B value to the Full Adders as Diret B for
addition and Complement of B for subtraction, depending on the MODE
Bit.
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Binary subtractor

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 Decimal adder (BCD Adder)
BCD adder can’t exceed 9 on each input digit. K is the carry.

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 Rules of BCD adder
■ Case 1: If the sum is 9 or less, the Binary code and the BCD
code are same. No additional is to be done.
■ Case 2 : Is the sum is 10 to 15, carry K will not come. Based
on the sum value, 6 is to be added to convert Binary code to
BCD code. This is achieved as Z8 AND (Z4 or Z2 ).
■ Case 3 : If the sum is 16 to 19, Carry K will come. In this
case also, 6 is to be added to convert Binary to BCD.
C = K + Z 8Z 4 + Z 8Z 2

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 Implementation of BCD adder
■ A decimal parallel
adder that adds n
decimal digits needs
n BCD adder
stages.

If 011
=1 0

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BCD Adder

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 Multiplexers (Data Selectors)
A Multiplexer selects one of the many inputs (selects one
from many) based on the Select signals.
Typical multiplexers are 2 to 1, 4 to 1, 8 to 1, 16 to 1 etc.
The number of data inputs for a Multiplexer are 2 n where n
is number of the select inputs.
Another input, called as Enable input is available for the
Multiplexer, which makes it enables or disabled, based on
this input. This enable input is used for expansion of the
multiplexers.

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 2 to 1 Multiplexer
S = 0, Y = I0 Truth Table🡪 S Y Y = S’I0 + SI1
S = 1, Y = I1 0 I0
1 I1

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4-to-1 Line and 8 to 1 Line Multiplexers

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 Expansion of Multiplexers

Implementation of 4 X 1
Multiplexer using two 2X1
Multiplexers and basic gates.
Implementation of 8 X 1 Multiplexer
using two 4X1 Multiplexers and one
2X1 multiplexer.
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Expansion of Multiplexers
Implementation of 8 X
1 multiplexer using
seven 2 X 1
Multiplexers.

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 Multiplexers for implementing
Boolean functions
Multiplexers can be used to implement Boolean functions.
Two methods are available for this requirement.
1.Using a multiplexer of 2n to 1 where n is the number of
variables of the function. Each data input of the Mux is a
term of the Boolean function. Give 1s to Minterm inputs
and 0s to Maxterm inputs. Give the variables of the
function as select lines.
2.Using a multiplexer of 2n-1 where n is the number of
variables of the function. Give n-1 variables as select lines.
Based on the nth variable, give data inputs as either 0 or 1
or nth variable itself or complement of the nth variable as
inputs.

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Implementation of a 3 variable
function with a 8X1 Mux

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 Implementation of a 3 variable
function with a 4X1 Mux
■ A more efficient method for implementing a Boolean function
of n variables with a multiplexer that has n-1 selection
inputs.
F(x, y, z) = Σ(1,2,6,7)

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 4-input function with a 8 to 1
multiplexer
F(A, B, C, D) = Σ(1, 3, 4, 11, 12, 13, 14, 15)

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 Decoders

■ The decoder is called n-to-m-line decoder, where

m≤2n .
■ 3-to-8 line decoder: For each possible input
combination, there are seven outputs that are
equal to 0 and only one output that is equal to 1.

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 Decoders

Enable

3 to 8 Decoder Block Diagram

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Implementation and truth table
of 3 to 8 Decoder

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 Decoder with enable input
■ Some decoders are constructed with NAND gates, it
becomes more economical to generate the decoder
minterms in their complemented form.
■ As indicated by the truth table , only one output can be equal
to 0 at any given time, all other outputs are equal to 1.

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Expansion of decoders

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 Expansion of decoders

3 to 8 Decoder using two 2 to 4 decoders

5 to 32 Decoder using four 3 to 8 and one 2

to 4 Decoders.
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 Implementation of a
Full Adder with a Decoder
■ From table 4-4, we obtain the functions for the combinational circuit in
sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)

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 Demultiplexer
■ A Demultipexer is opposite to Multiplexer. It selects the input
to one of the many outputs, based on the selection bits.
■ A Demultiplexer is same as a Decoder with an enable input.
The truth table of a Demultiplexer and a Decoder are similar.
A B

D0
Demultiplexer D1
E
D2
D3
Block Diagram
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De-multiplexer

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Expanding De-multiplexers

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Expanding De-multiplexer

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 Implementing a Boolean function
using a De-multiplexer

Implementation of
the the function
D(A,B,C)=Σ(1, 2,
4, 7) and
B(A,B,C)=Σ(1, 2,3,
7) using a
demultiplexer and
OR gates.

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 Encoders
■ An encoder is the inverse operation of a Decoder.
■ n bit Code is generated based on one of 2n inputs activated.
■ The different types of Encoders are 4 to 2, 8 to 3, 16 to 4,
etc.
■ We can derive the Boolean functions as below for a 8 to 3
Encoder. I0
I1 Y0
I2
Y2 = I 4 + I5 + I6 + I7 I3 Y1
I4
Y1 = I 2 + I3 + I6 + I7 I5 Y2
Y0 = I 1 + I3 + I5 + I7 I6
I7
8 to 3 Encoder Logic Equations
8 to 3 Encoder Block Diagram
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 8 to 3 Encoder

At any point of time, only one

input line has a value of 1.
8 to 3 Encoder
Truth Table

8 to 3 Encoder
Logic Diagram

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 Priority encoder

■ If two or more inputs are active simultaneously, the

output produces an undefined combination. We can
establish an input priority to ensure that only one input is
encoded.
■ Another ambiguity in the octal-to-binary encoder is that
an output with all 0’s is generated when all the inputs are
0; the output is the same as when D0 is equal to 1.
■ The discrepancy can be resolved for the aforesaid
condition by providing one more output to indicate that at
least one input is equal to 1 which is known as Validity
bit.
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 Priority encoder
V=0🡪 no valid inputs
V=1🡪 valid inputs

X’s in output columns represent

don’t-care conditions
X’s in the input columns are
useful for representing a truth
table in condensed form,
instead of listing all 16
minterms of four variables.

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4-input priority encoder

V = Validity, X, Y : Code bits generated based on Inputs

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 8 to 3 Priority encoder (IC 74148)

Truth Table
Pin Diagram
It is a negative logic IC i.e. 0 is active. EI is enable input , EO is Enable
output indicating all inputs are HIGH and GS is Group Signal Output
indicating some inputs are low. Prepared by : Prof. K S Rao
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 Magnitude comparator
A Magnitude comparator compares two data (A & B)and generates
output as A=B, A>B and A<B. Due to the requirements of expansion
(cascading), the inputs are to be A data, B data, previous comparison
outputs A=B, A>B and A<B.

Cascading
Outputs inputs

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 Magnitude comparator - Expansion

Final
outputs
Cascading of Comparators.

8 bit comparators is designed using two 4 bit comparators.

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Magnitude comparator - Expansion

Truth table for 7485 Magnitude comparator

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 4 Bit - Magnitude comparator
Logic Diagram
■ The equality relation of each
pair of bits can be expressed
logically with an
exclusive-NOR function as:

A = A3A2A1A0 ; B = B3B2B1B0

xi=AiBi+Ai’Bi’ for i = 0, 1, 2, 3

(A = B) = x3x2x1x0

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 Magnitude comparator
■ We inspect the relative
magnitudes of pairs of MSB. If
equal, we compare the next
lower significant pair of digits
until a pair of unequal digits is
reached.
■ If the corresponding digit of A is
1 and that of B is 0, we conclude
that A>B.
(A>B)=
A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’
0
(A<B)=
A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0 65
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 Code converter
The code converter converts one type of code to
other type of code. The different types of codes
are Binary, BCD, Excess-3, Gray, 7-segemnt
driver, etc.
Steps : 1.Write the truth table for the inputs &
outputs.
2. Simplify the Boolean equations for each output,
using K Map.
3. Draw the circuit diagram.

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 Example 1: BCD to Excess-3 Code
converter
Truth table

For input conditions 1010 to 1111, the outputs are don’t care, as
these inputs are not valid in BCD codes. 67
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 Formulation of BCD-to-Excess-3

■ Excess-3 code is formed by adding 3 to the

binary digit.
■ There are 16 possible inputs in Binary. Where
as for BCD, only code for 0 – 9 digits is valid.
■ So the six combinations 1010 to 1111 are not
used in BCD and to be treated as don’t cares.

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 Specification of BCD-to-Excess3

■ Inputs: a BCD input, A,B,C,D with A as the

most significant bit and D as the least
significant bit.
■ Outputs: an Excess-3 output W,X,Y,Z that
corresponds to the BCD input.
■ Internal operation – circuit to do the
conversion in combinational logic.

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 Expressions for W X Y Z

■ W(A,B,C,D) = Σm(5,6,7,8,9)
+d(10,11,12,13,14,15)
■ X(A,B,C,D) = Σm(1,2,3,4,9)
+d(10,11,12,13,14,15)
■ Y(A,B,C,D) = Σm(0,3,4,7,8)
+d(10,11,12,13,14,15)
■ Z(A,B,C,D) = Σm(0,2,4,6,8)
+d(10,11,12,13,14,15)

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 Karnaugh map
For each symbol of the Excess-3 code, we draw the map for simplifying
Boolean function.

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 Two level circuit implementation
■ Have equations
■ W = A + BC + BD = A + B(C+D)
■ X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
■ Y = CD + C’D’

9/15/09 - L12
Copyright 2009 - Combinational
72 Logic
Prepared
Joanne DeGroat, ECE, by : Prof. K S Rao Design
 Two level circuit implementation
■ Have equations
■ W = A + BC + BD = A + B(C+D)
■ X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
■ Y = CD + C’D’
■ Z = D’
■ Factoring out (C+D) and call it T
■ Then T’ = (C+D)’ = C’D’
■ W = A + BT
■ X = B’T + BT’
■ Y = CD + T’
■ Z = D’

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Copyright 2009 - Combinational
73 Logic
Prepared
Joanne DeGroat, ECE, by : Prof. K S Rao Design
 Create the digital circuit

■ Implementing
the second set of
equations where
T=C+D results in
a lower gate
count.
■ This gate has a
fanout of 3

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Example 2: Binary to Gray code
converter
Inputs Outputs
B3 B2 B1 B0 G3 G2 G1 G0 G3 = Σm(8,9,10,11,12,13,14,15)
G2 = Σm(4,5,6,7,8,9,10,11)
G1 = Σm(2,3,4,5,10,11,12,13)
G0 = Σm(1,2,5,6,9,10,13,14)

Simplify G3, G2, G1 and G0

individually using K-maps
and draw the logic diagram.

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Truth table Prepared by : Prof. K S Rao
 Example 3: Gray code to Binary code
converter

Truth table
In the sequence of Min-terms Truth table
for Gray code In the sequence of
Binary numbers
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 Example 4: BCD-to- Gray code
Converter
Term B3 B2 B1 B0 G3 G2 G1 G0
G3 = Σm(5,6,7,8,9) +
0 0 0 0 0 0 0 1 0
d(10,11,12,13,14,15)
1 0 0 0 1 0 1 1 0 G2 =
2 0 0 1 0 0 1 1 1 Σm(1,2,3,4,5,6,7,8) +
3 0 0 1 1 0 1 0 1 d(10,11,12,13,14,15)
4 0 1 0 0 0 1 0 0 G1 = Σm(0,1,2,7,8,9)
+
5 0 1 0 1 1 1 0 0
d(10,11,12,13,14,15)
6 0 1 1 0 1 1 0 1 G0 = Σm(2,3,6,7) +
7 0 1 1 1 1 1 1 1 d(10,11,12,13,14,15)
8 1 0 0 0 1 1 1 0
Simplify each of the
9 1 0 0 1 1 0 1 0
above outputs using
Truth Table, with Gray code adjusted to the centre K-Maps and draw the
logic diagram.

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 Example 5: BCD-to-Seven-Segment
Code Converter

■ Specification
■ Digital readouts on many digital products often
use LED seven-segment displays.
■ Each digit is created by lighting the
appropriate segments. The segments are
labeled a,b,c,d,e,f,g
■ The decoder takes a BCD input and outputs
the correct code for the seven-segment
display.

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 BCD to 7 Segment Code converter

■ Input: A 4-bit binary value that is a BCD

coded input.
■ Outputs: 7 bits, a through g for each of the
segments of the display.
■ Operation: Decode the input to activate the
correct segments.

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 BCD to 7 segment Code Converter

Truth table

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 BCD to 7 segment Code Converter

■ K-map for each output and get

■ A = A’C+A’BD+B’C’D’+AB’C’
■ B = A’B’+A’C’D’+A’CD+AB’C’
■ C = A’B+A’D+B’C’D’+AB’C’
■ D = A’CD’+A’B’C+B’C’D’+AB’C’+A’BC’D
■ E = A’CD’+B’C’D’
■ F = A’BC’+A’C’D’+A’BD’+AB’C’
■ G = A’CD’+A’B’C+A’BC’+AB’C’

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 Note on implementation

■ Direct implementation would require 27 AND

gates and 7 OR gates.
■ By sharing terms, the same logic can be
implemented with 14 less gates.
■ Normally a single decoder (Here 4 to 16) with
seven OR gates, can be used for this type of
multiple output logic generation.

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 Parity generator and checker
Parity is an additional bit added to the information so that the total number
of 1s in the information along with parity, is even for even parity and is
odd for the odd parity. For a 3 bit information, a parity is added at the
Transmitter side and the information is transmitted. At the receiver side,
the information and the parity are received and the same is checked for
the error. XOR gates are used for this purpose.

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 Parity generator and checker

Even parity bit generation and checking circuit. If the Error output is 0,
then there is no error. Otherwise, there is an error.
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 Static Hazards and Hazard free
Realization
A Hazard is a momentary unwanted switching transient at
a logic function’s output (i.e., a glitch).
Hazards/glitches occur due to unequal propagation delays
along different paths in a combinational circuit.
There are two types of hazards; Static and Dynamic.
Static‐0 Hazard: Occurs when output is 0 and should remain
at 0, but temporarily switches to a 1 due to a change in an
input.
Statuc-1 Hazard: Occurs when output is 1 and should
remain at 1, but temporarily switches to a 0 due to a change
in an input.

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 Static Hazards and Hazard free
Realization
Let each gate has a
delay of x nano
seconds. Let a=b=c=1.
Output is 1 because
AND1 output is 1. Now,
let b input changes
from 1 to 0.
Logically, AND1 output goes to 0 and
AND2 output goes to 1, giving final
output f =1. But, the input of AND2
gate from b does not change
immediately and takes a delay of x
nano seconds. During that time,
AND1 and AND2 outputs are 0 and
hene, the final output is 0 for the
duration of x. This is called static 1
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 Static Hazards and Hazard free
Realization

Static Hazard can be eliminated by

considering all Prime implicants (including
the redundant). The same is shown in the
K Maps here.

87
Prepared by : Prof. K S Rao
 Quiz 9 questions
DD Unit 3 Quiz 9 questions:
•The output of a combinational logic circuit depends on
•Present inputs only B. Present inputs and the previous state C. Previous state only D. All of these
Answer: Option A
•The inputs and outputs of a Full adder are
•2,2 B. 3,2 C. 2,3 D. 3,3
Answer: Option C
•The inputs and outputs of a Half subtractor are
•2,2 B. 3,2 C. 2,3 D. 3,3
Answer : Option A
•In Binary Adder cum subtractor, the gates externally used to select B or B’ depending on the mode bit, are
•AND B. OR C. XOR D. NOT
Answer : Option C
•Full adder can be implemented by using
•Two half adders B. Two half adders and an AND gate C. Two half adders and an OR gate D. Two Half adders and an XOR gate
Answer : Option C
•In BCD Adder, 6 is added to sum, when the binary sum is more than
•15 B. 10 C. 9 D. 19
Answer : Option C
•Carry look ahead adder has the characteristics of
•High speed B. Additional hardware C. No rippling of carry D. All of these
Answer : Option D
•The enable bit in multiplexer is used for
•Expansion B. Enabling the IC C. to make the IC selected D. All of these
Answer : Option D
•The parallel adder is also known as
•Binary adder B. Ripple adder C. Both A&B D. None of these
Answer : Option C
•The number of selection bits required for a 12 X 1 Multiplexer are
•12 B. 3 C. 4 D. 1 88
Answer : Option C Prepared by : Prof. K S Rao
 Quiz 10 questions
DD Unit 3 Quiz 10 questions:
•A Boolean function can be implemented using the combinational logic circuits
•Multiplexer B. Decoder + OR gates C. Demultiplexer + OR gates D. Any of these
Answer: Option D
•To design a 16 to 1 multiplexer using only 4 to 1 multiplexers, the number of 4 to 1 multiplexers required are
•4 B. 5 C. 3 D. 16
Answer: Option B
•While implementing a Boolean function using Multiplexers, the inputs to the Multiplexer, when one level less multiplexer is used, are
•1s and 0s B. 1s, 0s, 3rd variable and its complement C. variables given in the function D. None of these.
Answer : Option B
•To implement a BCD to 7 segment driver using a Decoder, the requirements are
•1 Decoder & 1 OR gate B. 1 Decoder and 7 OR gates C. 7 Decoders and 7 OR gates D. 7 Decoders and 1 OR gate
Answer : Option B
•To implement a Boolean function f (w,x,y,z) using a Multiplexer, the required multiplexer is
•16 to 1 B. 8 to 1 C. Either 16 to 1 or 8 to 1 D. 4 to 1
Answer : Option C
•To implement a Boolean function f(a,b,c) using a Decoder requires
•3 to 8 Decoder and an OR gate B. 3 to 8 Decoder C. 8 to 3 Encoder D. 4 to 16 Decoder
Answer : Option A
•The number of inputs and outputs for a BCD to 10 digit output Decoder are
•3 to 8 B. 4 to 10 C. 1 to 10 D. 10 to 4
Answer : Option B
•The normal Encoder has the deficiency of
•Ambiguity in the code generated when more than one input is given B. The code for the D0 input and no input is same C. Validity of the output code
generated is not known D. All of these.
Answer : Option D
•The gate that is better suited in the Magnitude comparators is
•NOR B. XOR C. XNOR D. NAND
Answer : Option C
•The gate used to generate Parity and to check parity is
•AND B. OR C. XOR D. XNOR 89
Answer : Option C Prepared by : Prof. K S Rao
 Exercise problems
5.1 Express T1 and T2 as functions of A,B,C and D.

5.2 a. Design a two level code converter from BCD to the 2-out-of-5 code shown below.
5.2b. Design a two-level code converter from the Ringtail code shown below to BCD.

Problem 5.2 a Problem 5.2 b

Prepared by : Prof. K S Rao
 Exercise problems
5.3 Design a circuit with four inputs x1, x2, x3, x4 and seven outputs p1, p2, m1, p3, m2, m3, m4
that receives a BCD code words and generates the corresponding Hamming code words
defined in Table 1-8.
5.4 You are supplied with just one NOT gate and an
unlimited amount of AND and OR gates and are
required to design a circuit that realizes the
expression
T (w, x, y, z) = w’x + x’y + xz’
Only unprimed variables are available as
inputs. Hint: You may find the map of T helpful.

5.6 A certain four-input gate, called a LEMON gate, realizes the switching Function
LEMON(A,B,C,D) = BC(A + D). Assume that the input variables are available in both
primed and unprimed form.
•Show a realization of the function f (w, x, y, z) = Ʃ(0, 1, 6, 9, 10, 11, 14, 15) with only three
LEMON gates and one OR gate.
•Can all switching functions be realized with LEMON and OR logic?
Hint: Draw the map for LEMON and utilize possible “patches” (coverings of the
minterms of f with the LEMON function) on the map of f.
Prepared by : Prof. K S Rao
 Exercise problems
P5.7
5.7 A three-input gate, BOMB, whose characteristics are
shown in Fig. P5.7, has been mass produced by an
unfortunate company. Experimental evidence shows that
input combinations 101 and 010 cause the gate to
physically explode. Your task is to determine whether the
gate is completely useless or can be externally modified
such that it may be efficiently used to implement any
switching function without causing explosions. P5.8
5.8 A logic module A, shown in Fig. P5.8, operates as follows: output yi = 1if i inputs out
of x0, x1, x2 are equal to 1. Design unit B in such a way that the overall logic function of
unit C will be to produce an output zi = 1 iff i inputs out of x0, x1, x2,x3 are equal to 1.
5.9 Given a logic module A that compares the magnitudes of two 3-bit numbers, X3 = x1x2x3
and Y3 = y1y2y3, where x3 and y3 are the least significant bits. Module A has two outputs G3
and S3, such that: G3 = 1 if X3 > Y3; S3 = 1 if X3 < Y3; and G3 = S3 = 0 if X3 = Y3.
(a) Design a logic unit B such that together with module A it will serve as a comparator for two
four-bit numbers, X4 = x1x2x3x4 and Y4 = y1y2y3y4, as shown in Fig. P5.9.
(a) Find expressions forG4 and S4 in terms of the inputs to unit B and show a realization
of these expressions using only NAND gates.
(b) Show a realization of module A by means of only units of type B. Assume that the
Prepared by : Prof. K S Rao
 Exercise problems
5.11 A half adder is a device capable of performing the
addition of two bits. It has two binary inputs, A and B, and
two outputs, S and C0. (Note that there is no carry into
the half adder.) P5.9
•Write truth tables that define the half adder and derive logic expressions for S and C0.
•Assuming that only uncomplemented inputs are available, show an implementation of the half
adder that requires only three two-input AND or OR gates and one NOT gate.
•Under the above assumption, design the half adder using no more than five NAND
gates or NOR gates, but not both together.
5.15 Analyze the two-output circuit
shown in Figure below. Indicate the logic
expression associated with every gate
output.

P5.15

Prepared by : Prof. K S Rao

 Exercise problems
5.19 A communication system is designed to transmit just two code words, A = 0010 and B =
1101. However, owing to noise in the system, the received word may have as many as two
errors. Design a combinational circuit that receives the words and that can correct one error
and detect the existence of two errors. Specifically, design the circuit in Fig. P5.19 in such a
way that output A will be equal to 1 if the received word is A, output B will be equal to 1 if
the received word is B, and output C will be equal to 1 if the word received has two errors
and thus cannot be corrected. P5.19
1. Design and implement a three bit parallel parity-bit generator and
checker.
2. Design a converter which sends a four bit input on line x which receives a sequence of
binary digits that must be distributed into four different output terminals with external
control.( serial-to-parallel converter )
3. Implement the following Boolean function using
1.AOI gates b. NAND gates c. NOR gates d. 8X1 Multiplexer e, 4X1 Multiplexer f.
Decoder and an OR gate g. Demultiplexer and an OR gate
5. Design a 16X 1 Mux using 4X1 Multiplexers in three different ways.
Using Multiplexers only, Using Multiplexers, a Decoder an OR gate (utilizing the Enable
Input).Using Multiplexers, AND and NOT gates.
6. Design a 4 to 16 decoder using 2 to 4 Decoders.
7. Design a 1 to 8 Demux using 1 to 2 Demux circuits.Prepared by : Prof. K S Rao