Surajit Das

Assistant Professor

DATA
REPRESENTATION
AND COMPUTER
ARITHMETIC
1 Data Representation and Computer Arithmetic

Course Content:
1. Number System.
2. Binary Data Representation- Fixed-point and Floating-point representation.
3. Floating point - IEEE 754 standard.
4. Sequential Multiplication Method for Unsigned Numbers.
5. Booth’s Multiplication Algorithm.
6. Fixed-point Division method- Restoring and Non-resorting division method.

References:
1. Mano, M.M., “Computer System Architecture”, PHI.
2. Hamacher, “Computer Organisation”, McGraw Hill.
3. William Stallings, “Computer Organization and Architecture”, Pearson Publication.
4. Chaudhuri P. Pal, “Computer Organisation & Design”, PHI.
5. T.K.Ghosh, “Computer Organization and Architecture”, McGraw Hill.

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2 Data Representation and Computer Arithmetic

Introduction
A computer uses two state electronic circuits to perform its tasks. The two states of a circuit
are represented as 0 and 1. Hence, it is said that computers work with two digits, 0 and 1. A
number system using two digits is called a binary number system. The computers store the
binary information needed to perform some operation in memory or processor registers. The
binary information can be instruction or data. Data can be numerical or alphabetical. Operands
for an arithmetic operation, address for a memory, characters, logical values etc. are considered
as data. Instructions consist of operation codes (opcode) for specific tasks and operand(s) on
which the action is executed. An operand could be a direct value (numerical or character or
logical) or an address for the same. As the computers work with binary numbers, it is obvious
that all kinds of data and instructions should be represented in the computer in a binary coded
format.

Number System
A number system defines a set of values used to represent quantity. In our daily life, we are
using decimal numbers, which are 0,1,2,3,4,5,6,7,8 and 9. In other words, humans are most
accustomed with decimal number system. But a computer can only understand the information
composed of 0s and 1s. That means the binary number system is followed by the computers in
most natural way.
A number in the number system of base or radix (r) is represented by a set of symbols from r
distinct symbols. The decimal number system uses 10 digits from 0 to 9, thus its base is 10.
The binary system uses two distinct digits 0 and 1, thus its base is 2. For octal system (base r
= 8), a number is represented by 8 distinct digits 0 to 7. The 16 symbols used in hexadecimal
number system (base r = 16) are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F. Here, symbols
A, B, C, D, E and F correspond to the numbers 10, 11, 12, 13, 14, 15 respectively.

Decimal Codes
As we know, humans understand decimal system easily and computers process everything in
binary, therefore, there must be a conversion system from decimal-to-binary representation in
computer’s input process. Similarly, binary-to-decimal conversion system must be a part of the
computer’s output process. These conversions should be performed very rapidly. To facilitate
rapid conversions, several number codes exist that encode each decimal separately by a group
of bits. These types of codes are called decimal codes. Two widely used decimal codes are:

BCD (Binary Coded Decimal):

The BCD is the simplest binary code to represent a decimal number. In BCD code, four bits
are used to represent a decimal number. For example, decimal 7 is represented by 0111. When
a decimal number consists of more than one decimal digit, each digit is independently
represented by its 4-bit binary equivalent. For example, 45 is represented by 0100 0101.
BCD code is weighted code and weights of four bits which represent an individual digit are 8,
4, 2, 1. For this reason, BCD code is sometimes called 8-4-2-1 code. In weighted codes, the
bits are multiplied by wights mentioned and addition of the weighted bits gives the decimal

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3 Data Representation and Computer Arithmetic

digit. For example, the number 0101 in BCD code (8-4-2-1 code) gives the decimal equivalent
8 * 0 + 4 * 1 + 2 * 0 + 1 * 1 = 5.

Excess-3 Code:
In this code, every BCD value is added with 3 (0011) and the sum represents the corresponding
BCD digit. The BCD and Excess-3 code for the number 935 will be as follows:

Decimal Number 9 3 5

BCD 1001 0011 0101

Excess-3 code 1100 0110 1000

The disadvantage of this code is that it is not a weighted code that means the sum of weights
of bits is not equal to the corresponding decimal digit.

Complements of Numbers
Complements are used in digital computers to simplify the subtraction and logical manipulation
and to represent the negative numbers. For any number system of base r, there can be two types
of complements: (r - 1)’s and r’s complement. For example, for decimal number system, the
two types of complements are 10’s and 9’s. Similarly, for binary system, two types of
complements are 2’s and 1’s. These complements are discussed as follows:

(r - 1)’s Complement:
The (r – 1)’s complement (also known as diminished complement) of a positive number N
having m digits in base r, is defined as (rm - 1) – N, where, m is the number of digits in the
integer part. In case of decimal numbers, the value of r = 10 and r – 1 = 9, so the 9’s
complement of N is (10m - 1) – N. Here, the number 10m represents a (n + 1) digit number
having a single 1 followed by m zeros. Thus, 10m – 1 will represent an m-digit number having
all 9’s. We can observe that, the 9’s complement of a decimal number can be obtained by
subtracting each digit of number individually from 9. For example, if we want to calculate the
9’s complement of 32, then it will be 99 – 32 = 67.
Similarly, 1’s complement of a binary number can be found by subtracting each bit
from 1. But, while performing subtraction operation from binary digit 1, the bits change from
either 0 to 1 or 1 to 0. The 1’s complement is found by simply changing 1’s to 0’s and 0’s to
1’s. For example, the 1’s complement of 11001 is 00110.
Similarly, (r – 1)’s complement can also be found for the octal numbers by subtracting
each digit of the number from 7 and for hexadecimal numbers by subtracting each digit from
F.

r’s Complement:
The r’s complement (also called radix complement) of a positive number N is defined as rm –
N, where n is the number of digits in the integer part of N and r is the base of the number N.

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4 Data Representation and Computer Arithmetic

The r’s complement of a number can also be obtained by adding 1 to (r - 1)’s complement of
the number. This is because rm – N is equivalent to (rm - 1) – N + 1. Therefore, the 10’s
complement of a decimal number can be found by adding 1 to its 9’s complement and the 2’s
complement of a binary number can be found by adding 1 to its 1’s complement. For example,
the 10’s complement of a decimal number 43678 is 56321 + 1 = 56322 and the 2’s complement
of a binary number 101101 is 010010 + 1 = 010011.

The complement of a complement of a number is the original number. The r’s complement of N
is (rm – N). The complement of the complement is [rm – (rm – N)] = N, which is the original
number.

Binary Data Representation

The binary numbers are represented as either signed or unsigned numbers. An n-bit signed
binary number consists of two parts: one part denotes the sign of the number and another part
denotes the magnitude of the number. The most significant bit (MSB) is always a sign bit which
denotes the sign of the number and the convention is that 0 and 1 denote ‘+’ and ‘-’ respectively.
The remaining (n - 1) bits denote the magnitude of the number.

MSB LSB
Sign bit Magnitude
In some Applications, there is no need to include the sign along with the number while
representing the numbers into the computers. The numbers that have no sign associated with
them are called unsigned numbers. All the bits in an unsigned binary number represent the
magnitude of the number.

MSB LSB
Magnitude
In addition to sign, a number may also include a radix point, which needs to be stored in the
register along with the number. The position of radix point in the register indicates whether the
number stored is an integer, a fraction or mixed integer fraction. There are two ways to specify
the position of radix points in the register, which are fixed-point and floating-point
representation.

Fixed- point Representation:

In this representation, the position of radix point is fixed. Generally, it is either stored at the
extreme left in the register indicating that the number stored is a fractional number or at the
extreme right position indicating that the number stored is an integer. However, in any case,
the radix point is not actually stored in the register; its presence is presumed at a specific
position in the register depending on whether the number stored in the register is treated as an

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5 Data Representation and Computer Arithmetic

integer or a fraction. The fixed-point representation of the binary number +00110101.011001

is defined as:
Integer fraction

0 0 0 1 1 0 1 0 1 0 1 1 0 0 1

Sign bit Assumed radix point

An integer number is represented by a sign bit and the magnitude bits. For a positive integer,
the sign bit is 0 and a positive binary system represents the magnitude bits. However, for a
negative integer, the sign bit is 1 and rest of the number can be represented by one of the three
possible methods namely,
1. Signed-magnitude representation
2. Signed-1’s complement representation
3. Signed-2’s complement representation

▪ Signed-magnitude representation:
In the signed-magnitude representation, a bit known as the sign bit is used to indicate the sign
of the number. For a number containing n bits, the right most n-1 bits indicate the magnitude
of the number and the leftmost indicate the required sign bit. To determine whether a number
is positive or negative, two values, 0 and 1, are assigned which indicate the positive and
negative numbers, respectively.
For example, we have to represent -15 using the signed-magnitude method. If we have an 8-
bit format, then the signed-magnitude representation of -15 is:

+15 00001111
-15 10001111

▪ Signed-1’s complement representation:

In this representation, the negative number is represented in 1’s complement of its positive
value. The 1’s complement of a given number is obtained by complementing each digit of the
number, that is, replacing the 0’s with 1’s and 1’s with 0’s. Note that the sign bit is also
complemented. For example, the signed 1’s complement representation of -15 can be found by
taking the 1’s complement of the binary equivalent of +15 is shown here.

+15 00001111
(taking 1’s complement) -15 11110000

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6 Data Representation and Computer Arithmetic

▪ Signed 2’s complement representation:

In this representation, the negative number is represented in 2’s complement of its positive
value. The 2’s complement of a given number is calculated by adding 1 to the 1’s complement
of that number. For example, the signed 2’s complement representation of -15 can be found by
taking the 2’s complement of the binary equivalent of +15 as shown here.

+15 00001111
(1’s complement)
-15 11110000
+ 1
(2’s complement) 11110001

In signed-magnitude representation, the range for numbers using n-bit register is: -(2n-1 – 1) to
+(2n-1 – 1). So, there are two representations of 0 (+0 and -0). +0 has a value of 0 in the
magnitude field and sign bit is 0, while -0 has a value 0 in the magnitude field and sign bit is 1.
Signed-1’s complement method is useful as a logic operation since the change of 0 to 1 and 1 to
0 is equivalent to a logical complement operation, giving the representable range in n-bit is:
-(2n-1 – 1) to +(2n-1 – 1). but not usually used for arithmetic operation.
In signed-2’s complement representation, the range for numbers using n-bits is: -(2n-1) to +(2n-1 –
1). This range comes from the fact that there is only one representation for 0, allowing an odd-
number of non-zero values to be represented. Thus, the negative numbers are represented using
only signed-2’s complement method.

Arithmetic Operations on Fixed-Point Numbers:

✓ Arithmetic Addition:
The addition of two numbers in the sign-magnitude system is performed by the rules of
ordinary arithmetic.
1) If the signs are the same, we add the two magnitudes and give the sum the common
sign.
2) If the signs are different, we subtract the smaller magnitude from the larger and give
the result the sign of the larger magnitude.
For example, (+25) + (-37) = (37 - 25) = - 12 and is done by subtracting the
smaller magnitude 25 from the larger magnitude 37 and using the sign of 37 for the sign
of the result. This is a process that requires the comparison of the signs and the
magnitudes and then performing either addition or subtraction.
This method of addition is quite complex when it is implemented in computers.
However, the addition using singed-2’s complement method is very simple.

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7 Data Representation and Computer Arithmetic

The two numbers, including their sign bits, are added and the carry out from the sign (leftmost)
position is discarded, if any. For example,

+6 00000110 +6 00000110
+13 00001101 -13 11110011
+19 00010011 -7 11111001

-6 11111010
+13 00001101
+7 00000111

Negative results are automatically in 2’s complement form. For example, in last case, the
signed binary number 11111001 is a negative number because the leftmost bit is 1. So, it’s
magnitude’s 2’s complement is 00000111. That is the binary equivalent of +7. Therefore, the
result is -7.
✓ Arithmetic Subtraction:
Subtraction of two signed binary numbers when negative numbers are in 2' s complement form
is very simple and can be stated as follows: Take the 2's complement of the subtrahend
(including the sign bit) and add it to the minuend (including the sign bit). A carry out of the
sign bit position is discarded. The subtraction can be summarized with the relation:
A – B = A + 1’s complement of B + 1
This method of subtraction is obtained from the fact that the subtraction can be converted into
addition, if sign of the subtrahend is reversed.

(±A) - (+B) = (±A) + (-B)

(±A) - (-B) = (±A) + (+B)

Consider the subtraction (-9) – (-15) = +6. For 8-bit registers, this can be written as 11110111
+ 00001111 = 100000110. The correct answer is 00000110, after removing the end carry.

It is worth noting that binary numbers in the signed-2's complement system are added and
subtracted by the same basic addition and subtraction rules as unsigned numbers. Therefore,
computers need only one common hardware circuit to handle both types of arithmetic. The user
or programmer must interpret the results of such addition or subtraction differently depending
on whether it is assumed that the numbers are signed or unsigned.

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8 Data Representation and Computer Arithmetic

Important Note:
Overflow in Fixed-point Representation
During the addition operation of two numbers, there may arise a case when the sum contains
more digits than those of the actual numbers. This situation is known as an overflow which
is considered to be a problem in computers as the length of a computer register is finite. A
register having a length of n bits cannot store the result of n + 1 bits. Some conditions to be
kept in mind while dealing with overflow are as follows:
1. Overflow may occur only when both numbers being added are either positive or
negative.
2. Overflow does not occur if the numbers differ in their signs. This is because adding a
positive and a negative number of results in a number smaller than the larger of the
two numbers.
For example,
Carries: 01 Carries: 10
+69 0 1000101 -69 1 0111011
+78 0 1001110 -78 1 0110010
+147 1 0010011 -147 0 1101101

Observe that the 8-bit result that should have been positive (first example) has a negative sign
bit and the 8-bit result that should have been negative (second example) has a positive sign
bit. However, if the carry out from the sign bit position is treated as the sign of the result, the
9-bit answer thus obtained will be correct answer. Since the 9-bit answer cannot be
accommodated with 8-bit register, we say that an overflow result.

Floating-Point Representation:
In this representation, the radix point is not assumed to be fixed at a specific position. A
separate register is used, which stores a number specifying the position of radix point in the
register in which the number (without radix point) is stored.
In floating-point representation, a number has two parts. The first part is called mantissa or
fraction, to represent a signed fixed-point number, which may be a fraction or an integer. The
second part is called exponent, to designate the position of the radix point in mantissa. A given
number (say N) is represented in the form m * re, where r is the radix of N. For example, the
floating-point representation of the floating-point binary number +101.011 (for which r = 2) is
+ (0.101011) * 2+3.
When floating-point numbers are stored in the register, only the mantissa and exponent
including their signs are actually represented, while the radix and the position of radix point

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9 Data Representation and Computer Arithmetic

are always assumed. For example, if we have 8 bits for fraction (mantissa) and 6bits for
exponent, then the binary number +(.101011) *23 will be represented as,

0 1 0 1 0 1 1 0 0 0 0 0 1 1
Fraction Exponent
Sign bit
Here, the bit 0 at the leftmost position (sign bit) in the fraction indicates the positive number.
Following the sign bit of the fraction is the binary point that is assumed but not actually shown
in the register. The exponent holds the binary equivalent of +3. The floating-point
representation allows a wide range of values as compared to fixed-point representation;
however, it requires expensive hardware for being implemented.
When the most significant bit (left most) of the mantissa is nonzero, the floating-point number
is said to be normalized. For example, 0.00386 * 104 is not a normalized number. The
corresponding normalized number is 0.386 * 102. Similarly, the 8-bit binary number 00011100
is not normalized because of the three leading 0s. The number can be normalized by shifting it
three positions to the left and leaving out the leading zeros to obtain 11100000. But the left
shifting three positions means multiplication of the original number with 23 = 8. So, to retain
the value of number same, the exponent must be subtracted by 3.
IEEE Standards for Floating-point Representation:
The Institute of Electrical and Electronics Engineers (IEEE) has specified standards known as
IEEE 754 standard for representing the floating-point numbers in 32 bits and 64 bits. In case
of 32 bits, the floating-point numbers are said to be in single precision format, while in case of
64 bits, they are said to be in double precision format.
Single-precision Representation
In Single-precision representation, the 32 bits are divided into three groups. The first group
consists of a single bit called the sign bit which indicates the sign of the number. The second
group consisting of 8 bits is used to specify the exponent part. The exponent part e uses excess-
127 representation and stores an unsigned integer value e’ = e + 127. Thus, e’ lies in the range
of 0 to 255. However, the actual exponent lies in the range of -126 to +127.
The last group represents the mantissa fraction part (value after decimal point) and contains
23 bits. Since binary normalization is used, the most significant bit of the mantissa is always
set to 1. This bit is not explicitly represented; it is assumed to be to the immediate left of the
binary point. This bit is called hidden 1. Thus, the 23 bits stored in the mantissa M field actually
represent the fractional part of the mantissa, that is, the bits to the right of the binary point. In
general, all the components of double precision including sign bit, exponent, and mantissa
fraction part are substituted in the equation 1.M * 2(e’-127)

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10 Data Representation and Computer Arithmetic

32 bits Hidden 1 (not stored)

S e’ 1. M

Sign bit 8-bit signed exponent 23-bit mantissa

in excess-127 form

Double-precision Representation
In the Double-precision Representation of floating-point numbers, 64-bits are also divided into
three groups. The first group consisting of single bit indicates the sign of the number (0 for
positive and 1 for negative). However, in this format, the exponent and the mantissa parts have
higher number of bits and their range is also high. The exponent part e consisting of 11 bits
uses excess-1023 representation and thus stores an unsigned integer value e’ = e + 1023. The
mantissa part includes 52 bits (value after decimal point). In general, all the components of
double precision including sign bit, exponent, and mantissa fraction part are substituted in the
equation 1.M * 2(e’-1023).
64bits Hidden 1 (not stored)

S e’ 1. M

Sign bit 11-bit signed exponent 52-bit mantissa

in excess-1023 form

Examples:
1. Represent the number -208.102510 in single and double precision representation.
Ans: To represent the number -208.102510 in single and double precision, the steps involved
are as follows:
Step 1: Convert the decimal number into its binary equivalent. 0.1025 * 2 = 0.205 (0)
-20810 = (11010000)2 0.205 * 2 = 0.41 (0)

0.102510 = (0.0001)2 0.41 * 2 = 0.82 (0)

Therefore, -208.102510 = (-11010000.0001)2 0.82 * 2 = 1.64 (1)

Step 2: Normalize the number. 0.64 * 2 = 1.28 ……..

-11010000.0001 = -1.10100000001 * 27
Step 3: Now, represent the number in single and double precision as follows:

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 11 Data Representation and Computer Arithmetic

In case of Single Precision:

S = 1 (since it is a negative number)
e=7
M = 10100000001 (including the value after decimal point)
Bias of single precision is 127
Therefore, e’ = e + 127
= 7 + 127
= 13410
e’ = (10000110)2
Hence, the single precision number is represented as given below:

S e’ M
1 bit 8 bits 23 bits
1 10000110 10100000 00100000 0000000

In case of double Precision:

S = 1 (since it is a negative number)
e=7
M = 10100000001 (including the value after decimal point)
Bias of single precision is 1023
Therefore, e’ = e + 1023
= 7 + 1023
= 103010
e’ = (10000000110)2
Hence, the double precision number is represented as given below:

S e’ M
1 bit 11 bits 52 bits
1 10000000110 10100000 00100000 00000000 00000000 00000000 00000000 0000

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12 Data Representation and Computer Arithmetic

2. Represent the binary positive number 1101011 in the IEEE single-precision format.
Ans: To represent the binary positive number 1101011 in single precision, the steps involved
are as follows:
Step 1: Normalize the number.
+1101011 = + 1.101011 * 26
Step 2: Now, represent the number in single and double precision as follows:
S = 0 (since it is a positive number)
e=6
M = 0.101011 (including the value after decimal point)
Bias of single precision is 127
Therefore, e’ = e + 127
= 6 + 127
= 13310
e’ = (10000101)2
Hence, the single precision number is represented as given below:

S e’ M
1 bit 8 bits 23 bits
0 10000101 10101100 00000000 0000000

3. Convert the following IEEE single precision floating-point number to their decimal
value.
01000100101101101000010000000000000
Ans: The single precision number can be converted into its decimal equivalent by following
these steps.
Step 1: First separate the given number into its sign bit (S), exponent part (e) and the mantissa
part (M).
S (1 bit) = 0
e’ (8 bits) = 10001001 = 137
M (23 bits) = 011011010000100000000000
Step 2: Find the value of e.
It is known that e’ = e + 127
That is, e = e’ – 127

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 13 Data Representation and Computer Arithmetic

Therefore, e = 137 – 127

e = 10.
Step 3: The required values are
S=0
e = 10
M = 0110110100001 (discarding the additional zeros)

By substituting the above components in the equation 1.M x 2(e), we get

1.0110110100001 x 210 = (10110110100.001)2
Step 4: Convert the binary number to its decimal equivalent.
(10110110100.001)2 = (1460.125)10

Exercise:
1. Represent the decimal number -0.75 in the IEEE single-precision format.
2. Express the number .000021 in the floating-point form.
3. What decimal value is represented by the IEEE single precision floating point number.
0101 0101 0110 0000 0000 0000 0000 0000
4. A floating-point number system uses 16 bits for representing a number. The most significant bit is
the sign bit. The least significant nine bits represent the mantissa and remaining 6 bits represent the
exponent. Assume that the numbers are stored in the normalized format with one hidden bit.
a) Give the representation of -1.6 x 103 in this number system.
b) What is the value represented by 0 000100 110000000?

Sequential Multiplication Method for Unsigned Numbers

The multiplication operation involves multiplying the multiplicand with the multiplier bits and
adding the partial products together to get the final product. The flowchart for multiplication
of two n-bit numbers using add and shift operations is shown below.
Initially, the multiplicand is loaded into the register M, multiplier is loaded into the register Q,
product register is initialized to 0 and the sequence counter is initialized to n, the number of
bits in the multiplier. The F flip-flop holds the end carry generated in the addition. This flip-
flop F is used as the serial input, when the register pair AQ is shifted right one position. The
decision of whether the multiplicand is to be added to the product register is made by checking
the LSB of the multiplier register, which is Q[0].
If Q[0] = 1, the multiplicand is added to the product register A. On the other hand, if Q[0] =
0, nothing is added. In either case, FAQ is shifted to the right. This process continues until the
size becomes 0.
For example, consider the multiplication of 4-bit numbers M = 10 (1010)2 and Q = 14 (1110)2.

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14 Data Representation and Computer Arithmetic

Flowchart:

START

A = 0; F = 0
Q = Multiplier
M =Multiplicand
Size = n

Yes
Q[0] = 1? A=A+M

No

Right Shift (FAQ)

Size = Size - 1

Size = 0?
No

Yes

Product = AQ

END

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 15 Data Representation and Computer Arithmetic

Operations Multiplicand (M) F Accumulator (A) Multiplier (Q) Size (n)

0 0000 1110
Initial Configuration 1010 4

Step 1:
Q[0] = 0
Right shift (FAQ) 1010 0 0000 0111
Size = Size - 1 3

Step 2:
Q[0] = 1
1010 0 1010 0111
A=A+M
Right shift (FAQ) 1010 0 0101 0011

Size = Size - 1 2

Step 3:
Q[0] = 1
1010 0 1111 0011
A=A+M
Right shift (FAQ) 1010 0 0111 1001

Size = Size - 1 1

Step 4:
Q[0] = 1
1010 1 0001 1001
A=A+M
Right shift (FAQ) 1010 0 1000 1100

Size = Size - 1 0

Since, the size register is currently 0, the algorithm is terminated and the final product is
AQ = (1000 1100)2 = 14010
This method of multiplication is good for unsigned number multiplication. In case of signed
number multiplication, the signs of the operands can be treated separately and the
multiplication of magnitudes of the numbers can be processed using the above method. The
sign of the product is determined as Mn XOR Qn, where Mn, Qn are the signs of the
multiplicand(M) and the multiplier (Q) respectively.

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16 Data Representation and Computer Arithmetic

Booth Multiplication for Signed Numbers

We have seen in the previous sections that the multiplication of two numbers in signed
magnitude form is easy. But if the numbers are in 2’s complement form then the earlier method
cannot be used. The number may be converted to signed magnitude form firstly. Then the
product may be reconverted into 2’s complement form. This is time consuming. However,
Booth designed an algorithm for signed number multiplication which is popularly known as
Booth’s Algorithm. It works well for both negative and positive multipliers uniformly.
The booth algorithm generates a 2n-bit product and treats both positive and negative
2’s complement n-bit operands uniformly. To understand the essence of this algorithm,
consider a multiplication operation in which the multiplier is positive and has a single block of
1s, for example, 0011110 (equivalent decimal is 30). To derive the product, we could add four
appropriately shifted versions of the multiplicand, as in the standard procedure.
0 1 0 1 1 0 1 (45)
0 0 1 1 1 1 0 (30)

0 0 0 0 0 0 0
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0
However, we can reduce the number of required operations by regarding this multiplier as the
difference between two numbers:
0 1 0 0 0 0 0 (32)
0 0 0 0 0 1 0 (2)
0 0 1 1 1 1 0 (30)
The multiplication by 0011110 can be achieved by summing up the following two products:
a) 25 times the multiplicand.
b) 2’s complement of 21 times the multiplicand.
In sequential multiplication method, four additions are required due to the string of four 1s.
This can be replaced by one addition and one subtraction. This is one significant advantage of
Booth’s multiplication method over sequential multiplication method.
Actually, Booth’s Algorithm involves recoding of the multiplier, firstly, in recoding format,
each bit in the multiplier can take any of the three values: 0, 1, -1

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17 Data Representation and Computer Arithmetic

How to recode the multiplier now?

The recoding rule on multiplier can be summarized as below:
Step 1: We assume an implied 0 to the right of the multiplier LSB.
Step 2: Start searching 1 from LSB (right most bit). Skip all 0s and continue the search till first
1 encountered.
Step 3: Change the first 1 in multiplier as -1.
Step 4: Search for a 0 one by one without disturbing all succeeding 1s; just recode them(1s) as
0s. When a 0 is encountered, change this 0 to 1.
Step 4: Proceed to look for next 1 without disturbing 0s and continue using steps 3 and 4.

Ai Ai-1 Recoding for Ai Remarks on multiplier

0 0 0 Sequence of 0s
1 0 -1 Start of sequence of 1s
0 1 1 End of sequence of 1s
1 1 0 Sequence of 1s

Examples:
Convert the following numbers into Booth’s recoded format:
a) 01111
b) 0011110
c) 101100 Implied zero
Ans: a) 0 1 1 1 1 0
Using the rule given above, we recode it as follows:
1 0 0 0 -1 (move from right to left and use the steps stated above)

24 (16) 23 (8) 22 (4) 21 (2) 20 (1)

0 1 1 1 1 15
1 0 0 0 -1 15

b) 0 0 1 1 1 1 0 0
Using the rule given above, we recode it as follows:
0 1 0 0 0 -1 0 (move from right to left and use the steps stated above)

26 (64) 25 (32) 24 (16) 23 (8) 22 (4) 21 (2) 20 (1)

0 0 1 1 1 1 0 30
0 1 0 0 0 -1 0 30

[Compiled by Surajit Das]

 18 Data Representation and Computer Arithmetic

c) 1 0 1 1 0 0 0
Using the rule given above, we recode it as follows:
-1 1 0 -1 0 0 (move from right to left and use the steps stated above)

25 (32) 24 (16) 23 (8) 22 (4) 21 (2) 20 (1)

1 0 1 1 0 0 20
-1 1 0 -1 0 0 20

Exercise:
1. Convert the following numbers into Booth’s recoded representation:
a) 011001
b) 11011
c) 001100
d) 101100
e) 1100 1010
f) 1110 1101

Booth multiplication of the above example is:

0 1 0 1 1 0 1 (45)
0 1 0 0 0 -1 0 (30)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 0 1 0 0 1 1 2’s complement of the multiplicand
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0
Based on this recoding rule, the booth’s algorithm for multiplication can be developed easily.
The Algorithm inspects two lower-order multiplier bits at time to take the next step of action.
A flip-flop is used to the right of LSB of the multiplier and it is initialized to 0. Subsequently,
it receives the LSB of the multiplier when the multiplier is shifted right.

[Compiled by Surajit Das]

19 Data Representation and Computer Arithmetic

Flowchart:

START

A = 0; Q[-1] = 0
Q = Multiplier
M =Multiplicand
Size = n

No No
Q[0] = 0 Q[0] = 1
and and
Q[-1] = 1 Q[-1] = 0

Yes Yes

A=A+M A=A-M

Arithmetic Right Shift (AQ)

Size = Size - 1

No Size = 0?

Yes

Product = AQ

END

[Compiled by Surajit Das]

20 Data Representation and Computer Arithmetic

To see how this procedure works, the following examples are considered.
1. M = -7 (1001)2
Q = +3 (0011)2

Multiplicand
Operations Accumulator (A) Multiplier (Q) Size (n)
(M)

Initial Configuration 1001 0000 0011 0 4

Step 1:
Q[0] = 1 and Q[-1] = 0
A=A–M 1001 0111 0011 0

ARS (AQ) 1001 0011 1001 1

Size = Size - 1 3

Step 2:
Q[0] = 1 and Q[-1] = 1
No update of A 1001 0011 1001 1

ARS (AQ) 1001 0001 1100 1

Size = Size - 1 2

Step 3:
Q[0] = 0 and Q[-1] = 1
1001 1010 1100 1
A=A+M
ARS (AQ) 1001 1101 0110 0

Size = Size - 1 1

Step 4:
Q[0] = 0 and Q[-1] = 0
1001 1101 0110 0
No update of A
ARS (AQ) 1001 1110 1011 0

Size = Size - 1 0

Since, the size register becomes 0, the algorithm is terminated and the product is AQ = 1110
1011, which shows that product is a negative number. To get the number in familiar form, take
the 2’s complement of the magnitude. The result is (– 21).

[Compiled by Surajit Das]

21 Data Representation and Computer Arithmetic

2. M = -7 (1001)2
Q = -3 (1101)2

Multiplicand
Operations Accumulator (A) Multiplier (Q) Size (n)
(M)

Initial Configuration 1001 0000 1101 0 4

Step 1:
Q[0] = 1 and Q[-1] = 0
A=A–M 1001 0111 1101 0

ARS (AQ) 1001 0011 1110 1

Size = Size - 1 3

Step 2:
Q[0] = 0 and Q[-1] = 1
A=A+M 1001 1100 1110 1

ARS (AQ) 1001 1110 0111 0

Size = Size - 1 2

Step 3:
Q[0] = 1 and Q[-1] = 0
1001 0101 0111 0
A=A-M
ARS (AQ) 1001 0010 1011 1

Size = Size - 1 1

Step 4:
Q[0] = 1 and Q[-1] = 1
1001 0010 1011 1
No update of A
ARS (AQ) 1001 0001 0101 1

Size = Size - 1 0

Since, the size register becomes 0, the algorithm is terminated and the product is AQ = 0001
0101, which shows that the product is a positive number. The result is +21.

[Compiled by Surajit Das]

 22 Data Representation and Computer Arithmetic

Exercise:
1. Apply Booth’s algorithm to multiply the two numbers (+14)10 and (-12)10. Assume the multiplier and
multiplicand to be of 5 bits each.
2. Apply Booth’s algorithm to multiply the two numbers (+15)10 and (+11)10. Assume the multiplier and
multiplicand to be of 5 bits each.

Division of Unsigned Integer

The division is more complex operation than multiplication. Given a dividend (D) and a divisor
(V), the quotient (Q) and the remainder (R) are related according to the following expression:
D = QV + R, where 0 ≤ R < V
Division with binary data is simpler as compared to dividing decimal data because in binary
division, the quotient digits are either 0 or 1 and estimating the number of times the dividend
For example, consider the division of 11001 by 101. Here, X = 11001 and Y = 101.

1 0 1 Quotient
A B Diff Borrow
1 0 1 1 1 0 0 1
0 0 0 0
1 0 1
0 1 1 1
0 0 1 0 1
1 0 1 0
1 1 0 0 1 0 1
0 Remainder
In this method, every iteration generates one quotient bit, First, align the divisor the dividend
from MSB and try to subtract it from the dividend. If the result of the subtraction is positive,
then put a 1 for the quotient, and shift the divisor one position to the right. This process is
repeated. However, if the divisor cannot be subtracted from the dividend for a positive result,
put a 0 for the quotient and shift the divisor to the right. Then, try to subtract the same from the
dividend. This process continues until all bits of the dividend are covered.
Division can be performed using three techniques which are as follows:
▪ Restoring technique
▪ Non- restoring technique
▪ Comparison technique.

[Compiled by Surajit Das]

23 Data Representation and Computer Arithmetic

Restoring Division Method:

In this method, dividend is shifted to the left instead of shifting the divisor. For dividing two
n-bit numbers, three n-bit registers A,M,Q are used in this method. Divisor is stored in the M
register. Initially, A contains 0 and Q holds the n-bit dividend. In each iteration, the contents
of register-pair AQ are shifted to the left first. The content of M is then subtracted from A. If
the result of subtraction is positive, a 1 is placed into the vacant position created in LSB position
of Q by the left shift operation; otherwise a 0 is put into this position and before beginning the
next iteration, restore the content of A by adding the current content of A register with M.
When, the algorithm terminates, the A register contains the remainder result and Q register
contains the quotient result.
Flowchart:
START

A=0
Q = Dividend Here, n is the no. of bits in Q
M =Divisor
Size = n

Left shift (AQ)

A=A-M

Sign of A No
A=A+M
Q[0] = 0
= 0?

Yes
Q[0] = 1

Size = Size - 1

No
Size = 0?

Yes
Quotient = Q
Remainder = A

END
[Compiled by Surajit Das]
24 Data Representation and Computer Arithmetic

To see how this procedure works, the following examples are considered.
Dividend Q = 20 (10100)2 and Divisor M = 3 (00011)2

Operations Divisor (M) Accumulator (A) Dividend (Q) Size (n)

Initial Configuration 000011 000000 10100 5

Step 1: LS(AQ) 000011 000001 0100_

A=A–M 000011 111110 0100_
As sign A = -ve
Set Q[0] = 0 000011 111110 01000

And restore A 000011 000001 01000 4

Step 2: LS(AQ) 000011 000010 1000_
A=A–M 000011 111111 1000_
As sign A = -ve
Set Q[0] = 0 000011 111111 10000

And restore A 000011 000010 10000 3

Step 3: LS(AQ) 000011 000101 0000_
A=A–M 000011 000010 0000_
As sign A = +ve
Set Q[0] = 1 000011 000010 00001 2
Step 4: LS(AQ) 000011 000100 0001_
A=A–M 000011 000001 0001_
As sign A = +ve
Set Q[0] = 1 000011 000001 00011 1
Step 5: LS(AQ) 000011 000010 0011_
A=A–M 000011 111111 0011_
As sign A = -ve
Set Q[0] = 0 000011 111111 00110
And restore A 000011 000010 00110 0

From the above result, we see that quotient (Q) = 00110= 6 and remainder (A) = 000010 = 2.

[Compiled by Surajit Das]

 25 Data Representation and Computer Arithmetic

Exercise:
1. Apply restoring division procedure to divide decimal number 7 by decimal number 3.
2. Apply restoring division procedure to divide decimal number 163 by decimal number 11.

Non-Restoring Division Method:

In the previous resorting method, when A is negative some extra additions are required to
restore the number. The non-restoring division technique skips the restoring step and works
with the negative residual.
The arithmetic actions in register A depends non the following two cases.
Case 1: when A is negative:
Left shift AQ and then A will be added with M register.
If sign of A is negative set Q[0] = 0 else set Q[0] = 1.
Case 2: when A is positive:
Left shift AQ and then A will be subtracted form M register.
If sign of A is negative set Q[0] = 0 else set Q[0] = 1.
Basis on these two observations, we can design the non-restoring division method and it will
be described using a flowchart.
This algorithm removes the restoration step, though it may require a restoration step at the end
of the algorithm for remainder A, if A is negative.

[Compiled by Surajit Das]

26 Data Representation and Computer Arithmetic

Flowchart: START

A=0
Q = Dividend
M =Divisor
Size = n

Sign of A
No
= 0?

Yes
Left Shift (AQ) Left Shift (AQ)

A=A-M A=A+M

No
Sign of
A = 0?

Yes
Set Q[0] = 1 Set Q[0] = 0

Size = Size - 1

No
Size = 0?

Yes

Sign of No
A = 0?
A=A+M
Yes

Quotient = Q
Remainder = A

[Compiled by Surajit Das] END

27 Data Representation and Computer Arithmetic

Example:
Let us take an example where dividend Q = 7 (0111)2 and divisor M = 3 (0011)2

Operations Divisor (M) Accumulator (A) Dividend (Q) Size (n)

Initial Configuration 00011 00000 0111 4

Step 1: sign of A =
+ve, LS (AQ) 00011 00000 111_

A=A–M 00011 11101 111_

As sign of A = -ve Set
Q[0] = 0 00011 11101 1110
Size = Size - 1 3

Step 2: sign of A = - 00011 11011 110_

ve, LS (AQ)
A=A+M 00011 11110 110_

As sign of A = -ve Set

Q[0] = 0 00011 11110 1100
Size = Size - 1 2

Step 3: sign of A = - 00011 11101 100_

ve, LS (AQ)
A=A+M 00011 00000 100_

As sign of A = +ve
Set Q[0] = 1 00011 00000 1001
Size = Size - 1
1
Step 4: Step 1: sign
00011 00001 001_
of A = +ve, LS (AQ)
A=A–M 00011 11110 001_
As sign of A = -ve Set
Q[0] = 0 00011 11110 0010

Size = Size - 1 0

Step 5: Restore A 00011 00001 0010

From the last step, we conclude that quotient = (0010)2 = 2 and remainder = (00001)2 = 1.

[Compiled by Surajit Das]

 28 Data Representation and Computer Arithmetic

Exercise:
1. Show the steps for non-restoring method of division when 9 is divided by 2 using 4-bit representation.
2. Show the steps for non-restoring method of division when 11 is divided by 3.

[Compiled by Surajit Das]