ESP32­C3 Series

Datasheet

Ultra­Low­Power SoC with RISC­V Single­Core CPU

Supporting IEEE 802.11b/g/n (2.4 GHz Wi­Fi) and Bluetooth® 5 (LE)

Including:
ESP32-C3

ESP32-C3FN4

ESP32-C3FH4

ESP32-C3FH4AZ

Version 1.4
Espressif Systems
Copyright © 2022

www.espressif.com
Product Overview

ESP32-C3 series of SoCs is an ultra-low-power and highly-integrated MCU-based solution that supports 2.4
GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). The block diagram of ESP32-C3 is shown below.

Espressif’s ESP32-C3 Wi-Fi + Bluetooth® Low Energy SoC

Core System Wireless MAC and RF

Baseband
2.4 GHz Balun + Switch
RISC-V
32-bit Wi-Fi
Wi-Fi MAC
Microprocessor Baseband 2.4 GHz Transmitter

Bluetooth LE 2.4 GHz Receiver

Cache SRAM Link Controller

Bluetooth LE RF Synthesizer
JTAG ROM Baseband

RTC
Peripherals RTC
PMU
Memory
SPI0/1 I2C GPIO RTC GPIO
Brownout Detector
SPI2
⚙ I2S UART
eFuse
Controller
Security
TWAI® RMT RTC Super Watchdog Timer ⚙ ⚙
SHA RSA
⚙ DIG ADC
GDMA
Controller
RTC Watchdog Timer
AES
⚙ RNG
USB Serial/ Temperature
HMAC ⚙
LED PWM System Timer Digital ⚙
JTAG Sensor Signature

Main System Watchdog Timers Secure ⚙ Flash

General-purpose Timers
Boot Encryption

Modules having power in specific power modes:

Active
Active and Modem-sleep
Active, Modem-sleep, and Light-sleep; ⚙ optional in Light-sleep
All modes

Figure 1: Block Diagram of ESP32­C3

Solution Highlights
• A complete Wi­Fi subsystem that complies • Storage capacities ensured by 400 KB of
with IEEE 802.11b/g/n protocol and supports SRAM (16 KB for cache) and 384 KB of ROM on
Station mode, SoftAP mode, SoftAP + Station the chip, and SPI, Dual SPI, Quad SPI, and QPI
mode, and promiscuous mode interfaces that allow connection to external flash

• A Bluetooth LE subsystem that supports • Reliable security features ensured by

features of Bluetooth 5 and Bluetooth mesh – Cryptographic hardware accelerators that
• 32­bit RISC­V single­core processor with a support AES-128/256, Hash, RSA, HMAC,
four-stage pipeline that operates at up to 160 digital signature and secure boot
MHz – Random number generator
• State­of­the­art power and RF performance – Permission control on accessing internal

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 memory, external memory, and peripherals • Rich set of peripheral interfaces and GPIOs,
ideal for various scenarios and complex
– External memory encryption and decryption
applications

Features
Wi­Fi • CoreMark® score:

• IEEE 802.11 b/g/n-compliant – 1 core at 160 MHz: 407.22 CoreMark; 2.55

CoreMark/MHz
• Supports 20 MHz, 40 MHz bandwidth in 2.4
GHz band • 384 KB ROM

• 1T1R mode with data rate up to 150 Mbps • 400 KB SRAM (16 KB for cache)

• Wi-Fi Multimedia (WMM) • 8 KB SRAM in RTC

• TX/RX A-MPDU, TX/RX A-MSDU • Embedded flash (see details in Chapter 1

ESP32-C3 Series Comparison)
• Immediate Block ACK
• SPI, Dual SPI, Quad SPI, and QPI interfaces that
• Fragmentation and defragmentation
allow connection to multiple external flash
• Transmit opportunity (TXOP)
• Access to flash accelerated by cache
• Automatic Beacon monitoring (hardware TSF)
• Supports flash in-Circuit Programming (ICP)
• 4 × virtual Wi-Fi interfaces

• Simultaneous support for Infrastructure BSS in

Advanced Peripheral Interfaces
Station mode, SoftAP mode, Station + SoftAP
mode, and promiscuous mode • 22 or 16 programmable GPIOs
Note that when ESP32-C3 scans in Station mode, • Digital interfaces:
the SoftAP channel will change along with the
– 3 × SPI
Station channel
– 2 × UART
• 802.11mc FTM
– 1 × I2C
Bluetooth – 1 × I2S

• Bluetooth LE: Bluetooth 5, Bluetooth mesh – Remote control peripheral, with 2 transmit
channels and 2 receive channels
• High power mode (21 dBm)
– LED PWM controller, with up to 6 channels
• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
– Full-speed USB Serial/JTAG controller
• Advertising extensions
– General DMA controller (GDMA), with 3
• Multiple advertisement sets
transmit channels and 3 receive channels
• Channel selection algorithm #2
– 1 × TWAI® controller compatible with ISO
• Internal co-existence mechanism between Wi-Fi 11898-1 (CAN Specification 2.0)
and Bluetooth to share the same antenna
• Analog interfaces:

CPU and Memory – 2 × 12-bit SAR ADCs, up to 6 channels

• 32-bit RISC-V single-core processor, up to 160 – 1 × temperature sensor

MHz • Timers:

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 – 2 × 54-bit general-purpose timers • Flash encryption

– 3 × digital watchdog timers • 4096-bit OTP, up to 1792 bits for use

– 1 × analog watchdog timer • Cryptographic hardware acceleration:

– 1 × 52-bit system timer – AES-128/256 (FIPS PUB 197)

• Permission Control
Low Power Management • SHA Accelerator (FIPS PUB 180-4)

• Power Management Unit with four power modes • RSA Accelerator

• Random Number Generator (RNG)

Security • HMAC

• Secure boot • Digital signature

Applications (A Non­exhaustive List)

With ultra-low power consumption, ESP32-C3 is an ideal choice for IoT devices in the following areas:

• Smart Home – Wi-Fi speaker

– Light control – Logger toys and proximity sensing toys

– Smart button • Smart Agriculture

– Smart plug – Smart greenhouse

– Indoor positioning – Smart irrigation

• Industrial Automation – Agriculture robot

– Industrial robot • Retail and Catering

– Mesh network – POS machines

– Human machine interface (HMI) – Service robot

– Industrial field bus • Audio Device

• Health Care – Internet music players

– Health monitor – Live streaming devices

– Baby monitor – Internet radio players

• Consumer Electronics • Generic Low-power IoT Sensor Hubs

– Smart watch and bracelet • Generic Low-power IoT Data Loggers

– Over-the-top (OTT) devices

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Contents

Contents

Product Overview 2
Solution Highlights 2
Features 3
Applications 4

1 ESP32­C3 Series Comparison 9

1.1 ESP32-C3 Series Nomenclature 9
1.2 Comparison 9

2 Pin Definition 10
2.1 Pin Layout 10
2.2 Pin Description 11
2.3 Power Scheme 13
2.4 Strapping Pins 14

3 Functional Description 17
3.1 CPU and Memory 17
3.1.1 CPU 17
3.1.2 Internal Memory 17
3.1.3 External Flash 17
3.1.4 Address Mapping Structure 18
3.1.5 Cache 18
3.2 System Clocks 19
3.2.1 CPU Clock 19
3.2.2 RTC Clock 19
3.3 Analog Peripherals 19
3.3.1 Analog-to-Digital Converter (ADC) 19
3.3.2 Temperature Sensor 20
3.4 Digital Peripherals 20
3.4.1 General Purpose Input / Output Interface (GPIO) 20
3.4.2 Serial Peripheral Interface (SPI) 22
3.4.3 Universal Asynchronous Receiver Transmitter (UART) 23
3.4.4 I2C Interface 23
3.4.5 I2S Interface 24
3.4.6 Remote Control Peripheral 24
3.4.7 LED PWM Controller 24
3.4.8 General DMA Controller 24
3.4.9 USB Serial/JTAG Controller 25
®
3.4.10 TWAI Controller 25
3.5 Radio and Wi-Fi 25
3.5.1 2.4 GHz Receiver 26
3.5.2 2.4 GHz Transmitter 26
3.5.3 Clock Generator 26

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Contents

3.5.4 Wi-Fi Radio and Baseband 26

3.5.5 Wi-Fi MAC 26
3.5.6 Networking Features 27
3.6 Bluetooth LE 27
3.6.1 Bluetooth LE Radio and PHY 27
3.6.2 Bluetooth LE Link Layer Controller 27
3.7 Low Power Management 28
3.8 Timers 28
3.8.1 General Purpose Timers 28
3.8.2 System Timer 29
3.8.3 Watchdog Timers 29
3.9 Cryptographic Hardware Accelerators 30
3.10 Physical Security Features 30
3.11 Peripheral Pin Configurations 30

4 Electrical Characteristics 33
4.1 Absolute Maximum Ratings 33
4.2 Recommended Operating Conditions 33
4.3 VDD_SPI Output Characteristics 33
4.4 DC Characteristics (3.3 V, 25 °C) 34
4.5 ADC Characteristics 34
4.6 Current Consumption 35
4.6.1 RF Current Consumption in Active Mode 35
4.6.2 Current Consumption in Other Modes 35
4.7 Reliability 36
4.8 Wi-Fi Radio 36
4.8.1 Wi-Fi RF Transmitter (TX) Specifications 37
4.8.2 Wi-Fi RF Receiver (RX) Specifications 37
4.9 Bluetooth LE Radio 39
4.9.1 Bluetooth LE RF Transmitter (TX) Specifications 39
4.9.2 Bluetooth LE RF Receiver (RX) Specifications 40

5 Package Information 43

6 Related Documentation and Resources 44

Revision History 45

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List of Tables

List of Tables
1 ESP32-C3 Series Comparison 9
2 Pin Description 11
3 Description of ESP32-C3 Power-up and Reset Timing Parameters 14
4 Strapping Pins 15
5 Parameter Descriptions of Setup and Hold Times for the Strapping Pins 16
6 IO MUX Pin Functions 20
7 Power-Up Glitches on Pins 22
8 Mapping of SPI Signals and Chip Pins 23
9 Connection Between ESP32-C3 and External Flash 23
10 Peripheral Pin Configurations 30
11 Absolute Maximum Ratings 33
12 Recommended Operating Conditions 33
13 VDD_SPI Output Characteristics 33
14 DC Characteristics (3.3 V, 25 °C) 34
15 ADC Characteristics 34
16 ADC Calibration Results 35
17 Current Consumption Depending on RF Modes 35
18 Current Consumption in Modem-sleep Mode 35
19 Current Consumption in Low-Power Modes 36
20 Reliability Qualifications 36
21 Wi-Fi Frequency 36
22 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 37
23 TX EVM Test 37
24 RX Sensitivity 37
25 Maximum RX Level 38
26 RX Adjacent Channel Rejection 38
27 Bluetooth LE Frequency 39
28 Transmitter Characteristics - Bluetooth LE 1 Mbps 39
29 Transmitter Characteristics - Bluetooth LE 2 Mbps 39
30 Transmitter Characteristics - Bluetooth LE 125 Kbps 40
31 Transmitter Characteristics - Bluetooth LE 500 Kbps 40
32 Receiver Characteristics - Bluetooth LE 1 Mbps 41
33 Receiver Characteristics - Bluetooth LE 2 Mbps 41
34 Receiver Characteristics - Bluetooth LE 125 Kbps 42
35 Receiver Characteristics - Bluetooth LE 500 Kbps 42

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List of Figures

List of Figures
1 Block Diagram of ESP32-C3 2
2 ESP32-C3 Series Nomenclature 9
3 ESP32-C3 Pin Layout (Top View, Excluding ESP32-C3FH4AZ) 10
4 ESP32-C3FH4AZ Pin Layout (Top View) 11
5 ESP32-C3 Power Scheme 13
6 ESP32-C3 Power-up and Reset Timing 14
7 Setup and Hold Times for the Strapping Pins 15
8 Address Mapping Structure 18
9 QFN32 (5×5 mm) Package 43

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1 ESP32-C3 Series Comparison

1. ESP32­C3 Series Comparison

1.1 ESP32­C3 Series Nomenclature

ESP32-C3 F H x AZ

Other Identification Code

Flash

Flash temperature
H: High temperature
N: Normal temperature

Flash

Chip series

Figure 2: ESP32­C3 Series Nomenclature

1.2 Comparison
Table 1: ESP32­C3 Series Comparison

Ordering Code Embedded Flash Ambient Temperature (°C) Package (mm) GPIO No.
ESP32-C3 1
— –40 ∼ 105 QFN32 (5*5) 22
ESP32-C3FN4 4 MB –40 ∼ 85 QFN32 (5*5) 22
ESP32-C3FH4 4 MB –40 ∼ 105 QFN32 (5*5) 22
ESP32-C3FH4AZ 2
4 MB –40 ∼ 105 QFN32 (5*5) 16
1
ESP32-C3 requires an external SPI flash.
2
For ESP32-C3FH4AZ, SPI0/SPI1 pins for flash connection are not bonded. For details, see Note 7
under Table 2 Pin Description.

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2 Pin Definition

2. Pin Definition
2.1 Pin Layout

26 GPIO19

25 GPIO18
29 XTAL_N
30 XTAL_P

27 U0RXD
28 U0TXD
32 VDDA

31 VDDA
LNA_IN 1 24 SPIQ

VDD3P3 2 23 SPID

VDD3P3 3 22 SPICLK

XTAL_32K_P 4 21 SPICS0

XTAL_32K_N 5 20 SPIWP

GPIO2 6
ESP32-C3 19 SPIHD

CHIP_EN 7 18 VDD_SPI

GPIO3 8 33 GND 17 VDD3P3_CPU

MTDI 10

VDD3P3_RTC 11

MTCK 12

MTDO 13

GPIO8 14

GPIO9 15

GPIO10 16
9
MTMS

Figure 3: ESP32­C3 Pin Layout (Top View, Excluding ESP32­C3FH4AZ)

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2 Pin Definition

26 GPIO19

25 GPIO18
29 XTAL_N
30 XTAL_P

27 U0RXD
28 U0TXD
32 VDDA

31 VDDA
LNA_IN 1 24 NC

VDD3P3 2 23 NC

VDD3P3 3 22 NC

XTAL_32K_P 4 21 NC

XTAL_32K_N 5 20 NC

GPIO2 6
ESP32-C3FH4AZ 19 NC

CHIP_EN 7 18 VDD_SPI

GPIO3 8 33 GND 17 VDD3P3_CPU

MTDI 10

VDD3P3_RTC 11

MTCK 12

MTDO 13

GPIO8 14

GPIO9 15

GPIO10 16
9
MTMS

Figure 4: ESP32­C3FH4AZ Pin Layout (Top View)

2.2 Pin Description

Table 2: Pin Description

Name No. Type Power Domain Function

LNA_IN 1 I/O — RF input and output
VDD3P3 2 PA — Analog power supply
VDD3P3 3 PA — Analog power supply
XTAL_32K_P 4 I/O/T VDD3P3_RTC GPIO0, ADC1_CH0, XTAL_32K_P
XTAL_32K_N 5 I/O/T VDD3P3_RTC GPIO1, ADC1_CH1, XTAL_32K_N
GPIO2 6 I/O/T VDD3P3_RTC GPIO2, ADC1_CH2, FSPIQ
High: on, enables the chip.
CHIP_EN 7 I VDD3P3_RTC Low: off, the chip powers off.
Note: Do not leave the CHIP_EN pin floating.

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2 Pin Definition

Name No. Type Power Domain Function

GPIO3 8 I/O/T VDD3P3_RTC GPIO3, ADC1_CH3
MTMS 9 I/O/T VDD3P3_RTC GPIO4, ADC1_CH4, FSPIHD, MTMS
MTDI 10 I/O/T VDD3P3_RTC GPIO5, ADC2_CH0, FSPIWP, MTDI
VDD3P3_RTC 11 PD — Input power supply for RTC
MTCK 12 I/O/T VDD3P3_CPU GPIO6, FSPICLK, MTCK
MTDO 13 I/O/T VDD3P3_CPU GPIO7, FSPID, MTDO
GPIO8 14 I/O/T VDD3P3_CPU GPIO8
GPIO9 15 I/O/T VDD3P3_CPU GPIO9
GPIO10 16 I/O/T VDD3P3_CPU GPIO10, FSPICS0
VDD3P3_CPU 17 PD — Input power supply for CPU IO
VDD_SPI 7
18 I/O/T/PD VDD3P3_CPU GPIO11, output power supply for flash6
SPIHD 19 I/O/T VDD3P3_CPU GPIO12, SPIHD
SPIWP 20 I/O/T VDD3P3_CPU GPIO13, SPIWP
SPICS0 21 I/O/T VDD3P3_CPU GPIO14, SPICS0
SPICLK 22 I/O/T VDD3P3_CPU GPIO15, SPICLK
SPID 23 I/O/T VDD3P3_CPU GPIO16, SPID
SPIQ 24 I/O/T VDD3P3_CPU GPIO17, SPIQ
GPIO18 25 I/O/T VDD3P3_CPU GPIO18, USB_D­
GPIO19 26 I/O/T VDD3P3_CPU GPIO19, USB_D+
U0RXD 27 I/O/T VDD3P3_CPU GPIO20, U0RXD
U0TXD 28 I/O/T VDD3P3_CPU GPIO21, U0TXD
XTAL_N 29 — — External crystal output
XTAL_P 30 — — External crystal input
VDDA 31 PA — Analog power supply
VDDA 32 PA — Analog power supply
GND 33 G — Ground
1
PA : analog power supply; PD : power supply for RTC IO; I: input; O: output; T: high impedance.
2
Pin functions in bold font are the default pin functions in SPI boot mode.
3
Ports of embedded flash correspond to pins of ESP32-C3FN4 and ESP32-C3FH4 as follows:
• CS# = SPICS0
• IO0/DI = SPID
• IO1/DO = SPIQ
• CLK = SPICLK
• IO2/WP# = SPIWP
• IO3/HOLD# = SPIHD
These pins are not recommended for other uses.
4
For the data port connection between ESP32-C3 and external flash please refer to Section 3.4.2 Serial Peripheral
Interface (SPI).
5
The pin function in this table refers only to some fixed settings and do not cover all cases for signals that can be
input and output through the GPIO matrix. For more information on the GPIO matrix, please refer to Chapter IO
MUX and GPIO Matrix (GPIO, IO_MUX) in ESP32-C3 Technical Reference Manual.
6
By default VDD_SPI is the power supply pin for embedded flash or external flash. It can only be used as GPIO11
only when the chip is connected to an external flash, and this flash is powered by an external power supply.
7
For ESP32-C3FH4AZ, pins within the frame (namely pin 19 ∼ pin 24) are not bonded, and are labelled as ”not
connected”.
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2 Pin Definition

2.3 Power Scheme

ESP32-C3 has four input power pins:

• VDDA1

• VDDA2

• VDD3P3_RTC

• VDD3P3_CPU

And one input/output power pin:

• VDD_SPI

VDDA1 and VDDA2 are the input power supply for the analog domain.

When working as an output power supply, VDD_SPI can be powered by VDD3P3_CPU via RSP I (nominal 3.3 V).
VDD_SPI can be powered off via software to minimize the current leakage of flash in Deep-sleep mode.

RTC IO is powered from VDD3P3_RTC.

The RTC domain is powered from Low Power Voltage Regulator, which is powered from VDD3P3_RTC.

The Digital System domain is powered from Digital System Voltage Regulator, which is powered from
VDD3P3_CPU and VDD3P3_RTC at the same time.

Digital IO is powered from VDD3P3_CPU.

The power scheme diagram is shown in Figure 5.

Figure 5: ESP32­C3 Power Scheme

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2 Pin Definition

Notes on CHIP_EN:

Figure 6 shows the power-up and reset timing of ESP32-C3. Details about the parameters are listed in Table
3.

t0 t1

2.8 V

VDDA,
VDD3P3,
VDD3P3_RTC,
VDD3P3_CPU

VIL_nRST
CHIP_EN

Figure 6: ESP32­C3 Power­up and Reset Timing

Table 3: Description of ESP32­C3 Power­up and Reset Timing Parameters

Min
Parameter Description (µs)
Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and
t0 50
VDD3P3_CPU rails, and activating CHIP_EN
Duration of CHIP_EN signal level < VIL_nRST (refer to its value in
t1 50
Table 14) to reset the chip

2.4 Strapping Pins

ESP32-C3 has three strapping pins:

• GPIO2

• GPIO8

• GPIO9

Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG
register. For register description, please refer to Section GPIO Matrix Register Summary in
ESP32-C3 Technical Reference Manual.

During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0”
or ”1”, and hold these bits until the chip is powered down or shut down.

Types of system reset include:

• power-on reset

• RTC watchdog reset

• brownout reset

• analog super watchdog reset

• crystal clock glitch detection reset

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2 Pin Definition

By default, GPIO9 is connected to the internal weak pull-up resistor. If GPIO9 is not connected or connected to
an external high-impedance circuit, the latched bit value will be ”1”

To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-C3.

After reset, the strapping pins work as normal-function pins.

Table 4 lists detailed booting configurations of the strapping pins.

Table 4: Strapping Pins

Booting Mode 1
Pin Default SPI Boot Download Boot
GPIO2 N/A 1 1
GPIO8 N/A Don’t care 1
Internal weak
GPIO9 1 0
pull-up
Enabling/Disabling ROM Messages Print in SPI Boot Mode
Pin Default Functionality
When the value of eFuse field EFUSE_UART_PRINT_CONTROL is
0 (default), print is enabled and not controlled by GPIO8.
GPIO8 N/A 1, if GPIO8 is 0, print is enabled; if GPIO8 is 1, it is disabled.
2, if GPIO8 is 0, print is disabled; if GPIO8 is 1, it is enabled.
3, print is disabled and not controlled by GPIO8.
1
The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected be-
havior.

Figure 7 shows the setup and hold times for the strapping pins before and after the CHIP_EN signal goes high.
Details about the parameters are listed in Table 5.

t0 t1

VIL_nRST
CHIP_EN

VIH

Strapping pin

Figure 7: Setup and Hold Times for the Strapping Pins

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2 Pin Definition

Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pins

Min
Parameter Description (ms)
t0 Setup time before CHIP_EN goes from low to high 0
t1 Hold time after CHIP_EN goes high 3

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3 Functional Description

3. Functional Description
This chapter describes the functions of ESP32-C3.

3.1 CPU and Memory

3.1.1 CPU
ESP32-C3 has a low-power 32-bit RISC-V single-core microprocessor with the following features:

• four-stage pipeline that supports a clock frequency of up to 160 MHz

• RV32IMC ISA

• 32-bit multiplier and 32-bit divider

• up to 32 vectored interrupts at seven priority levels

• up to 8 hardware breakpoints/watchpoints

• up to 16 PMP regions

• JTAG for debugging

For more information, please refer to Chapter ESP-RISC-V CPU in ESP32-C3 Technical Reference Manual.

3.1.2 Internal Memory

ESP32-C3’s internal memory includes:

• 384 KB of ROM: for booting and core functions.

• 400 KB of on­chip SRAM: for data and instructions, running at a configurable frequency of up to 160
MHz. Of the 400 KB SRAM, 16 KB is configured for cache.

• RTC FAST memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in
Deep-sleep mode.

• 4 Kbit of eFuse: 1792 bits are reserved for your data, such as encryption key and device ID.

• Embedded flash : See details in Chapter 1 ESP32-C3 Series Comparison.

For more information, please refer to Chapter System and Memory in ESP32-C3 Technical Reference
Manual.

3.1.3 External Flash

ESP32-C3 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external
flash.

CPU’s instruction memory space and read-only data memory space can map into external flash of ESP32-C3,
whose size can be 16 MB at most. ESP32-C3 supports hardware encryption/decryption based on XTS-AES to
protect developers’ programs and data in flash.

Through high-speed caches, ESP32-C3 can support at a time up to:

• 8 MB of instruction memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.

• 8 MB of data memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.

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3 Functional Description

Note:
After ESP32-C3 is initialized, software can customize the mapping of external flash into the CPU address space.

For more information, please refer to Chapter System and Memory in ESP32-C3 Technical Reference
Manual.

3.1.4 Address Mapping Structure

Figure 8: Address Mapping Structure

Note:
The memory space with gray background is not available for use.

3.1.5 Cache
ESP32-C3 has an eight-way set associative cache. This cache is read-only and has the following features:

• size: 16 KB

• block size: 32 bytes

• pre-load function

• lock function

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3 Functional Description

• critical word first and early restart

3.2 System Clocks

For more information, please refer to Chapter Reset and Clock in ESP32-C3 Technical Reference Manual.

3.2.1 CPU Clock

The CPU clock has three possible sources:

• external main crystal clock

• fast RC oscillator (typically about 17.5 MHz, and adjustable)

• PLL clock

The application can select the clock source from the three clocks above. The selected clock source drives the
CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock
source would be the external main crystal clock divided by 2.

Note:
ESP32-C3 is unable to operate without an external main crystal clock.

3.2.2 RTC Clock

The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible
sources:

• external low-speed (32 kHz) crystal clock

• internal slow RC oscillator (typically about 136 kHz, and adjustable)

• internal fast RC oscillator divided clock (derived from the fast RC oscillator divided by 256)

The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources:

• external main crystal clock divided by 2

• internal fast RC oscillator divide-by-N clock (typically about 17.5 MHz, and adjustable)

3.3 Analog Peripherals

For more information, please refer to Chapter On-Chip Sensors and Analog Signal Processing in ESP32-C3
Technical Reference Manual.

3.3.1 Analog­to­Digital Converter (ADC)

ESP32-C3 integrates two 12-bit SAR ADCs.

• ADC1 supports measurements on 5 channels, and is factory-calibrated.

• ADC2 supports measurements on 1 channel, and is not factory-calibrated.

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3 Functional Description

Note:
ADC2 of some chip revisions is not operable. For details, please refer to ESP32-C3 Series SoC Errata.

For ADC characteristics, please refer to Table 15.

For GPIOs assigned to ADC, please refer to Table 10.

3.3.2 Temperature Sensor

The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via
an ADC into a digital value.

The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature
changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O
load. Generally, the chip’s internal temperature is higher than the operating ambient temperature.

3.4 Digital Peripherals

3.4.1 General Purpose Input / Output Interface (GPIO)
ESP32-C3 has 22 or 16 GPIO pins which can be assigned various functions by configuring corresponding
registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC.

All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are
configured as an input, the input value can be read by software through the register. Input GPIOs can also be set
to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting
and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other
functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to holding state.

The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide
highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while
peripheral output signals can be configured to any IO pins. Table 6 shows the IO MUX functions of each
pin.

Table 6: IO MUX Pin Functions

Name No. Function 0 Function 1 Function 2 Reset Notes

XTAL_32K_P 4 GPIO0 GPIO0 — 0 R
XTAL_32K_N 5 GPIO1 GPIO1 — 0 R
GPIO2 6 GPIO2 GPIO2 FSPIQ 1 R
GPIO3 8 GPIO3 GPIO3 — 1 R
MTMS 9 MTMS GPIO4 FSPIHD 1 R
MTDI 10 MTDI GPIO5 FSPIWP 1 R
MTCK 12 MTCK GPIO6 FSPICLK 1* G
MTDO 13 MTDO GPIO7 FSPID 1 G
GPIO8 14 GPIO8 GPIO8 — 1 —
GPIO9 15 GPIO9 GPIO9 — 3 —
GPIO10 16 GPIO10 GPIO10 FSPICS0 1 G

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Name No. Function 0 Function 1 Function 2 Reset Notes

VDD_SPI 1
18 GPIO11 GPIO11 — 0 —
SPIHD 19 SPIHD GPIO12 — 3 —
SPIWP 20 SPIWP GPIO13 — 3 —
SPICS0 21 SPICS0 GPIO14 — 3 —
SPICLK 22 SPICLK GPIO15 — 3 —
SPID 23 SPID GPIO16 — 3 —
SPIQ 24 SPIQ GPIO17 — 3 —
GPIO18 25 GPIO18 GPIO18 — 0 USB, G
GPIO19 26 GPIO19 GPIO19 — 0* USB
U0RXD 27 U0RXD GPIO20 — 3 G
U0TXD 28 U0TXD GPIO21 — 4 —
1
For ESP32-C3FH4AZ, pins within the frame (namely pin 19 ∼ pin 24) are not bonded, and are labelled
as ”not connected”.

Reset

The default configuration of each pin after reset:

• 0 - input disabled, in high impedance state (IE = 0)

• 1 - input enabled, in high impedance state (IE = 1)

• 2 - input enabled, pull-down resistor enabled (IE = 1, WPD = 1)

• 3 - input enabled, pull-up resistor enabled (IE = 1, WPU = 1)

• 4 - output enabled, pull-up resistor enabled (OE = 1, WPU = 1)

• 0* - input disabled, pull-up resistor enabled (IE = 0, WPU = 0, USB_WPU = 1). See details in Notes

• 1* - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is

0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
1, input enabled, in high impedance state (IE = 1)

We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power
consumption. You may add pull-up and pull-down resistors in your PCB design referring to Table 14, or enable
internal pull-up and pull-down resistors during software initialization.

Notes

• R - These pins have analog functions.

• USB - GPIO18 and GPIO19 are USB pins. The pull-up value of a USB pin is controlled by the pin’s pull-up
value together with USB pull-up value. If any of the two pull-up values is 1, the pin’s pull-up resistor will be
enabled. The pull-up resistors of USB pins are controlled by USB_SERIAL_JTAG_DP_PULLUP bit.

• G - These pins have glitches during power-up. See details in Table 7.

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Table 7: Power­Up Glitches on Pins

Typical Time Period

Pin Glitch1 (ns)
MTCK Low-level glitch 5
MTDO Low-level glitch 5
GPIO10 Low-level glitch 5
U0RXD Low-level glitch 5
GPIO18 High-level glitch 50000
1
Low-level glitch: the pin is at a low level output status during the
time period;
High-level glitch: the pin is at a high level output status during the
time period;
Pull-down glitch: the pin is at an internal weak pulled-down status
during the time period;
Pull-up glitch: the pin is at an internal weak pulled-up status during
the time period.
Please refer to Table 14 for detailed parameters about low/high-
level and pull-down/up.

For more information, please refer to Chapter IO MUX and GPIO Matrix (GPIO, IO_MUX) in ESP32-C3 Technical
Reference Manual.

3.4.2 Serial Peripheral Interface (SPI)

ESP32-C3 features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can be configured to operate in
SPI memory mode, while SPI2 can be configured to operate in general-purpose SPI modes.

• SPI Memory mode

In SPI memory mode, SPI0 and SPI1 interface with SPI memory. Data are transferred in unit of byte. Up to
four-line STR reads and writes are supported. The clock frequency is configurable to a maximum of 120
MHz in STR mode.

• SPI2 General­purpose SPI (GP­SPI) mode

When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports
two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master
and slave modes. The host’s clock frequency is configurable. Data are transferred in unit of byte. The clock
polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA.

– In master mode, the clock frequency is 80 MHz at most, and the four modes of SPI transfer format are
supported.

– In slave mode, the clock frequency is 60 MHz at most, and the four modes of SPI transfer format are
also supported.

The mapping between SPI bus signals and GPIO pins is shown in Table 8:

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Table 8: Mapping of SPI Signals and Chip Pins

Full­Duplex Half­Duplex Chip Pin Signal

SPI Signal SPI Signal Pin Function FSPI Signals
MOSI MOSI D FSPID
MISO (MISO) Q FSPIQ
CS CS CS FSPICS0 ~ 5
CLK CLK CLK FSPICLK
— — WP FSPIWP
— — HD FSPIHD

In most cases, the data port connection between ESP32-C3 and external flash is as follows:

Table 9: Connection Between ESP32­C3 and External Flash

External Flash Data Port

Chip Pin SPI Single­Line Mode SPI Two­Line Mode SPI Four­Line Mode
SPID (SPID) DI IO0 IO0
SPIQ (SPIQ) DO IO1 IO1
SPIWP (SPIWP) WP# — IO2
SPIHD (SPIHD) HOLD# — IO3

For GPIOs assigned to SPI, please refer to Table 10.

For more information, please refer to Chapter SPI Controller (SPI) in ESP32-C3 Technical Reference
Manual.

3.4.3 Universal Asynchronous Receiver Transmitter (UART)

ESP32-C3 has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous
communication (RS232 and RS485) at a speed of up to 5 Mbps. The UART controller provides hardware flow
control (CTS and RTS signals) and software flow control (XON and XOFF). Both UART interfaces connect to
GDMA via UHCI0, and can be accessed by the GDMA controller or directly by the CPU.

For GPIOs assigned to UART, please refer to Table 10.

For more information, please refer to Chapter UART Controller (UART) in ESP32-C3 Technical Reference
Manual.

3.4.4 I2C Interface

ESP32-C3 has an I2C bus interface which is used for I2C master mode or slave mode, depending on your
configuration. The I2C interface supports:

• standard mode (100 Kbit/s)

• fast mode (400 Kbit/s)

• up to 800 Kbit/s (constrained by SCL and SDA pull-up strength)

• 7-bit and 10-bit addressing mode

• double addressing mode

• 7-bit broadcast address

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You can configure instruction registers to control the I2C interface for more flexibility.

For GPIOs assigned to I2C, please refer to Table 10.

For more information, please refer to Chapter I2C Controller (I2C) in ESP32-C3 Technical Reference
Manual.

3.4.5 I2S Interface

ESP32-C3 includes a standard I2S interface. This interface can operate as a master or a slave in full-duplex
mode or half-duplex mode, and can be configured for 8-bit, 16-bit, 24-bit, or 32-bit serial communication. BCK
clock frequency, from 10 kHz up to 40 MHz, is supported.

The I2S interface connects to the GDMA controller. The interface supports TDM PCM, TDM MSB alignment,
TDM standard, and PDM standard.

For GPIOs assigned to I2S, please refer to Table 10.

For more information, please refer to Chapter I2S Controller (I2S) in ESP32-C3 Technical Reference Manual.

3.4.6 Remote Control Peripheral

The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two channels
of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and
other single wire protocols. All four channels share a 192 × 32-bit memory block to store transmit or receive
waveform.

For GPIOs assigned to the Remote Control Peripheral, please refer to Table 10.

For more information, please refer to Chapter Remote Control Peripheral (RMT) in ESP32-C3 Technical Reference
Manual.

3.4.7 LED PWM Controller

The LED PWM controller can generate independent digital waveform on six channels. The LED PWM
controller:

• can generate digital waveform with configurable periods and duty cycle. The accuracy of duty cycle can be
up to 18 bits.

• has multiple clock sources, including APB clock and external main crystal clock.

• can operate when the CPU is in Light-sleep mode.

• supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient
generator.

For GPIOs assigned to LED PWM, please refer to Table 10.

For more information, please refer to Chapter LED PWM Controller (LEDC) in ESP32-C3 Technical Reference
Manual.

3.4.8 General DMA Controller

ESP32-C3 has a general DMA controller (GDMA) with six independent channels, i.e. three transmit channels and
three receive channels. These six channels are shared by peripherals with DMA feature. The GDMA controller
implements a fixed-priority scheme among these channels, whose priority can be configured.

The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and
memory-to-memory data transfer at a high speed. All channels can access internal RAM.

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Peripherals on ESP32-C3 with DMA feature are SPI2, UHCI0, I2S, AES, SHA, and ADC.

For more information, please refer to Chapter GDMA Controller (GDMA) in ESP32-C3 Technical Reference
Manual.

3.4.9 USB Serial/JTAG Controller

ESP32-C3 integrates a USB Serial/JTAG controller. This controller has the following features:

• CDC-ACM virtual serial port and JTAG adapter functionality

• USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does not
support the faster 480 Mbit/s high-speed transfer mode)

• programming embedded/external flash

• CPU debugging with compact JTAG instructions

• a full-speed USB PHY integrated in the chip

For GPIOs assigned to USB Serial/JTAG, please refer to Table 10.

For more information, please refer to Chapter USB Serial/JTAG Controller (USB_SERIAL_JTAG) in ESP32-C3
Technical Reference Manual.

3.4.10 TWAI® Controller

ESP32-C3 has a TWAI® controller with the following features:

• compatible with ISO 11898-1 protocol (CAN Specification 2.0)

• standard frame format (11-bit ID) and extended frame format (29-bit ID)

• bit rates from 1 Kbit/s to 1 Mbit/s

• multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)

• 64-byte receive FIFO

• acceptance filter (single and dual filter modes)

• error detection and handling: error counters, configurable error interrupt threshold, error code capture,
arbitration lost capture

For GPIOs assigned to TWAI, please refer to Table 10.

For more information, please refer to Chapter Two-wire Automotive Interface (TWAI) in ESP32-C3 Technical
Reference Manual.

3.5 Radio and Wi­Fi

ESP32-C3 radio consists of the following blocks:

• 2.4 GHz receiver

• 2.4 GHz transmitter

• bias and regulators

• balun and transmit-receive switch

• clock generator

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3.5.1 2.4 GHz Receiver

The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to
the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions,
ESP32-C3 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and baseband
filters.

3.5.2 2.4 GHz Transmitter

The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the
antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of
the power amplifier.

Additional calibrations are integrated to cancel any radio imperfections, such as:

• carrier leakage

• I/Q amplitude/phase matching

• baseband nonlinearities

• RF nonlinearities

• antenna matching

These built-in calibration routines reduce the cost, time, and specialized equipment required for product
testing.

3.5.3 Clock Generator

The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All
components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators
and dividers.

The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are
optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the
transmitter.

3.5.4 Wi­Fi Radio and Baseband

ESP32-C3 Wi-Fi radio and baseband support the following features:

• 802.11b/g/n

• 802.11n MCS0-7 that supports 20 MHz and 40 MHz bandwidth

• 802.11n MCS32

• 802.11n 0.4 µs guard interval

• data rate up to 150 Mbps

• RX STBC (single spatial stream)

• adjustable transmitting power

3.5.5 Wi­Fi MAC

ESP32-C3 implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS) STA
and SoftAP operations under the Distributed Control Function (DCF). Power management is handled
automatically with minimal host interaction to minimize the active duty period.

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ESP32-C3 Wi-Fi MAC applies the following low-level protocol functions automatically:

• 4 × virtual Wi-Fi interfaces

• infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode

• RTS protection, CTS protection, Immediate Block ACK

• fragmentation and defragmentation

• TX/RX A-MPDU, TX/RX A-MSDU

• transmit opportunity (TXOP)

• Wi-Fi multimedia (WMM)

• GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise

• automatic beacon monitoring (hardware TSF)

• 802.11mc FTM

3.5.6 Networking Features

Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocols
over Wi-Fi. TLS 1.0, 1.1 and 1.2 is also supported.

3.6 Bluetooth LE
ESP32-C3 includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an
RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and
Bluetooth mesh.

3.6.1 Bluetooth LE Radio and PHY

Bluetooth Low Energy radio and PHY in ESP32-C3 support:

• 1 Mbps PHY

• 2 Mbps PHY for higher data rates

• coded PHY for longer range (125 Kbps and 500 Kbps)

• HW Listen before talk (LBT)

3.6.2 Bluetooth LE Link Layer Controller

Bluetooth Low Energy Link Layer Controller in ESP32-C3 supports:

• LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data

• multiple advertisement sets

• simultaneous advertising and scanning

• multiple connections in simultaneous central and peripheral roles

• adaptive frequency hopping and channel assessment

• LE channel selection algorithm #2

• connection parameter update

• high duty cycle non-connectable advertising

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• LE privacy 1.2

• LE data packet length extension

• link layer extended scanner filter policies

• low duty cycle directed advertising

• link layer encryption

• LE Ping

3.7 Low Power Management

With the use of advanced power-management technologies, ESP32-C3 can switch between different power
modes.

• Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.

• Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wi-Fi base band,
Bluetooth LE base band, and radio are disabled, but Wi-Fi and Bluetooth LE connection can remain active.

• Light-sleep mode: The CPU is paused. Any wake-up events (MAC, host, RTC timer, or external interrupts)
will wake up the chip. Wi-Fi and Bluetooth LE connection can remain active.

• Deep-sleep mode: CPU and most peripherals are powered down. Only the RTC memory is powered on.
Wi-Fi connection data are stored in the RTC memory. The RTC timer or the RTC GPIOs can wake up the
chip from the Deep-sleep mode.

For power consumption in different power modes, please refer to Section 4.6.

3.8 Timers
3.8.1 General Purpose Timers
ESP32-C3 is embedded with two 54-bit general-purpose timers, which are based on 16-bit prescalers and
54-bit auto-reload-capable up/down-timers.

The timers’ features are summarized as follows:

• a 16-bit clock prescaler, from 1 to 65536

• a 54-bit time-base counter programmable to be incrementing or decrementing

• able to read real-time value of the time-base counter

• halting and resuming the time-base counter

• programmable alarm generation

• level interrupt generation

For more information, please refer to Chapter Timer Group (TIMG) in ESP32-C3 Technical Reference
Manual.

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3 Functional Description

3.8.2 System Timer

ESP32-C3 integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The system
timer has the following features:

• counters with a fixed clock frequency of 16 MHz

• three types of independent interrupts generated according to alarm value

• two alarm modes: target mode and period mode

• 52-bit target alarm value and 26-bit periodic alarm value

• automatic reload of counter value

• counters can be stalled if the CPU is stalled or in OCD mode

For more information, please refer to Chapter System Timer (SYSTIMER) in ESP32-C3 Technical Reference
Manual.

3.8.3 Watchdog Timers

For more information, please refer to Chapter Watchdog Timers (WDT) in ESP32-C3 Technical Reference
Manual.

Digital Watchdog Timers

ESP32-C3 contains three digital watchdog timers: one in each of the two timer groups (called Main System
Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT).

During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order
to detect and recover from booting errors.

Digital watchdog timers have the following features:

• four stages, each with a programmable timeout value. Each stage can be configured, enabled and
disabled separately

• interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or
system reset for RWDT upon expiry of each stage

• 32-bit expiry counter

• write protection, to prevent RWDT and MWDT configuration from being altered inadvertently

• flash boot protection

If the boot process from an SPI flash does not complete within a predetermined period of time, the
watchdog will reboot the entire main system.

Analog Watchdog Timer

ESP32-C3 also has one analog watchdog timer: RTC super watchdog timer (SWD). It is an ultra-low-power
circuit in analog domain that helps to prevent the system from operating in a sub-optimal state and resets the
system if required.

SWD has the following features:

• Ultra-low power

• Interrupt to indicate that the SWD timeout period is close to expiring

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3 Functional Description

• Various dedicated methods for software to feed SWD, which enables SWD to monitor the working state of
the whole operating system

3.9 Cryptographic Hardware Accelerators

ESP32-C3 is equipped with hardware accelerators of general algorithms, such as AES-128/AES-256 (FIPS PUB
197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB 180-4), and RSA3072.
The chip also supports independent arithmetic, such as Big Integer Multiplication and Big Integer Modular
Multiplication. The maximum operation length for RSA and Big Integer Modular Multiplication is 3072 bits. The
maximum factor length for Big Integer Multiplication is 1536 bits.

3.10 Physical Security Features

• Transparent external flash encryption (AES-XTS algorithm) with software inaccessible key prevents
unauthorized readout of your application code or data.

• Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature)
can be booted.

• HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity
verification and other purposes.

• Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity
verification.

• World Controller provides two running environments for software. All hardware and software resources are
sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed
by hardware in the general world, thus establishing a security boundary.

3.11 Peripheral Pin Configurations

Table 10: Peripheral Pin Configurations

Interface Signal Pin Function

ADC ADC1_CH0 XTAL_32K_P Two 12-bit SAR ADCs
ADC1_CH1 XTAL_32K_N
ADC1_CH2 GPIO2
ADC1_CH3 GPIO3
ADC1_CH4 MTMS
ADC2_CH0 MTDI
JTAG MTDI MTDI JTAG for software debugging
MTCK MTCK
MTMS MTMS
MTDO MTDO

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Interface Signal Pin Function

UART U0RXD_in Any GPIO pins Two UART channels with hardware flow control
U0CTS_in and GDMA
U0DSR_in
U0TXD_out
U0RTS_out
U0DTR_out
U1RXD_in
U1CTS_in
U1DSR_in
U1TXD_out
U1RTS_out
U1DTR_out
I2C I2CEXT0_SCL_in Any GPIO pins One I2C channel in slave or master mode
I2CEXT0_SDA_in
I2CEXT1_SCL_in
I2CEXT1_SDA_in
I2CEXT0_SCL_out
I2CEXT0_SDA_out
I2CEXT1_SCL_out
I2CEXT1_SDA_out
LED PWM ledc_ls_sig_out0~5 Any GPIO pins Six independent PWM channels
I2S I2S0O_BCK_in Any GPIO pins Stereo input and output from/to the audiocodec
I2S_MCLK_in
I2SO_WS_in
I2SI_SD_in
I2SI_BCK_in
I2SI_WS_in
I2SO_BCK_out
I2S_MCLK_out
I2SO_WS_out
I2SO_SD_out
I2SI_BCK_out
I2SI_WS_out
I2SO_SD1_out
Remote Control RMT_SIG_IN0~1 Any GPIO pins Two channels for an IR transceiver of various
Peripheral RMT_SIG_OUT0~1 waveforms
SPI0/1 SPICLK_out_mux SPICLK Support Standard SPI, Dual SPI, Quad SPI, and
SPICS0_out SPICS0 QPI that allow connection to external flash
SPICS1_out Any GPIO pins
SPID_in/_out SPID
SPIQ_in/_out SPIQ
SPIWP_in/_out SPIWP
SPIHD_in/_out SPIHD

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Interface Signal Pin Function

SPI2 FSPICLK_in/_out_mux Any GPIO pins • Master mode and slave mode of SPI, Dual
FSPICS0_in/_out SPI, Quad SPI, and QPI
FSPICS1~5_out • Connection to external flash, RAM, and
FSPID_in/_out other SPI devices
FSPIQ_in/_out • Four modes of SPI transfer format
FSPIWP_in/_out • Configurable SPI frequency
FSPIHD_in/_out • 64-byte FIFO or GDMA buffer
USB Serial/JTAG USB_D+ GPIO19 USB-to-serial converter, and USB-to-JTAG
USB_D- GPIO18 converter
TWAI twai_rx Any GPIO pins Compatible with ISO 11898-1 protocol
twai_tx
twai_bus_off_on
twai_clkout

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4 Electrical Characteristics

4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the
device. These are stress ratings only, and do not refer to the functional operation of the device.

Table 11: Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VDDA, VDD3P3, VDD3P3_RTC, Voltage applied to power supply pins
–0.3 3.6 V
VDD3P3_CPU, VDD_SPI per power domain
TST ORE Storage temperature –40 150 °C

4.2 Recommended Operating Conditions

Table 12: Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

VDDA, VDD3P3 Voltage applied to power supply pins per
3.0 3.3 3.6 V
VDD3P3_RTC power domain
VDD_SPI (working as
— 3.0 3.3 3.6 V
input power supply)1
VDD3P3_CPU2, 3 Voltage applied to power supply pin 3.0 3.3 3.6 V
4
IV DD Current delivered by external power supply 0.5 — — A
ESP32-C3 105
Operating ambient
TA ESP32-C3FN4 –40 — 85 °C
temperature
ESP32-C3FH4 105
1
For more information, please refer to Section 2.3 Power Scheme.
2
When VDD_SPI is used to drive peripherals, VDD3P3_CPU should comply with the peripherals’ speci-
fications. For more information, please refer to Table 13.
3
To write eFuse, VDD3P3_CPU should not be higher than 3.3 V.
4
If you use a single power supply, the recommended output current is 500 mA or more.

4.3 VDD_SPI Output Characteristics

Table 13: VDD_SPI Output Characteristics

Symbol Parameter Typ Unit

RSP I On-resistance in 3.3 V mode 7.5 Ω

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Note:
In real-life applications, when VDD_SPI works in 3.3 V output mode, VDD3P3_CPU may be affected by RSP I . For
example, when VDD3P3_CPU is used to drive a 3.3 V flash, it should comply with the following specifications:

VDD3P3_CPU > VDD_flash_min + I_flash_max*RSP I

Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the maximum current.

For more information, please refer to section 2.3 Power Scheme.

4.4 DC Characteristics (3.3 V, 25 °C)

Table 14: DC Characteristics (3.3 V, 25 °C)

Symbol Parameter Min Typ Max Unit

CIN Pin capacitance — 2 — pF
1 1
VIH High-level input voltage 0.75 × VDD — VDD + 0.3 V
1
VIL Low-level input voltage –0.3 — 0.25 × VDD V
IIH High-level input current — — 50 nA
IIL Low-level input current — — 50 nA
2 1
VOH High-level output voltage 0.8 × VDD — — V
2 1
VOL Low-level output voltage — — 0.1 × VDD V
1
High-level source current (VDD = 3.3 V,
IOH — 40 — mA
VOH >= 2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD1= 3.3 V, VOL =
IOL — 28 — mA
0.495 V, PAD_DRIVER = 3)
RP U Pull-up resistor — 45 — kΩ
RP D Pull-down resistor — 45 — kΩ
1 1
VIH_nRST Chip reset release voltage 0.75 × VDD — VDD + 0.3 V
1
VIL_nRST Chip reset voltage –0.3 — 0.25 × VDD V
1
VDD is the I/O voltage for a particular power domain of pins.
2
VOH and VOL are measured using high-impedance load.

4.5 ADC Characteristics

Table 15: ADC Characteristics

Symbol Parameter Min Max Unit

ADC connected to an external
DNL (Differential nonlinearity)1 –7 7 LSB
100 nF capacitor; DC signal input;
ambient temperature at 25 °C;
INL (Integral nonlinearity) –12 12 LSB
Wi-Fi off
Sampling rate — — 100 kSPS 2
1
To get better DNL results, you can sample multiple times and apply a filter, or calculate the average value.
2
kSPS means kilo samples-per-second.

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The calibrated ADC results after hardware calibration + software calibration are shown in Table 16. For higher
accuracy, you may implement your own calibration methods.

Table 16: ADC Calibration Results

Parameter Description Min Max Unit

ATTEN0, effective measurement range of 0 ~ 750 –10 10 mV
ATTEN1, effective measurement range of 0 ~ 1050 –10 10 mV
Total error
ATTEN2, effective measurement range of 0 ~ 1300 –10 10 mV
ATTEN3, effective measurement range of 0 ~ 2500 –35 35 mV

4.6 Current Consumption

The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF
port. All transmitters’ measurements are based on a 100% duty cycle.

4.6.1 RF Current Consumption in Active Mode

Table 17: Current Consumption Depending on RF Modes

Work mode Description Peak (mA)

802.11b, 1 Mbps, @21 dBm 335
802.11g, 54 Mbps, @19 dBm 285
TX
802.11n, HT20, MCS7, @18.5 dBm 276
Active (RF working)
802.11n, HT40, MCS7, @18.5 dBm 278
802.11b/g/n, HT20 84
RX
802.11n, HT40 87

4.6.2 Current Consumption in Other Modes

Table 18: Current Consumption in Modem­sleep Mode

Typ
CPU Frequency
Mode Description All Peripherals Clocks All Peripherals Clocks
(MHz)
Disabled (mA) Enabled (mA)1
CPU is running 23 28
160
CPU is idle 16 21
Modem-sleep2,3
CPU is running 17 22
80
CPU is idle 13 18
1
In practice, the current consumption might be different depending on which peripherals are enabled.
2
In Modem-sleep mode, Wi-Fi is clock gated.
3
In Modem-sleep mode, the consumption might be higher when accessing flash. For a flash rated at 80
Mbit/s, in SPI 2-line mode the consumption is 10 mA.

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Table 19: Current Consumption in Low­Power Modes

Mode Description Typ (µA)

Light-sleep VDD_SPI and Wi-Fi are powered down, and all GPIOs are high-impedance 130
Deep-sleep RTC timer + RTC memory 5
Power off CHIP_EN is set to low level, the chip is powered off 1

4.7 Reliability
Table 20: Reliability Qualifications

Test Item Test Conditions Test Standard

HTOL (High Temperature
125 °C, 1000 hours JESD22-A108
Operating Life)
ESD (Electro-Static HBM (Human Body Mode)1± 2000 V JS-001
2
Discharge Sensitivity) CDM (Charge Device Mode) ± 1000 V JS-002
Current trigger ± 200 mA
Latch up JESD78
Voltage trigger 1.5 × VDDmax
Bake 24 hours @125 °C
J-STD-020, JESD47,
Preconditioning Moisture soak (level 3: 192 hours @30 °C, 60% RH)
JESD22-A113
IR reflow solder: 260 + 0 °C, 20 seconds, three times
TCT (Temperature Cycling
–65 °C / 150 °C, 500 cycles JESD22-A104
Test)
uHAST (Highly
Accelerated Stress Test, 130 °C, 85% RH, 96 hours JESD22-A118
unbiased)
HTSL (High Temperature
150 °C, 1000 hours JESD22-A103
Storage Life)
LTSL (Low Temperature
–40 °C, 1000 hours JESD22-A119
Storage Life)
1
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
2
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

4.8 Wi­Fi Radio

Table 21: Wi­Fi Frequency

Min Typ Max

Parameter (MHz) (MHz) (MHz)
Center frequency of operating channel 2412 — 2484

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4.8.1 Wi­Fi RF Transmitter (TX) Specifications

Table 22: TX Power with Spectral Mask and EVM Meeting 802.11 Standards

Min Typ Max

Rate (dBm) (dBm) (dBm)
802.11b, 1 Mbps — 21.0 —
802.11b, 11 Mbps — 21.0 —
802.11g, 6 Mbps — 21.0 —
802.11g, 54 Mbps — 19.0 —
802.11n, HT20, MCS0 — 20.0 —
802.11n, HT20, MCS7 — 18.5 —
802.11n, HT40, MCS0 — 20.0 —
802.11n, HT40, MCS7 — 18.5 —

Table 23: TX EVM Test

Min Typ SL1

Rate (dB) (dB) (dB)
802.11b, 1 Mbps, @21 dBm — –24.5 –10
802.11b, 11 Mbps, @21 dBm — –25.0 –10
802.11g, 6 Mbps, @21 dBm — –23.0 –5
802.11g, 54 Mbps, @19 dBm — –27.5 –25
802.11n, HT20, MCS0, @20 dBm — –22.5 –5
802.11n, HT20, MCS7, @18.5 dBm — –29.0 –27
802.11n, HT40, MCS0, @20 dBm — –22.5 –5
802.11n, HT40, MCS7, @18.5 dBm — –28.0 –27
1
SL stands for standard limit value.

4.8.2 Wi­Fi RF Receiver (RX) Specifications

Table 24: RX Sensitivity

Min Typ Max

Rate (dBm) (dBm) (dBm)
802.11b, 1 Mbps — –98.4 —
802.11b, 2 Mbps — –96.0 —
802.11b, 5.5 Mbps — –93.0 —
802.11b, 11 Mbps — –88.6 —
802.11g, 6 Mbps — –93.8 —
802.11g, 9 Mbps — –92.2 —
802.11g, 12 Mbps — –91.0 —
802.11g, 18 Mbps — –88.4 —
802.11g, 24 Mbps — –85.8 —
802.11g, 36 Mbps — –82.0 —
Cont’d on next page

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Table 24 – cont’d from previous page

Min Typ Max
Rate (dBm) (dBm) (dBm)
802.11g, 48 Mbps — –78.0 —
802.11g, 54 Mbps — –76.6 —
802.11n, HT20, MCS0 — –93.6 —
802.11n, HT20, MCS1 — –90.8 —
802.11n, HT20, MCS2 — –88.4 —
802.11n, HT20, MCS3 — –85.0 —
802.11n, HT20, MCS4 — –81.8 —
802.11n, HT20, MCS5 — –77.8 —
802.11n, HT20, MCS6 — –76.0 —
802.11n, HT20, MCS7 — –74.8 —
802.11n, HT40, MCS0 — –90.0 —
802.11n, HT40, MCS1 — –88.0 —
802.11n, HT40, MCS2 — –85.2 —
802.11n, HT40, MCS3 — –82.0 —
802.11n, HT40, MCS4 — –78.8 —
802.11n, HT40, MCS5 — –74.6 —
802.11n, HT40, MCS6 — –73.0 —
802.11n, HT40, MCS7 — –71.4 —

Table 25: Maximum RX Level

Min Typ Max

Rate (dBm) (dBm) (dBm)
802.11b, 1 Mbps — 5 —
802.11b, 11 Mbps — 5 —
802.11g, 6 Mbps — 5 —
802.11g, 54 Mbps — 0 —
802.11n, HT20, MCS0 — 5 —
802.11n, HT20, MCS7 — 0 —
802.11n, HT40, MCS0 — 5 —
802.11n, HT40, MCS7 — 0 —

Table 26: RX Adjacent Channel Rejection

Min Typ Max

Rate (dB) (dB) (dB)
802.11b, 1 Mbps — 35 —
802.11b, 11 Mbps — 35 —
802.11g, 6 Mbps — 31 —
802.11g, 54 Mbps — 20 —
802.11n, HT20, MCS0 — 31 —
Cont’d on next page

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Table 26 – cont’d from previous page

Min Typ Max
Rate (dB) (dB) (dB)
802.11n, HT20, MCS7 — 16 —
802.11n, HT40, MCS0 — 25 —
802.11n, HT40, MCS7 — 11 —

4.9 Bluetooth LE Radio

Table 27: Bluetooth LE Frequency

Min Typ Max

Parameter
(MHz) (MHz) (MHz)
Center frequency of operating channel 2402 — 2480

4.9.1 Bluetooth LE RF Transmitter (TX) Specifications

Table 28: Transmitter Characteristics ­ Bluetooth LE 1 Mbps

Parameter Description Min Typ Max Unit

RF power control range –24.00 0 21.00 dBm
RF transmit power
Gain control step — 3.00 — dB
Max |fn |n=0, 1, 2, ..k — 17.00 — kHz
Max |f0 − fn | — 1.75 — kHz
Carrier frequency offset and drift
Max |fn − fn−5 | — 1.46 — kHz
|f1 − f0 | — 0.80 — kHz
∆ f 1avg — 250.00 — kHz
Min ∆ f 2max (for at least
Modulation characteristics — 190.00 — kHz
99.9% of all ∆ f 2max )
∆ f 2avg /∆ f 1avg — 0.83 — —
± 2 MHz offset — –37.62 — dBm
In-band spurious emissions ± 3 MHz offset — –41.95 — dBm
> ± 3 MHz offset — –44.48 — dBm

Table 29: Transmitter Characteristics ­ Bluetooth LE 2 Mbps

Parameter Description Min Typ Max Unit

RF power control range –24.00 0 21.00 dBm
RF transmit power
Gain control step — 3.00 — dB
Max |fn |n=0, 1, 2, ..k — 20.80 — kHz
Max |f0 − fn | — 1.30 — kHz
Carrier frequency offset and drift
Max |fn − fn−5 | — 1.33 — kHz
|f1 − f0 | — 0.70 — kHz
∆ f 1avg — 498.00 — kHz
Cont’d on next page
Modulation characteristics

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Table 29 – cont’d from previous page

Parameter Description Min Typ Max Unit
Min ∆ f 2max (for at least
— 430.00 — kHz
99.9% of all ∆ f 2max )
∆ f 2avg /∆ f 1avg — 0.93 — —
± 4 MHz offset — –43.55 — dBm
In-band spurious emissions ± 5 MHz offset — –45.26 — dBm
> ± 5 MHz offset — –45.26 — dBm

Table 30: Transmitter Characteristics ­ Bluetooth LE 125 Kbps

Parameter Description Min Typ Max Unit

RF power control range –24.00 0 21.00 dBm
RF transmit power
Gain control step — 3.00 — dB
Max |fn |n=0, 1, 2, ..k — 17.50 — kHz
Max |f0 − fn | — 0.45 — kHz
Carrier frequency offset and drift
|fn − fn−3 | — 0.70 — kHz
|f0 − f3 | — 0.30 — kHz
∆ f 1avg — 250.00 — kHz
Modulation characteristics Min ∆ f 1max (for at least
— 235.00 — kHz
99.9% of all∆ f 2max )
± 2 MHz offset — –37.90 — dBm
In-band spurious emissions ± 3 MHz offset — –41.00 — dBm
> ± 3 MHz offset — –42.50 — dBm

Table 31: Transmitter Characteristics ­ Bluetooth LE 500 Kbps

Parameter Description Min Typ Max Unit

RF power control range –24.00 0 21.00 dBm
RF transmit power
Gain control step — 3.00 — dB
Max |fn |n=0, 1, 2, ..k — 17.00 — kHz
Max |f0 − fn | — 0.88 — kHz
Carrier frequency offset and drift
|fn − fn−3 | — 1.00 — kHz
|f0 − f3 | — 0.20 — kHz
∆ f 2avg — 208.00 — kHz
Modulation characteristics Min ∆ f 2max (for at least
— 190.00 — kHz
99.9% of all ∆ f 2max )
± 2 MHz offset — –37.90 — dBm
In-band spurious emissions ± 3 MHz offset — –41.30 — dBm
> ± 3 MHz offset — –42.80 — dBm

4.9.2 Bluetooth LE RF Receiver (RX) Specifications

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Table 32: Receiver Characteristics ­ Bluetooth LE 1 Mbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –97 — dBm
Maximum received signal @30.8% PER — — 5 — dBm
Co-channel C/I — — 8 — dB
F = F0 + 1 MHz — –3 — dB
F = F0 – 1 MHz — –4 — dB
F = F0 + 2 MHz — –29 — dB
F = F0 – 2 MHz — –31 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –33 — dB
F = F0 – 3 MHz — –27 — dB
F ≥ F0 + 4 MHz — –29 — dB
F ≤ F0 – 4 MHz — –38 — dB
Image frequency — — –29 — dB
F = Fimage + 1 MHz — –41 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –33 — dB
30 MHz ~ 2000 MHz — –5 — dBm
2003 MHz ~ 2399 MHz — –18 — dBm
Out-of-band blocking performance
2484 MHz ~ 2997 MHz — –15 — dBm
3000 MHz ~ 12.75 GHz — –5 — dBm
Intermodulation — — –30 — dBm

Table 33: Receiver Characteristics ­ Bluetooth LE 2 Mbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –93 — dBm
Maximum received signal @30.8% PER — — 3 — dBm
Co-channel C/I — — 10 — dB
F = F0 + 2 MHz — –7 — dB
F = F0 – 2 MHz — –7 — dB
F = F0 + 4 MHz — –28 — dB
F = F0 – 4 MHz — –26 — dB
Adjacent channel selectivity C/I
F = F0 + 6 MHz — –26 — dB
F = F0 – 6 MHz — –27 — dB
F ≥ F0 + 8 MHz — –29 — dB
F ≤ F0 – 8 MHz — –28 — dB
Image frequency — — –28 — dB
F = Fimage + 2 MHz — –26 — dB
Adjacent channel to image frequency
F = Fimage – 2 MHz — –7 — dB
30 MHz ~ 2000 MHz — –5 — dBm
2003 MHz ~ 2399 MHz — –19 — dBm
Out-of-band blocking performance
2484 MHz ~ 2997 MHz — –16 — dBm
3000 MHz ~ 12.75 GHz — –5 — dBm
Intermodulation — — –29 — dBm

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Table 34: Receiver Characteristics ­ Bluetooth LE 125 Kbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –105 — dBm
Maximum received signal @30.8% PER — — 5 — dBm
Co-channel C/I — — 3 — dB
F = F0 + 1 MHz — –6 — dB
F = F0 – 1 MHz — –6 — dB
F = F0 + 2 MHz — –33 — dB
F = F0 – 2 MHz — –43 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –37 — dB
F = F0 – 3 MHz — –47 — dB
F ≥ F0 + 4 MHz — –40 — dB
F ≤ F0 – 4 MHz — –50 — dB
Image frequency — — –40 — dB
F = Fimage + 1 MHz — –50 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –37 — dB

Table 35: Receiver Characteristics ­ Bluetooth LE 500 Kbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –100 — dBm
Maximum received signal @30.8% PER — — 5 — dBm
Co-channel C/I — — 3 — dB
F = F0 + 1 MHz — –2 — dB
F = F0 – 1 MHz — –3 — dB
F = F0 + 2 MHz — –32 — dB
F = F0 – 2 MHz — –33 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –23 — dB
F = F0 – 3 MHz — –40 — dB
F ≥ F0 + 4 MHz — –34 — dB
F ≤ F0 – 4 MHz — –44 — dB
Image frequency — — –34 — dB
F = Fimage + 1 MHz — –46 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –23 — dB

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5 Package Information

5. Package Information

Figure 9: QFN32 (5×5 mm) Package

Note:

• The source file of recommended PCB land pattern is provided for your reference. You can view it with Autodesk
Viewer;

• For reference PCB layout, please refer to ESP32-C3 Hardware Design Guidelines;

• For information about tape, reel, and product marking, please refer to Espressif Chip Packaging Information.

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6 Related Documentation and Resources

6. Related Documentation and Resources

Related Documentation
• ESP32-C3 Technical Reference Manual – Detailed information on how to use the ESP32-C3 memory and peripherals.
• ESP32-C3 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-C3 into your hardware product.
• ESP32-C3 Series SoC Errata – Descriptions of known errors in ESP32-C3 series of SoCs.
• Certificates
https://espressif.com/en/support/documents/certificates
• ESP32-C3 Product/Process Change Notifications (PCN)
https://espressif.com/en/support/documents/pcns?keys=ESP32-C3
• ESP32-C3 Advisories – Information on security, bugs, compatibility, component reliability.
https://espressif.com/en/support/documents/advisories?keys=ESP32-C3
• Documentation Updates and Update Notification Subscription
https://espressif.com/en/support/download/documents

Developer Zone
• ESP-IDF Programming Guide for ESP32-C3 – Extensive documentation for the ESP-IDF development framework.
• ESP-IDF and other development frameworks on GitHub.
https://github.com/espressif
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
https://esp32.com/
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
https://blog.espressif.com/
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
https://espressif.com/en/support/download/sdks-demos

Products
• ESP32-C3 Series SoCs – Browse through all ESP32-C3 SoCs.
https://espressif.com/en/products/socs?id=ESP32-C3
• ESP32-C3 Series Modules – Browse through all ESP32-C3-based modules.
https://espressif.com/en/products/modules?id=ESP32-C3
• ESP32-C3 Series DevKits – Browse through all ESP32-C3-based devkits.
https://espressif.com/en/products/devkits?id=ESP32-C3
• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
https://products.espressif.com/#/product-selector?language=en

Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
(Online stores), Become Our Supplier, Comments & Suggestions.
https://espressif.com/en/contact-us/sales-questions

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Revision History

Revision History
Date Version Release Notes

• Deleted feature ”Antenna diversity”

• Deleted feature ”Supports external power amplifier”
2022-12-15 v1.4
• Updated the glitch type of GPIO18 to high-level glitch in Table Power-Up
Glitches on Pins

• Updated notes for Table Power-Up Glitches on Pins

• Added links to the Technical Reference Manual and Peripheral Pin Con-
figurations in Chapter 3 Functional Description
• Added a note about ADC2 error in Section 3.3.1 Analog-to-Digital Con-
verter (ADC)
2022-11-15 v1.3 • Updated Section 3.8.3 Watchdog Timers
• Added Table ADC Calibration Results
• Updated Section 4.6.2 Current Consumption in Other Modes
• Updated RF transmit power in Section 4.9 Bluetooth LE Radio
• Updated the typo in Section 5 Package Information
• Updated Chapter 6 Related Documentation and Resources

• Added a new chip variant ESP32-C3FH4AZ;

• Updated Figure Block Diagram of ESP32-C3;
2022-04-13 v1.2
• Added the wake up source for Deep-sleep mode in Section 3.7 Low
Power Management.

• Updated Figure Block Diagram of ESP32-C3 to show power modes;

• Added CoreMark score in Features;
• Updated Table Pin Description to show default pin functions;
2021-10-26 v1.1 • Updated Figure ESP32-C3 Power Scheme and related descriptions;
• Added Table Mapping of SPI Signals and Chip Pins;
• Added note 3 to Table Recommended Operating Conditions;
• Other updates to wording.

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Revision History

Date Version Release Notes

• Updated power modes;

• Updated Section 2.4 Strapping Pins;
• Updated some clock names and their frequencies in Section 3.2 System
Clocks;
• Added clarification about ADC1 and ADC2 in Section 3.3.1 Analog-to-
Digital Converter (ADC);
2021-05-28 v1.0
• Updated the default configuration of U0RXD andU0TXD after reset in
Table IO MUX Pin Functions;
• Updated sampling rate in Table ADC Characteristics;
• Updated Table Reliability Qualifications;
• Added the link to recommended PCB land pattern in Chapter 5 Package
Information.

2021-04-23 v0.8 Updated Wi-Fi Radio and Bluetooth LE Radio data.

• Updated information about USB Serial/JTAG Controller;

• Added GPIO2 to Section 2.4 Strapping Pins;
• Updated Figure Address Mapping Structure;
• Added Table IO MUX Pin Functions and Table Power-Up Glitches on Pins
in Section 3.4.1 General Purpose Input / Output Interface (GPIO);
2021-04-07 v0.7
• Updated information about SPI2 in Section 3.4.2 Serial Peripheral Inter-
face (SPI);
• Updated fixed-priority channel scheme in Section 3.4.8 General DMA
Controller;
• Updated Table Reliability Qualifications.

• Clarified that of the 400 KB SRAM, 16 KB is configured as cache;

2021-01-18 v0.6 • Updated maximum value to standard limit value in Table TX EVM Test in
Section 4.8.1 Wi-Fi RF Transmitter (TX) Specifications.

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Revision History

Date Version Release Notes

• Updated information about Wi-Fi;

• Added connection between embedded flash ports and chip pins to ta-
ble notes in Section 2.2 Pin Description;
• Updated Figure ESP32-C3 Power Scheme, added Figure ESP32-C3
Power-up and Reset Timing and Table Description of ESP32-C3 Power-
up and Reset Timing Parameters in Section 2.3 Power Scheme;
2021-01-13 v0.5 • Added Figure Setup and Hold Times for the Strapping Pins and Table
Parameter Descriptions of Setup and Hold Times for the Strapping Pins in
Section 2.4 Strapping Pins;
• Updated Table Peripheral Pin Configurations in Section 3.11 Peripheral
Pin Configurations;
• Added Chapter 4 Electrical Characteristics;
• Added Chapter 5 Package Information.

2020-11-27 v0.4 Preliminary version.

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 Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice.
ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO
WARRANTIES TO ITS AUTHENTICITY AND ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-
INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
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in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any
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The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
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www.espressif.com of their respective owners, and are hereby acknowledged.
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