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1 TRANSISTORS
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
The transistor can be a high or low resistance device, hence the name, which is derived from TRANSfer resISTOR. It is used in many switching and amplifier circuits where its resistive properties are controlled by small currents. 1.1 TRANSISTOR CONSTRUCTION The properties of semi-conductor materials, P and N type, were discussed in Module 4.1.1. A transistor is made up of these materials in the configurations shown in Figure 1. The circuit symbols for these transistors are also shown.
COLLECTOR
N
BASE
CIRCUIT SYMBOL
P N
EMITTER
N OT P OINTING IN E
COLLECTOR
THE NPN TRANSISTOR
P
BASE
CIRCUIT SYMBOL
N P
EMITTER
THE PNP TRANSISTOR
PNP & NPN Transistors Figure 1
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1. 2.
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
As can be seen from figure 1, there are two possible types of physical arrangement: The N-P-N transistor, which consists of a thin region of P-type material, sandwiched between two Ntype regions. The P-N-P transistor, which consists of a thin region of N-type material, sandwiched between two Ptype regions.
The centre region of the device is called the Base; one outer region is called the Emitter, and the other the Collector. Although the emitter and collector regions are the same type of extrinsic semiconductor (N-type in N-P-N and P-type in P-N-P), they are constructed and doped differently and are not interchangeable on a practical device.
The circuit symbol for both P-N-P and N-P-N are shows in figure 1. The only difference between them is the direction of the arrowhead on the emitter lead. For either type, the arrowhead indicates the direction of Conventional current flow when the base/emitter junction is forward biased (i.e. base +ve with respect to emitter for an N-P-N device, and base ve relative to emitter for a P-N-P device).
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
1.2 TRANSISTOR OPERATION Figure 2 shows a NPN transistor and the corresponding diode circuit. It can be seen from the diode circuit that to operate, the base/emitter must be forward biased, whereas the base/collector is reversed biased.
N - TYPE
B
P - TYPE N - TYPE
E
DIODE MODEL
NPN Transistor & Diode Circuit Figure 2
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 3 shows a simple transistor circuit using electron flow to explain the operation.
IC HIGH (99%)
C B E
IB LOW (1%)
IE HIGH (100%)
NPN Transistor Operation Figure 3
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
1.3 SWITCHING TRANSISTORS
When a transistor is to be used as a switching device, it operates either as an open circuit (i.e. in the cut-off region) or as a short circuit (i.e. in the saturation region). Figure 3 shows the solenoid switch and an alternative transistor switch.
LAMP
SOLENOID ANALOGY
E B
Switching Transistors Figure 3
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
For a common base circuit, such as in figure 3, the output voltage taken from the collector is either equal to the supply voltage (saturated region), or zero volts. (cut-off).
1.4 AMPLIFIER TRANSISTORS
Successful use of a transistor as an amplifier depends upon the collector current being controlled by the base. Amplification in a transistor is called Gain and is the relationship between base current to collector current. Figure 4 shows amplifier gain.
AMPLIFIER
INPUT SIGNAL
AMPLIFICATION IN A TRANSISTOR IS CALLED GAIN
OUTPUT SIGNAL
COLLECTOR CURRENT GAIN = BASE CURRENT
IC =I B
Amplifier Gain Figure 4
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
1.4.1 OUTPUT CHARACTERISTICS (LOAD LINE)
Figure 5 shows a Common Emitter amplifier stage. Common Emitter Amplifier Stage
+40V
RL IC IB VCE VBE
Figure 5 With no base/emitter bias applied, there will be no collector current flowing. The output voltage VCE will be equal to the supply voltage (40V). As the collector current IC flows through resistor RL there will be a voltage drop (IC x RL) across the resistor. The collector voltage will depend upon the collector current i.e. 40V minus IC x RL volts. If IC is zero, then VCE must be 40v. VCE could be reduced to zero by a value of IC of 40/RL amperes. If we assume RL to have a value of 18 ohms, then VCE will be zero for an IC of approximately 2.2 amperes.
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IC
2.5
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 6 shows a graph plotting collector current against collector/emitter voltage for different values of base current.
2.0
35mA
1.5
25mA 15mA
1.0
0.5
VCE
10 20 30 40 50 60 70
Common Emitter Characteristics Figure 6
The straight line from the collector/emitter voltage axis to the collector current axis is the Load Line and indicates the only values of VCE and IC which are possible for that circuit. Obviously, if a different value of RL is used, we would get a different load line with a different slope.
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
For amplifiaction to take place we must first apply an initial bias voltage to the base. With 1.3 VBE applied the IB will be 25mA giving an IC of 1.4A which would produce an output of 15V (VCE). If we now apply a sinusoidal input signal of 0.6V, the base current would vary between 15 -35mA, which in turn would vary the IC between 1.1 1.7A, giving a voltage output between 10 20V. This produces an amplifier gain of 0.6A/25mA = 30. Figure 7 shows the voltage/current waveforms of these variations.
20 V
15 V
35mA
25mA
15mA
1.6 V
1.3 V
1.0 V
VCE
1.7 A
1.4 A
VBE
Waveform Variations (Current/Voltage) Figure 7
1.1 A
IC
10 V
IB
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 8 shows a typical bipolar transistor.
TAG
c EMITTER
BASE COLLECTOR
Bipolar Transistor Figure 8
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
1.5 TRANSISTOR CONFIGURATIONS
Before a transistor can be used, it must be connected into an input circuit (by two wires) and an output circuit (two wires). However, because the transistor has only three terminals, one of the terminals must be in both the input and output circuits; this is then called The Common terminal. Three circuit configurations are possible and are illustrated in figure 9.
C B O UTPU T INP UT E INP UT
O UTPU T
CO M M ON E MITTE R
CO M M ON B AS E
E B O UTPU T INP UT C
CO M M ON C OLLE CTO R
Transistor Configurations Figure 9 Note that the word common refers to the transistor component connected to both the INPUT and OUTPUT. In the common emitter configuration for example, the emitter is connected to both the input and output.
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Table 1 shows the comparisons of the three transistor configurations
Common Emitter
Common Base (0.95 0.995) 500 800 Medium
Common Collector
Current Gain Voltage Gain Power Gain Input Impedance Output Impedance I/P O/P Phase Typical Use
20 -200 100 600 Highest
20 - 200 <1 Lowest
500 - 2000 10 50 K 180 Normal Amp
50 - 200 100 k - 1M In Phase Impedance matching (low to high) Table 1
20k - 100k 20 500 In Phase Impedance matching (high to low)
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1.6
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
FIELD EFFECT TRANSISTORS (FET)
A field-effect transistor (FET) is a semiconductor device in which the current flowing through a conduction channel i.e. between two terminals called the Source and the Drain and is controlled by an electric field arising from a voltage applied to another terminal, called the Gate). There are two classes of field-effect transistor: 1. 2. The Junction-Gate Field-effect Transistor (JUGFET). The Insulated-Gate Field-Effect Transistor (IGFET).
JUGFET: Has one (or more) semiconductor gate regions, which form P-N junction with the channel. IGFET: Has an insulating layer (usually of oxide material) between the channel and the gate electrode (usually metal) It is often called the MOSFET (Metal Oxide semiconductor FET). There is a furtyher subdivision of filed-effect transistors which isd due to the doping of the semiconductor: 1. 2. An N-Channel field-effect transistor has an N-Type semiconducting channel. A P-Channel field-effect transistor has a P-Type semiconducting channel.
1.6.1 CONSTRUCTION
Suppose we have a semiconductor bar of N-type material with contacts on each end. If a voltage is applied between these two contacts, current will flow through the bar, caused almost entirely by drift of majority carriers (which are electrons for an N-Type bar). The terminal through which the majority carriers enter the bar is usually called the Source and the terminal through which the majority carriers leave the bar is called the Drain. The drain-to-source voltage is usually called VDS. It is positive for normal operation of an N-channel device. On both sides of the N-type bar, heavily doped P-Type regions have been formed (using usual techniques for making P-N junctions). The two regions are connected together and brought out to the Gate terminal. The region of N-Type material between the two gate regions is called the Channel along which the majority carriers drift from source to drain. Between the gate and the source terminals a bias (called VGS) is applied to reverse bias the P-N junctions between the regions and the channel. For an N-channel device VGS will be negative. As the junctions are reversed biased there will be almost zero current at the gate terminal.
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 10 shows the construction of a JUGFET.
GATE DRAIN REGION
SOURCE REGION
SOURCE
DRAIN
P-TYPE
N TYPE
N-TYPE CHANNEL GATE
N TYPE
JUGFET Construction Figure 10
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1.6.2 JFET OPERATION
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 11 shows the operation of a JFET.
ELECTRONS FLOW THROUGH THE N-TYPE MATERIAL
S O U R CE N R E G IO N
D RA IN N R E G IO N
P R E GI O N S
G A TE
CHARGE CARRIERS FORCED OUT O F THESE REG IONS
HIGH ENO UG H G ATE VOLTAGE WILL CLOSE CHANNEL COMPLETELY
SOURCE
DRAIN
SOURCE
DRAIN NO OUTPUT
GATE
GATE
GATE VOLTAGE
GATE VOLTAGE
JFET Operation Figure 11 The JUGFET has a physical structure that can be represented by the diagram shown in Figure 11a. In Figure 11b, if the N-Type material is connected to a power source, current will flow through it. It can be seen that the power source could be connected either way, the source and drain being interchangeable. The current flow consists of electrons moving through the N-Type semiconductor. In Figure 11c, a negative potential is applied to the gate regions. The junction between the P-Type and NType regions forms a reversed-biased diode, so no current flows. However, an electric filed extends into the N-Type bar from the P-Type regions. This charge forces current carriers (electrons) away from the region, reducing the amount of the N-Type material for conducting between the source and the drain. If the potential applied to the gate is made sufficiently negative (Figure 11d), the electric field will extend across the whole thickness of the N-Type material. Hardly any charge carriers will be available for current
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
flow, and the current available from the drain will drop to a very low value (never to zero, for it is physically impossible for the channel to close completely). Changes in the voltage applied to the gate will cause corresponding changes in the current flowing between the source and the drain, which makes the operation of the FET very similar to a bipolar transistor. Figure 12 shows a typical JFET.
FLAT SIDE
DRAIN
GATE
SOURCE
Junction Field Effect Transistor (JFET) Figure 12
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1.6.3 CIRCUIT SYMBOL
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 13 shows the circuit symbol for an N-Channel and P-Channel JUGFET.
DRAIN
GATE
SOURCE
N-CHANNEL JUGFET
DRAIN
GATE
SOURCE
P-CHANNEL JUGFET
N-Channel P-Channel JUGFET Circuit Symbol Figure 13 Table 2 shows the comparisons between N & P-channel JUGFETs.
N-CHANNEL Volts Drain-Source Majority Carriers Drain positive wrt Source Electrons
P-CHANNEL Drain negative wrt Source Holes
Bias to decrease drain current Wrt: With respect to.
Gate negative wrt Source
Gate positive wrt Source
Table 2
1.6.4 DRAIN CHARACTERISTICS
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IDS
(mA)
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
The drain characteristics of an N-Channel depletion-mode JUGFET in the common source configuration is shown if figure 14.
VGS = -0V
8 7
VGS = -1V
6 5
VGS = -2V
4 3
VGS = -3V
2
VGS = -4V
VDS
5 10 15 20 25
(VOLTS)
Drain Characteristics N-Channel JUGFET Figure 14
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1.6.5 INSULATED-GATE FET
JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
The insulated-gate field-effect transistor (IGFET) has one, or more, gate electrode(s) electrically insulated from the channel. In most devices the insulation is a layer of oxide and the name metal-oxide semicondutcor transistor (MOST) or MOSFET is commonly used. In these devices an electric field is produced in the insulating (oxide) layer by a voltage applied to a metal gate electrode. This electric field controls the number of charge carries in the semiconductor channel and thus controls the current flow between the source and drain terminals. The MOSFET is a more versatile device than the JUGFET and is widely used in integrated circuits as well as discrete transistors. As well as P and N-channel devices, it is possible to manufacture MOSFETs to operate either: 1. 2. Enhancement-Mode device. Depletion-Mode device.
1.6.6 DEPLETION MODE MOSFET
In the depletion-mode type, charge carriers are present in the channel at Zero gate bias and the device is, therefore, conducting. The application of a gate voltage, which depletes the number of charge carriers in the channel thus reduces the conductivity and is called reverse gate bias. This type of operation is similar to that of the JUGFET previously discussed. Because the gate is insulated from the channel it is also possible to apply the forward gate bias without drawing gate current. This bias draws more charge carriers into the channel and results in an increase in conductivity.
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 15 shows an P-channel Depletion type MOSFET.
GAT E SOURCE DRAIN
P -C HA N NE L
POS ITIVE BIAS APPLIED GATE SOURCE DRAIN
P -C HA N NE L NARROWER CONDUCTING CHANNEL
P-channel Depletion Type MOSFET Figure 15
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
1.6.7 ENHANCEMENT MODE MOSFET
In the enhancement-mode type, the gate must be forward biased to produce charge carriers in the channel. These devices are normally of and do not conduct either at zero gate bias or for reverse gate bias. Figure 16 shows P-channel enhancement type MOSFET.
GATE SOURCE DRAIN
METAL OXIDE
SEMICONDUCTO R
NEGATIVE BIAS APPLIED GATE SOURCE DRAIN
P-channel Enhancement Type MOSFET Figure 16
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JAR 66 CATEGORY B1 COVERSION COURSE MODULE 4
MODULE 4.1.2. TRANSISTORS
Figure 17 shows the circuit symbols for P-Channel/N-Channel Depletion MOSFETS, figure 18 NChannel/P-Channel Enhancement MOSFETS.
DRAIN P-CHANNEL
GATE
N-CHANNEL
SOURCE
Depletion Mode MOSFET Circuit Symbols Figure 17 Enhancement Mode MOSFET Circuit Symbols
DRAIN P-CHANNEL
GATE
N-CHANNEL
SOURCE
Figure 18
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JAR 66 CATEGORY B1 MODULE 4 ELECTRONIC FUNDAMENTALS
MODULE 4.1.2. TRANSISTORS
