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Lab_3 Handouts NAND_NOR AND_OR Gates

The document outlines the objectives and tasks for VLSI Lab# 3, focusing on the design and analysis of NAND and NOR gates using LT-Spice. Key activities include creating schematics, performing transient analysis, and calculating propagation delay and average power dissipation. The lab report emphasizes hands-on experimentation and comparison with theoretical expectations.

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Hasham Sohail
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10 views

Lab_3 Handouts NAND_NOR AND_OR Gates

The document outlines the objectives and tasks for VLSI Lab# 3, focusing on the design and analysis of NAND and NOR gates using LT-Spice. Key activities include creating schematics, performing transient analysis, and calculating propagation delay and average power dissipation. The lab report emphasizes hands-on experimentation and comparison with theoretical expectations.

Uploaded by

Hasham Sohail
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Lab# 3

Engr. Muhammad Sohail

Learning Objectives
• To draw NAND Gate Schematic and Perform its transient Analysis
• To create NAND Gate Symbol Library
• Call NAND gate and Inverter within an AND gate schematic to
perform transient analysis.
• Analyze Propagation Delay and average power dissipation from
waveforms
• Calculate Propagation Delay and average power dissipation via SPICE
Directives
• Lab Performance Report
Lab Performance Report#3
• Task#1: Create NAND gate schematic and symbol in LT-Spice. Call the NAND gate symbol you created from the component library into a
new schematic. Perform its transient analysis using two different pulse inputs of your own choice (make sure that each of tr and tf should
be 5% of the time period.) Vary the PMOS and NMOS transistor sizes till you get a symmetric output waveform.

• Task#2: Create NOR gate schematic and symbol in LT-Spice. Call the NAND gate symbol you created from the component library into a new
schematic. Perform its transient analysis using two different pulse inputs of your own choice (make sure that each of tr and tf should be 5%
of the time period.) Vary the PMOS and NMOS transistor sizes till you get a symmetric output waveform.

• Perform following analysis for both NAND and NOR Gates

• Analysis#1: Perform Transient analysis for 3 time periods of the input pulse with larger T. Show output vs input voltage waveforms. Write
your observations by comparing it with truth-table.

𝟏
• Analysis#2: Find the Propagation Delay using a simple waveform observation technique as discussed in the demo: tpHL , tpLH and tp1= (tpHL
𝟐
+ tpLH). Reduce the rise and fall times of the input waveforms to 0.1% of their respective time-periods. Again, find the average propagation
delay tp2. Compare tp2 with the previous tp1 to see the effect of change in tr and tf. Write down your observations in few lines.

• Analysis#3: Find the Propagation Delay this time using .meas spice directive and report the log file’s screenshot. Write your observation in
two lines.

• Analysis#4: Find the Average Power consumption for input with longer T using .meas SPICE directive.

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