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64 Mbit (x16) Multi-Purpose Flash Plus

SST39VF6401B / SST39VF6402B
SST39VF640xB2.7V 64Mb (x16) MPF+ memories Data Sheet
FEATURES:
• Organized as 4M x16 • Fast Read Access Time:
• Single Voltage Read and Write Operations – 70 ns
– 2.7-3.6V – 90 ns
• Superior Reliability • Latched Address and Data
– Endurance: 100,000 Cycles (Typical) • Fast Erase and Word-Program:
– Greater than 100 years Data Retention – Sector-Erase Time: 18 ms (typical)
• Low Power Consumption (typical values at 5 MHz) – Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Active Current: 9 mA (typical) – Word-Program Time: 7 µs (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical) • Automatic Write Timing
• Hardware Block-Protection/WP# Input Pin – Internal VPP Generation
– Top Block-Protection (top 32 KWord) • End-of-Write Detection
for SST39VF6402B – Toggle Bits
– Bottom Block-Protection (bottom 32 KWord) – Data# Polling
for SST39VF6401B • CMOS I/O Compatibility
• Sector-Erase Capability • JEDEC Standard
– Uniform 2 KWord sectors – Flash EEPROM Pin Assignments
• Block-Erase Capability – Software command sequence compatibility
– Uniform 32 KWord blocks - Address format is 11 bits, A10-A0
- Block-Erase 6th Bus Write Cycle is 30H
• Chip-Erase Capability
- Sector-Erase 6th Bus Write Cycle is 50H
• Erase-Suspend/Erase-Resume Capabilities
• Packages Available
• Hardware Reset Pin (RST#)
– 48-lead TSOP (12mm x 20mm)
• Security-ID Feature – 48-ball TFBGA (8mm x 10mm)
– SST: 128 bits; User: 128 bits • All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION configuration, or data memory. For all system applications,

they significantly improve performance and reliability, while
The SST39VF640xB devices are 4M x16 CMOS Multi- lowering power consumption. They inherently use less
Purpose Flash Plus (MPF+) manufactured with SST’s pro- energy during Erase and Program than alternative flash
prietary, high-performance CMOS SuperFlash technology. technologies. The total energy consumed is a function of
The split-gate cell design and thick-oxide tunneling injector the applied voltage, current, and time of application. Since
attain better reliability and manufacturability compared with for any given voltage range, the SuperFlash technology
alternate approaches. The SST39VF640xB write (Pro- uses less current to program and has a shorter erase time,
gram or Erase) with a 2.7-3.6V power supply. These the total energy consumed during any Erase or Program
devices conform to JEDEC standard pin assignments for operation is less than alternative flash technologies. These
x16 memories. devices also improve flexibility while lowering the cost for
Featuring high performance Word-Program, the program, data, and configuration storage applications.
SST39VF640xB devices provide a typical Word-Program The SuperFlash technology provides fixed Erase and Pro-
time of 7 µsec. These devices use Toggle Bit or Data# Poll- gram times, independent of the number of Erase/Program
ing to indicate the completion of Program operation. To pro- cycles that have occurred. Therefore the system software
tect against inadvertent write, they have on-chip hardware or hardware does not have to be modified or de-rated as is
and Software Data Protection schemes. Designed, manu- necessary with alternative flash technologies, whose Erase
factured, and tested for a wide spectrum of applications, and Program times increase with accumulated Erase/Pro-
these devices are offered with a guaranteed typical endur- gram cycles.
ance of 100,000 cycles. Data retention is rated at greater
than 100 years. To meet high-density, surface mount requirements, the
SST39VF640xB devices are offered in 48-lead TSOP and
The SST39VF640xB devices are suited for applications that 48-ball TFBGA packages. See Figures 1 and 2 for pin
require convenient and economical updating of program, assignments.

©2006 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
S71288-02-000 7/06 MPF is a trademark of Silicon Storage Technology, Inc.
1 These specifications are subject to change without notice.
 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
Device Operation Any commands issued during the internal Program opera-
tion are ignored. During the command sequence, WP#
Commands are used to initiate the memory operation func-
should be statically held high or low.
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE# Sector/Block-Erase Operation
low. The address bus is latched on the falling edge of WE# The Sector- (or Block-) Erase operation allows the system
or CE#, whichever occurs last. The data bus is latched on to erase the device on a sector-by-sector (or block-by-
the rising edge of WE# or CE#, whichever occurs first. block) basis. The SST39VF640xB offer both Sector-Erase
The SST39VF640xB also have the Auto Low Power and Block-Erase mode. The sector architecture is based
mode which puts the device in a near standby mode after on uniform sector size of 2 KWord. The Block-Erase mode
data has been accessed with a valid Read operation. This is based on uniform block size of 32 KWord. The Sector-
reduces the IDD active read current from typically 9 mA to Erase operation is initiated by executing a six-byte com-
typically 3 µA. The Auto Low Power mode reduces the typi- mand sequence with Sector-Erase command (50H) and
cal IDD active read current to the range of 2 mA/MHz of sector address (SA) in the last bus cycle. The Block-Erase
Read cycle time. The device exits the Auto Low Power operation is initiated by executing a six-byte command
mode with any address transition or control signal transition sequence with Block-Erase command (30H) and block
used to initiate another Read cycle, with no access time address (BA) in the last bus cycle. The sector or block
penalty. Note that the device does not enter Auto-Low address is latched on the falling edge of the sixth WE#
Power mode after power-up with CE# held steadily low, pulse, while the command (50H or 30H) is latched on the
until the first address transition or CE# is driven high. rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Read Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
The Read operation of the SST39VF640xB is controlled ing waveforms and Figure 23 for the flowchart. Any com-
by CE# and OE#, both have to be low for the system to mands issued during the Sector- or Block-Erase operation
obtain data from the outputs. CE# is used for device are ignored. When WP# is low, any attempt to Sector-
selection. When CE# is high, the chip is deselected and (Block-) Erase the protected block will be ignored. During
only standby power is consumed. OE# is the output con- the command sequence, WP# should be statically held
trol and is used to gate data from the output pins. The high or low.
data bus is in high impedance state when either CE# or
OE# is high. Refer to the Read cycle timing diagram for Erase-Suspend/Erase-Resume Commands
further details (Figure 3).
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
Word-Program Operation read from any memory location, or program data into any
The SST39VF640xB are programmed on a word-by-word sector/block that is not suspended for an Erase operation.
basis. Before programming, the sector where the word The operation is executed by issuing one byte command
exists must be fully erased. The Program operation is sequence with Erase-Suspend command (B0H). The
accomplished in three steps. The first step is the three-byte device automatically enters read mode typically within 20
load sequence for Software Data Protection. The second µs after the Erase-Suspend command had been issued.
step is to load word address and word data. During the Valid data can be read from any sector or block that is not
Word-Program operation, the addresses are latched on the suspended from an Erase operation. Reading at address
falling edge of either CE# or WE#, whichever occurs last. location within erase-suspended sectors/blocks will output
The data is latched on the rising edge of either CE# or DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
WE#, whichever occurs first. The third step is the internal mode, a Word-Program operation is allowed except for the
Program operation which is initiated after the rising edge of sector or block selected for Erase-Suspend.
the fourth WE# or CE#, whichever occurs first. The Pro-
To resume Sector-Erase or Block-Erase operation which has
gram operation, once initiated, will be completed within 10
been suspended the system must issue Erase Resume
µs. See Figures 4 and 5 for WE# and CE# controlled Pro-
command. The operation is executed by issuing one byte
gram operation timing diagrams and Figure 19 for flow-
command sequence with Erase Resume command (30H)
charts. During the Program operation, the only valid reads
at any address in the last Byte sequence.
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
Chip-Erase Operation ‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
The SST39VF640xB provide a Chip-Erase operation,
Block- or Chip-Erase, the Data# Polling is valid after the
which allows the user to erase the entire memory array to
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
the “1” state. This is useful when the entire device must be
Data# Polling timing diagram and Figure 20 for a flowchart.
quickly erased.
The Chip-Erase operation is initiated by executing a six- Toggle Bits (DQ6 and DQ2)
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The During the internal Program or Erase operation, any con-
Erase operation begins with the rising edge of the sixth secutive attempts to read DQ6 will produce alternating “1”s
WE# or CE#, whichever occurs first. During the Erase and “0”s, i.e., toggling between 1 and 0. When the internal
operation, the only valid read is Toggle Bit or Data# Polling. Program or Erase operation is completed, the DQ6 bit will
See Table 6 for the command sequence, Figure 9 for tim- stop toggling. The device is then ready for the next opera-
ing diagram, and Figure 23 for the flowchart. Any com- tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
mands issued during the Chip-Erase operation are is valid after the rising edge of sixth WE# (or CE#) pulse.
ignored. When WP# is low, any attempt to Chip-Erase will DQ6 will be set to “1” if a Read operation is attempted on an
be ignored. During the command sequence, WP# should Erase-Suspended Sector/Block. If Program operation is ini-
be statically held high or low. tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
Write Operation Status Detection An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
The SST39VF640xB provide two software means to detect
sector is being actively erased or erase-suspended. Table 1
the completion of a Write (Program or Erase) cycle, in
shows detailed status bits information. The Toggle Bit
order to optimize the system write cycle time. The software
(DQ2) is valid after the rising edge of the last WE# (or CE#)
detection includes two status bits: Data# Polling (DQ7) and
pulse of Write operation. See Figure 7 for Toggle Bit timing
Toggle Bit (DQ6). The End-of-Write detection mode is
diagram and Figure 20 for a flowchart.
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
TABLE 1: WRITE OPERATION STATUS
The actual completion of the nonvolatile write is asyn-
Status DQ7 DQ6 DQ2
chronous with the system; therefore, either a Data# Poll-
Normal Standard DQ7# Toggle No Toggle
ing or Toggle Bit read may be simultaneous with the Operation Program
completion of the write cycle. If this occurs, the system
Standard 0 Toggle Toggle
may possibly get an erroneous result, i.e., valid data may Erase
appear to conflict with either DQ7 or DQ6. In order to pre- Erase- Read from 1 1 Toggle
vent spurious rejection, if an erroneous result occurs, the Suspend Erase-Suspended
software routine should include a loop to read the Mode Sector/Block
accessed location an additional two (2) times. If both Read from Data Data Data
Non- Erase-Suspended
reads are valid, then the device has completed the Write Sector/Block
cycle, otherwise the rejection is valid.
Program DQ7# Toggle N/A
T1.0 1288
Data# Polling (DQ7) Note: DQ7 and DQ2 require a valid address when reading
status information.
When the SST39VF640xB are in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
Data Protection Hardware Reset (RST#)
The SST39VF640xB provide both hardware and software The RST# pin provides a hardware method of resetting the
features to protect nonvolatile data from inadvertent writes. device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
Hardware Data Protection return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 required after RST# is driven high before a valid Read can
ns will not initiate a write cycle. take place (see Figure 15).
VDD Power Up/Down Detection: The Write operation is The Erase or Program operation that has been interrupted
inhibited when VDD is less than 1.5V. needs to be reinitiated after the device resumes normal
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# operation mode to ensure data integrity.
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down. Software Data Protection (SDP)
The SST39VF640xB provide the JEDEC approved Soft-
Hardware Block Protection ware Data Protection scheme for all data alteration opera-
The SST39VF6402B support top hardware block protec- tions, i.e., Program and Erase. Any Program operation
tion, which protects the top 32 KWord block of the device. requires the inclusion of the three-byte sequence. The
The SST39VF6401B support bottom hardware block pro- three-byte load sequence is used to initiate the Program
tection, which protects the bottom 32 KWord block of the operation, providing optimal protection from inadvertent
device. The Boot Block address ranges are described in Write operations, e.g., during the system power-up or
Table 2. Program and Erase operations are prevented on power-down. Any Erase operation requires the inclusion of
the 32 KWord when WP# is low. If WP# is left floating, it is six-byte sequence. These devices are shipped with the
internally held high via a pull-up resistor, and the Boot Software Data Protection permanently enabled. See Table
Block is unprotected, enabling Program and Erase opera- 6 for the specific software command codes. During SDP
tions on that block. command sequence, invalid commands will abort the
device to read mode within TRC. The contents of DQ15-DQ8
TABLE 2: BOOT BLOCK ADDRESS RANGES can be VIL or VIH, but no other value, during any SDP com-
mand sequence.
Product Address Range
Bottom Boot Block Common Flash Memory Interface (CFI)
SST39VF6401B 000000H-007FFFH
The SST39VF640xB also contain the CFI information to
Top Boot Block describe the characteristics of the device. In order to enter
SST39VF6402B 3F8000H-3FFFFFH the CFI Query mode, the system must write three-byte
T2.0 1288 sequence, same as product ID entry command with 98H
(CFI Query command) to address 555H in the last byte
sequence. Once the device enters the CFI Query mode,
the system can read CFI data at the addresses given in
Tables 7 through 9. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
Product Identification Security ID
The Product Identification mode identifies the devices as The SST39VF640xB devices offer a 256-bit Security ID
the SST39VF6401B and SST39VF6402B, and the manu- space. The Secure ID space is divided into two 128-bit seg-
facturer as SST. This mode may be accessed through ments - one factory programmed segment and one user
software operations. Users may use the Software Product programmed segment. The first segment is programmed
Identification operation to identify the part (i.e., using the and locked at SST with a random 128-bit number. The user
device ID) when using multiple manufacturers in the same segment is left un-programmed for the customer to pro-
socket. For details, see Table 6 for software operation, gram as desired.
Figure 11 for the Software ID Entry and Read timing dia-
To program the user segment of the Security ID, the user
gram and Figure 21 for the Software ID Entry command
must use the Security ID Word-Program command. To
sequence flowchart.
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
TABLE 3: PRODUCT IDENTIFICATION should be locked using the User Sec ID Program Lock-Out.
Address Data This disables any future corruption of this space. Note that
Manufacturer’s ID 0000H BFH regardless of whether or not the Sec ID is locked, neither
Device ID Sec ID segment can be erased.
SST39VF6401B 0001H 236DH The Secure ID space can be queried by executing a three-
SST39VF6402B 0001H 236CH byte command sequence with Enter Sec ID command
T3.0 1288 (88H) at address 555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Product Identification Mode Exit/ Refer to Table 6 for more details.
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 13 for timing waveform, and Figures 21 and
22 for flowcharts.

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

FUNCTIONAL BLOCK DIAGRAM

SuperFlash
X-Decoder Memory

Memory Address
Address Buffer & Latches
Y-Decoder

CE#
OE# I/O Buffers and Data Latches
WE# Control Logic
WP#
RESET# DQ15 - DQ0
1288 B1.0

A15 1 48 A16
A14 2 47 NC
A13 3 46 VSS
A12 4 45 DQ15
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
A19 9 Standard Pinout 40 DQ5
A20 10 39 DQ12
WE# 11 Top View 38 DQ4
RST# 12 37 VDD
A21 13 Die Up 36 DQ11
WP# 14 35 DQ3
NC 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0

1288 48-tsop P1.0

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

TOP VIEW (balls facing down)

6
A13 A12 A14 A15 A16 NC DQ15 VSS
5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# RST# A21 A19 DQ5 DQ12 VDD DQ4
3
NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

1288 4-tfbga B1K P2.0

1
A3 A4 A2 A1 A0 CE# OE# VSS

A B C D E F G H

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

TABLE 4: PIN DESCRIPTION

Symbol Pin Name Functions
AMS1-A0 Address Inputs To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.
RST# Reset To reset and return the device to Read mode.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
NC No Connection Unconnected pins.
T4.0 1288
1. AMS = Most significant address
AMS = A21 for SST39VF640xB

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
TABLE 5: OPERATION MODES SELECTION
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1 Sector or block address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
X X VIH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 6
T5.0 1288
1. X can be VIL or VIH, but no other value.

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
TABLE 6: SOFTWARE COMMAND SEQUENCE
Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
Word-Program 555H AAH 2AAH 55H 555H A0H WA3 Data
Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX4 50H
Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX 4 30H
Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Erase-Suspend XXXXH B0H
Erase-Resume XXXXH 30H
Query Sec ID5 555H AAH 2AAH 55H 555H 88H
User Security ID 555H AAH 2AAH 55H 555H A5H WA6 Data
Word-Program
User Security ID 555H AAH 2AAH 55H 555H 85H XXH6 0000H
Program Lock-Out
Software ID Entry7,8 555H AAH 2AAH 55H 555H 90H
CFI Query Entry 555H AAH 2AAH 55H 555H 98H
Software ID Exit9,10 555H AAH 2AAH 55H 555H F0H
/CFI Exit/Sec ID Exit
Software ID Exit9,10 XXH F0H
/CFI Exit/Sec ID Exit
T6.0 1288
1. Address format A10-A0 (Hex).
Addresses A11- A21 can be VIL or VIH, but no other value, for Command sequence for SST39VF640xB.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A21 for SST39VF640xB
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000010H to 000017H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF6401B Device ID = 236DH, is read with A0 = 1,
SST39VF6402B Device ID = 236CH, is read with A0 = 1.
AMS = Most significant address
AMS = A21 for SST39VF640xB
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000010H-000017H.

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

TABLE 7: CFI QUERY IDENTIFICATION STRING1 FOR SST39VF640XB

Address Data Data
10H 0051H Query Unique ASCII string “QRY”
11H 0052H
12H 0059H
13H 0002H Primary OEM command set
14H 0000H
15H 0000H Address for Primary Extended Table
16H 0000H
17H 0000H Alternate OEM command set (00H = none exists)
18H 0000H
19H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 0000H
T7.0 1288
1. Refer to CFI publication 100 for more details.

TABLE 8: SYSTEM INTERFACE INFORMATION FOR SST39VF640XB

Address Data Data
1BH 0027H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 0036H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 0000H VPP min. (00H = no VPP pin)
1EH 0000H VPP max. (00H = no VPP pin)
1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs)
20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported)
21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H 0000H Maximum time out for buffer program 2N times typical
25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T8.0 1288

TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39VF640XB

Address Data Data
27H 0017H Device size = 2N Bytes (17H = 23; 223 = 8 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0007H y = 2047 + 1 = 2048 sectors (07FFH = 2047)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 007FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y =127 + 1 = 128 blocks (007FH = 127)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T9.0 1288

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1

Limits
Symbol Parameter Min Max Units Test Conditions
IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read3 18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max
IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILIW Input Leakage Current 10 µA WP#=GND to VDD or RST#=GND to VDD
on WP# pin and RST#
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
VIH Input High Voltage 0.7VDD V VDD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T10.0 1288
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 17
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.

TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units
TPU-READ1 Power-up to Read Operation 100 µs
TPU-WRITE 1 Power-up to Program/Erase Operation 100 µs
T11.0 1288
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 12: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF
CIN 1 Input Capacitance VIN = 0V 6 pF
T12.0 1288
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 13: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method
NEND 1,2 Endurance 10,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78
T13.0 1288
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
AC CHARACTERISTICS

TABLE 14: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

SST39VF640xB-70 SST39VF640xB-90
Symbol Parameter Min Max Min Max Units
TRC Read Cycle Time 70 90 ns
TCE Chip Enable Access Time 70 90 ns
TAA Address Access Time 70 90 ns
TOE Output Enable Access Time 35 45 ns
TCLZ1 CE# Low to Active Output 0 0 ns
TOLZ1 OE# Low to Active Output 0 0 ns
TCHZ 1 CE# High to High-Z Output 20 30 ns
TOHZ1 OE# High to High-Z Output 20 30 ns
TOH1 Output Hold from Address Change 0 0 ns
TRP1 RST# Pulse Width 500 500 ns
TRHR 1 RST# High before Read 50 50 ns
TRY1,2 RST# Pin Low to Read Mode 20 20 µs
T14.0 1288
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.

TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units
TBP Word-Program Time 10 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1 WE# Pulse Width High 30 ns
TCPH1 CE# Pulse Width High 30 ns
TDS Data Setup Time 30 ns
TDH1 Data Hold Time 0 ns
TIDA1 Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
T15.0 1288
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

TRC TAA

ADDRESS AMS-0

TCE
CE#

TOE
OE#

VIH TOLZ TOHZ

WE#

TCHZ
TOH
HIGH-Z TCLZ HIGH-Z
DQ15-0
DATA VALID DATA VALID

1288 F03.0

Note: AMS = Most significant address

AMS = A21 for SST39VF640xB

FIGURE 3: READ CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 555 2AA 555 ADDR

TAH
TDH
TWP
WE#
TAS TWPH TDS

OE#

TCH
CE#

TCS

DQ15-0 XXAA XX55 XXA0 DATA

SW0 SW1 SW2 WORD

(ADDR/DATA) 1288 F04.0

Note: AMS = Most significant address

AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 555 2AA 555 ADDR

TAH
TDH
TCP
CE#
TAS TCPH TDS

OE#

TCH
WE#

TCS

DQ15-0 XXAA XX55 XXA0 DATA

SW0 SW1 SW2 WORD

(ADDR/DATA) 1288 F05.0

Note: AMS = Most significant address

AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS AMS-0

TCE

CE#

TOES
TOEH
OE#

TOE

WE#

DQ7 DATA DATA# DATA# DATA

1288 F06.0

Note: AMS = Most significant address

AMS = A21 for SST39VF640xB

FIGURE 6: DATA# POLLING TIMING DIAGRAM

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

ADDRESS AMS-0

TCE

CE#

TOE TOES
TOEH

OE#

WE#

DQ6 and DQ2

TWO READ CYCLES

1288 F07.0
WITH SAME OUTPUTS

Note: AMS = Most significant address

AMS = A21 for SST39VF640xB

FIGURE 7: TOGGLE BITS TIMING DIAGRAM

TSCE
SIX-BYTE CODE FOR CHIP-ERASE

ADDRESS AMS-0 555 2AA 555 555 2AA 555

CE#

OE#

TWP

WE#

DQ15-0
XXAA XX55 XX80 XXAA XX55 XX10

SW0 SW1 SW2 SW3 SW4 SW5 1288 F08.0

Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

TBE
SIX-BYTE CODE FOR BLOCK-ERASE

ADDRESS AMS-0 555 2AA 555 555 2AA BAX

CE#

OE#

TWP

WE#

DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30

1288 F09.0
SW0 SW1 SW2 SW3 SW4 SW5
Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
BAX = Block Address
AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

SIX-BYTE CODE FOR SECTOR-ERASE TSE

ADDRESS AMS-0 555 2AA 555 555 2AA SAX

CE#

OE#

TWP

WE#

DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50

1288 F10.0
SW0 SW1 SW2 SW3 SW4 SW5
Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
SAX = Sector Address
AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

Three-Byte Sequence for Software ID Entry

ADDRESS A14-0 555 2AA 555 0000 0001

CE#

OE#

TWP TIDA

WE#

TWPH
TAA
DQ15-0
XXAA XX55 XX90 00BF Device ID

SW0 SW1 SW2 1288 F11.0

Note: Device ID = 236DH for SST39VF6401B and 236CH for SST39VF6402B

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 11: SOFTWARE ID ENTRY AND READ

Three-Byte Sequence for CFI Query Entry

ADDRESS A14-0 555 2AA 555

CE#

OE#

TWP TIDA

WE#

TWPH
TAA
DQ15-0
XXAA XX55 XX98
1288 F12.0
SW0 SW1 SW2

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 12: CFI QUERY ENTRY AND READ

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A14-0 555 2AA 555

DQ15-0 XXAA XX55 XXF0

TIDA
CE#

OE#

TWP
WE#
TWHP
1288 F13.0
SW0 SW1 SW2
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS AMS-0 555 2AA 555

CE#

OE#

TWP TIDA

WE#

TWPH
TAA
DQ15-0
XXAA XX55 XX88
1288 F14.0
SW0 SW1 SW2

Note: AMS = Most significant address

AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.

FIGURE 14: SEC ID ENTRY

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

TRP

RST#

CE#/OE# TRHR
1288 F15.0

FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

TRP

RST#
TRY

CE#/OE#

End-of-Write Detection
(Toggle-Bit) 1288 F16.0

FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

VIHT

INPUT VIT REFERENCE POINTS VOT OUTPUT

VILT

1288 F17.0

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO TESTER

TO DUT

CL

1288 F18.0

FIGURE 18: A TEST LOAD EXAMPLE

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load Word
Address/Word
Data

Wait for end of

Program (TBP,
Data# Polling
bit, or Toggle bit
operation)

Program
Completed

1288 F19.0

X can be VIL or VIH, but no other value

FIGURE 19: WORD-PROGRAM ALGORITHM

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

Internal Timer Toggle Bit Data# Polling

Program/Erase Program/Erase Program/Erase

Initiated Initiated Initiated

Wait TBP, Read word Read DQ7

TSCE, TSE
or TBE

Read same No Is DQ7 =

Program/Erase word true data?
Completed
Yes

No Does DQ6 Program/Erase

match? Completed

Yes

Program/Erase
Completed
1288 F20.0

FIGURE 20: WAIT OPTIONS

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

CFI Query Entry Sec ID Query Entry Software Product ID Entry

Command Sequence Command Sequence Command Sequence

Load data: XXAAH Load data: XXAAH Load data: XXAAH

Address: 555H Address: 555H Address: 555H

Load data: XX55H Load data: XX55H Load data: XX55H

Address: 2AAH Address: 2AAH Address: 2AAH

Load data: XX98H Load data: XX88H Load data: XX90H

Address: 555H Address: 555H Address: 555H

Wait TIDA Wait TIDA Wait TIDA

Read CFI data Read Sec ID Read Software ID

X can be VIL or VIH, but no other value

1288 F21.0

FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XXAAH Load data: XXF0H

Address: 555H Address: XXH

Load data: XX55H

Wait TIDA
Address: 2AAH

Load data: XXF0H Return to normal

Address: 555H operation

Wait TIDA

Return to normal
operation

X can be VIL or VIH, but no other value

1288 F22.0

FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

Chip-Erase Sector-Erase Block-Erase

Command Sequence Command Sequence Command Sequence

Load data: XXAAH Load data: XXAAH Load data: XXAAH

Address: 555H Address: 555H Address: 555H

Load data: XX55H Load data: XX55H Load data: XX55H

Address: 2AAH Address: 2AAH Address: 2AAH

Load data: XX80H Load data: XX80H Load data: XX80H

Address: 555H Address: 555H Address: 555H

Load data: XXAAH Load data: XXAAH Load data: XXAAH

Address: 555H Address: 555H Address: 555H

Load data: XX55H Load data: XX55H Load data: XX55H

Address: 2AAH Address: 2AAH Address: 2AAH

Load data: XX10H Load data: XX50H Load data: XX30H

Address: 555H Address: SAX Address: BAX

Wait TSCE Wait TSE Wait TBE

Chip erased Sector erased Block erased

to FFFFH to FFFFH to FFFFH

1288 F23.0

X can be VIL or VIH, but no other value

FIGURE 23: ERASE COMMAND SEQUENCE

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
PRODUCT ORDERING INFORMATION

SST 39 VF 6402B - 70 - 4C - EK E
XX XX XXXXB - XXX - XX - XXX X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B1 = TFBGA (8mm x 10mm, 0.8mm pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
640 = 64 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash Plus

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
Valid Combinations for SST39VF6401B
SST39VF6401B-70-4C-EK SST39VF6401B-70-4C-B1K
SST39VF6401B-70-4C-EKE SST39VF6401B-70-4C-B1KE
SST39VF6401B-90-4C-EK SST39VF6401B-90-4C-B1K
SST39VF6401B-90-4C-EKE SST39VF6401B-90-4C-B1KE
SST39VF6401B-70-4I-EK SST39VF6401B-70-4I-B1K
SST39VF6401B-70-4I-EKE SST39VF6401B-70-4I-B1KE
SST39VF6401B-90-4I-EK SST39VF6401B-90-4I-B1K
SST39VF6401B-90-4I-EKE SST39VF6401B-90-4I-B1KE

Valid Combinations for SST39VF6402B

SST39VF6402B-70-4C-EK SST39VF6402B-70-4C-B1K
SST39VF6402B-70-4C-EKE SST39VF6402B-70-4C-B1KE
SST39VF6402B-90-4C-EK SST39VF6402B-90-4C-B1K
SST39VF6402B-90-4C-EKE SST39VF6402B-90-4C-B1KE
SST39VF6402B-70-4I-EK SST39VF6402B-70-4I-B1K
SST39VF6402B-70-4I-EKE SST39VF6402B-70-4I-B1KE
SST39VF6402B-90-4I-EK SST39VF6402B-90-4I-B1K
SST39VF6402B-90-4I-EKE SST39VF6402B-90-4I-B1KE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet
PACKAGING DIAGRAMS

1.05
0.95
Pin # 1 Identifier

0.50
BSC

0.27
12.20 0.17
11.80

0.15
18.50 0.05
18.30

DETAIL
1.20
max.
0.70
0.50 20.20
19.80
0˚- 5˚
0.70
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, 0.50
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
1mm
3. Coplanarity: 0.1 mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM

SST PACKAGE CODE: EK

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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 64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Data Sheet

TOP VIEW BOTTOM VIEW

10.00 ± 0.20 5.60
0.80

6 6
5 5
4.00
4 4
8.00 ± 0.20
3 3
2 2
1 1
0.80
0.45 ± 0.05
(48X)

A B C D E F G H H G F E D C B A

A1 CORNER A1 CORNER

1.10 ± 0.10
SIDE VIEW

0.12 1mm
SEATING PLANE
0.35 ± 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm) 48-tfbga-B1K-8x10-450mic-4

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM

SST PACKAGE CODE: B1K

TABLE 16: REVISION HISTORY

Number Description Date
00 • Initial release Mar 2005
01 • Clarified JEDEC software command compatibility on page 1 May 2005
02 • Changed document phase from Preliminary Information to Data Sheet Jul 2006

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com

©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06

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