13.

7 INTERRUPT
An
interrupt is the process which allows the processor to suspend its current execution and
Tespond to the
external/internal request. This request may either be single or multiple (which
can be handled the
on
priority basis).
An interrupt can be
provided to the processor in either of the following two ways:
Internally by an instruction of a program.
(This has been already discussed in section C)
Externally by a peripheral device.
With programmed I/0, the problem was the processor time has wasted. With
interrupt-initiated
1/0, the
I/0 interface informs the processor when it is
ready for transfer in the form an
interrupt (Fig.13.13). When the processor receives an
F interrupt signal from the peripheral, it
stops executing the current program and respond the
requesting peripheral.
13.7.1 Interrupt handling
Let discuss the
us
processor's role in interrupt-initiated I/0 in more detail. The occurrence of an
interrupt causes a number of.events both in processor hardware and software.
a typical
sequence. After completing the I/0 operation by the 1/0
Fig.13.16 shows
device, following sequence of
events oOccur:

(1) Device issues an

interrupt signal.
(ii) Processor finishes execution of the current
instruction before responding to the
interrupt, as indicated in Fig. 13.16.
(it) The processor tests for an interrupt, if it finds, sends an acknowledgment signal to the
requesting device. The acknowledgment allows the device to remove its interrupt
signal.
(iv) Processor transfers the control to the interrupt routine after
the currently executing program in the
saving the information of
register called program status word (PSW) and
the address of the next instruction to be executed
counter) onto a stack.
(i.e., the content of program
(iv) Processor executes the interrupt service routine.
(v) When interrupt processing is complete, the saved information
retrieved from the
are
stack and restored to the appropriate registers. Now the
normal execution resumes.
Illustration with example

Consider a task that requires some computations and the result to be printed on a line printer
Let the program consists of two routines, COMPUTE and PRINT. Assume that COMPUTE produces
a set of lines of output, to be printed by the PRINT routine.
In response to the interrupt request, PRINT is the interrupt service routine. Fig. 13.17 shows,
that an interrupt request arrives during an execution of instruction i.
Program1 Program 2
COMPUTE routine PRINT routine

1
1

Interrupt
occurs here
i+1

M-1

gure 13.17 Transfer of control through the use of interrupts.

13.7.2 Types of interrupt
Following are the three types of interrupts occur generally :

() Hardware and software interrupts

(ii) Vectored and non-vectored interrupts
(ii) Maskable and non-maskable interrupts
When anexternal hardware initiates an interrupt by sending a signal to the particular pin of
the processor, it is referred as hardware interrupt. Software interrupts are initiated by the
program instructions. While executing a program, a software interrupt instruction is
encountered; the processor handles it like an interrupt.
The processor responds to the interrupt signal by storing the return address from the program
counter into the memory stack and then transfers the control to a service routine. The way that
the processor chooses the branch address of the service routine varies from one unit to another.
In principle, there are two methods for doing this: vectored and non- vectored. In a vectored
interrupt, the branch address is assigned to a fixed location in memory. For example, in 8085
microprocessor, RSTs are vectored interrupt. In a non-vectored interrupt, the source that
interrupts supplies the branch information to the processor. This information is called the
interrupt vector.

Some interrupt requests are required immediate response from the processor. They are
programmed as non-maskable or enable interrupts. The processor has explicitly responded to
such interrupts. Some interrupts may not be responded by the processor immediately or even
processor may reject it, such interrupts are referred as maskable or disable interrupts. For
example, in 8085 microprocessor, TRAP is a maskable interrupts and RST 7.5 - 5.5 are
non-maskable interrupts. Also, al these interupts are also fall into the category of hardware
interrupts.
 Processor > I/O
Issue read commandTOCesso
Issue read command D o somethin
Processor > 1/0 else
to 1/O interface to I/O interface

Read status Read status - - Interrupt

of I/O interface
I/O>Processor of I/O interface
I/O>
Processor

Not
ready Check Check Error
Eror status condition
status Condition

Ready
Read word I/O> Processor
Read word
1/O>Processor from I/O interface
from I/O interfac

Write word
Write word Processor > Memory
Processor > Memory
into memory
into memory

No
No Done?
Done?

Yes Yes
Next instruction
Next instruction
(b) Interrupt-initiated 1/O
/ (a) Programmed I/O