6-UARTa
6-UARTa
With STM32
N Amanquah
Why communicate serially?
• CPU word size is 32 bits, sending all of a word’s bits simultaneously has
disadvantages:
Typical SPI bus: master and three independent slaves Daisy-chained SPI bus: master and cooperative slaves
Philips
• Data rates:
• Set baud rate in register (USART_BRR)
• Can generate interrupts & errors
• Overrun – could not process data before next arrived.
• Framing error – cannot find stop bit at proper place.
• Parity error- parity is not same as indicated in setup
• Status registers e.g. (USART_ISR)
Multiple UART peripherals on STM32
Key registers
Goal:
configure as 8N1 8bits, No parity, 1 stop bit
baud rate
Overview of steps
• Turn on Clock for port
• Set ALT MODER for UART
• Set the AFRL (or H) for the Pin (alternate function register)
Fields such as
RTOEN: Receiver timeout enable
CPOL: Clock polarity (used together to set clock phase and polarity)
CPHA: Clock phase
USART baud rate register (USART_BRR)
• $27.5.4, p 716
• If oversampling by 16,
• Implies USARTDIV= fck/buad
TC: Transmission complete set when the transmission of a frame containing data is complete and if
TXE is set
RXNE: Read data register not empty (data has arrived) check for when this is 1 and read it
This bit is set when the content of the RDR shift register has been transferred to the USART_RDR register
TE bit must be set before writing the data to be transmitted to the USART_TDR
The TDR register is an interface between the internal bus and the output shift register
When TXE=1, it means TDR is empty (has been copied already to shift register)
This is a good time to write to TDR. Writing to TDR clears TXE.
After transmission by the sift register is complete (and TXE is also 1, i.e. no new data), the TC becomes 1
Reception:
When character is received, RXNE is set to 1, (i.e. content of receive shift register has been copied to RDR)
This is a good time to read from RDR. (RXNEIE interrupt also thrown)