BCS302 - Digital Design & Computer

Organization

Module 3
Basic Structure of
Computers
Functional Units
 Functional Units

Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Figure 1.1. Basic functional units of a computer.

Input unit: Cont..
• The source program/high level language program/coded
information/simply data is fed to a computer through input
devices keyboard is a most common type.
• Whenever a key is pressed, one corresponding word or
number is translated into its equivalent binary code over a
cable & fed either to memory or processor.

• Joysticks, trackballs, mouse, scanners etc are other input

devices.
 Cont..
Output unit:-
• These actually are the counterparts of input unit. Its basic
function is to send the processed results to the outside world.
• Examples:- Printer, speakers, monitor etc.

Memory unit:
• Its function into store programs and data. It is basically to two
types
1. Primary memory
2. Secondary memory
 Cont..
1. Primary memory: -
 Is the one exclusively associated with the processor and
operates at the electronics speeds programs must be stored
in this memory while they are being executed.
 The memory contains a large number of semiconductors
storage cells.
 Number of bits in each word is called word length of the
computer.
 Programs must reside in the memory during execution.
Instructions and data can be written into the memory or read
out under the control of processor
 Cont..
 To provide easy access to a word in memory, a distinct
address is associated with each word location. Addresses are
numbers that identify memory location

 The time required to access one word in called memory

access time.

 Memory which is only readable by the user and contents of

which can‘t be altered is called read only memory (ROM) it
contains operating system.
 Cont..
• Caches are the small fast RAM units, which are coupled with
the processor and are often contained on the same IC chip to
achieve high performance. Although primary storage is
essential it tends to be expensive.

2. Secondary memory: -
• Is used where large amounts of data & programs have to be
stored, particularly information that is accessed
infrequently.
• Examples: - Magnetic disks & tapes, optical disks (ie CD-
ROM‘s), floppies etc.,
 Cont..
Arithmetic logic unit (ALU):-
• Most of the computer operators are executed in ALU of the
processor like addition, subtraction, division, multiplication,
etc. the operands are brought into the ALU from memory and
stored in high speed storage elements called register.
• Then according to the instructions the operation is performed
in the required sequence.
• The control and the ALU are many times faster than other
devices connected to a computer system.
• This enables a single processor to control a number of
external devices such as key boards, displays, magnetic and
optical disks, sensors and other mechanical controllers
 Cont..
Control unit:-
• It effectively is the nerve center that sends signals to other
units and senses their states.
• The actual timing signals that govern the transfer of data
between input unit, processor, memory and output unit are
generated by the control unit.
• Operations of a computer:
 Accept information in the form of programs and data through
an input unit and store it in the memory
 Fetch the information stored in the memory, under program
control, into an ALU, where the information is processed
 Output the processed information through an output unit
 Control all activities inside the machine through a control unit
Basic Operational Concepts
 Basic Operational Concepts
• Activity in a computer is governed by instructions.
• To perform a task, an appropriate program consisting of a
list of instructions is stored in the memory.
• Individual instructions are brought from the memory into
the processor, which executes the specified operations.
• Data to be used as operands are also stored in the
memory.
 Cont..
Example:
• Add LOCA, R0
• This instruction adds the operand at memory
location LOCA, to operand in register R0 & places
the sum into register.
• This instruction requires the performance of several
steps,
1. First the instruction is fetched from the memory into
the processor.
2. The operand at LOCA is fetched and added to the
contents of R0
 Cont..
3. Finally the resulting sum is stored in the register R0

• The preceding add instruction combines a memory

access operation with an ALU Operations.
• In some other type of computers, these two types of
operations are performed by separate instructions
for performance reasons.
 Cont..
Load LOCA, R1
Add R1, R0
• Transfers between the memory and the
processor are started by sending the address
of the memory location to be accessed to the
memory unit and issuing the appropriate
control signals.
• The data are then transferred to or from the
memory.
Cont..
 Cont..
• The fig shows how memory & the processor can be
connected.
• In addition to the ALU & the control circuitry, the
processor contains a number of registers used for
several different purposes
• Instruction register (IR)
• Program counter (PC)
• General-purpose register (R0 – Rn-1)
• Memory address register (MAR)
• Memory data register (MDR)
 Cont..
The instruction register (IR):- Holds the instructions
that is currently being executed.
• Its output is available for the control circuits which
generates the timing signals that control the various
processing elements in one execution of instruction.
The program counter PC:-
This is another specialized register that keeps track of
execution of a program.
It contains the memory address of the next
instruction to be fetched and executed.
- Besides IR and PC, there are n-general purpose
registers R0 through Rn-1.
 Cont..
• The other two registers which facilitate
communication with memory are: -
1. MAR – (Memory Address Register):- It holds the
address of the location to be accessed.
2. MDR – (Memory Data Register):- It contains the
data to be written into or read out of the address
location.
Operating steps are
• 1. Programs reside in the memory & usually get
these through the Input unit.
• 2. Execution of the program starts when the PC is set
to point at the first instruction of the program.
 Cont..
• 3. Contents of PC are transferred to MAR and a Read
Control Signal is sent to the memory.
• 4. After the time required to access the memory
elapses, the address word is read out of the memory
and loaded into the MDR.
• 5. Now contents of MDR are transferred to the IR &
now the instruction is ready to be decoded and
executed.
• 6. If the instruction involves an operation by the ALU,
it is necessary to obtain the required operands.
• 7. An operand in the memory is fetched by sending
its address to MAR & Initiating a read cycle.
 Cont..
• 8. When the operand has been read from the
memory to the MDR, it is transferred from MDR to
the ALU.
• 9. After one or two such repeated cycles, the ALU
can perform the desired operation.
• 10. If the result of this operation is to be stored in
the memory, the result is sent to MDR.
• 11. Address of location where the result is stored is
sent to MAR & a write cycle is initiated.
• 12. The contents of PC are incremented so that PC
points to the next instruction that is to be executed.
 Cont..
• Normal execution of a program may be preempted
(temporarily interrupted) if some devices require urgent
servicing, to do this one device raises an Interrupt signal.

• An interrupt is a request signal from an I/O device for service

by the processor. The processor provides the requested
service by executing an appropriate interrupt service routine.

• The Diversion may change the internal stage of the processor

its state must be saved in the memory location before
interruption. When the interrupt-routine service is
completed the state of the processor is restored so that the
interrupted program may continue.
 BUS STRUCTURE
• The simplest and most common way of interconnecting
various parts of the computer.
• To achieve a reasonable speed of operation, a computer must
be organized so that all its units can handle one full word of
data at a given time.
• A group of lines that serve as a connecting port for several
devices is called a bus.
• In addition to the lines that carry the data, the bus must have
lines for address and control purpose.
• Simplest way to interconnect is to use the single bus as shown
in the Figure
Cont..
 Cont..
• Since the bus can be used for only one
transfer at a time, only two units can actively
use the bus at any given time.
• Bus control lines are used to arbitrate multiple
requests for use of one bus.
Single bus structure is
• Low cost
• Very flexible for attaching peripheral devices
 Cont..
• Multiple bus structure certainly increases, the
performance but also increases the cost significantly.

• All the interconnected devices are not of same speed

& time, leads to a bit of a problem. This is solved by
using cache registers (ie buffer registers).

• These buffers are electronic registers of small

capacity when compared to the main memory but of
comparable speed.
 Cont..
• The instructions from the processor at once
are loaded into these buffers and then the
complete transfer of data at a fast rate will
take place.
Performance
 Performance
• The most important measure of the performance of a
computer is how quickly it can execute programs.

• The speed with which a computer executes program is

affected by the design of its hardware.

• For best performance, it is necessary to design the compilers,

the machine instruction set, and the hardware in a
coordinated way.
 Cont..
• The total time required to execute the program is elapsed
time is a measure of the performance of the entire computer
system.
• It is affected by the speed of the processor, the disk and the
printer.
• The time needed to execute a instruction is called the
processor time.
• Just as the elapsed time for the execution of a program
depends on all units in a computer system, the processor time
depends on the hardware involved in the execution of
individual machine instructions.
 Cont..
• This hardware comprises the processor and the memory
which are usually connected by the bus as shown in the fig c.
 Cont..
• At the start of execution, all program instructions and the
required data are stored in the main memory.
• As the execution proceeds, instructions are fetched one by
one over the bus into the processor, and a copy is placed in
the cache later if the same instruction or data item is needed
a second time, it is read directly from the cache.
• The internal speed of performing the basic steps of instruction
processing on chip is very high and is considerably faster than
the speed at which the instruction and data can be fetched
from the main memory.
• A program will be executed faster if the movement of
instructions and data between the main memory and the
processor is minimized, which is achieved by using the cache.
 Cont..
Processor clock:
• Processor circuits are controlled by a timing signal called
clock. The clock designer the regular time intervals called
clock cycles.
• To execute a machine instruction the processor divides the
action to be performed into a sequence of basic steps that
each step can be completed in one clock cycle.
• The length P of one clock cycle is an important parameter that
affects the processor performance.
• Processor used in today‘s personal computer and work station
have a clock rates that range from a few hundred million to
over a billion cycles per second.
 Basic performance equation
 We now focus our attention on the processor time
component of the total elapsed time.
 Let ‘T‘ be the processor time required to execute a program
that has been prepared in some high-level language.
 The compiler generates a machine language object program
that corresponds to the source program. Assume that
complete execution of the program requires the execution of
‘N’ machine cycle language instructions.
 The number N is the actual number of instruction execution
and is not necessarily equal to the number of machine cycle
instructions in the object program.
 Cont..
 Suppose that the average number of basic steps needed to
execute one machine cycle instruction is S, where each basic
step is completed in one clock cycle. If clock rate is ‘R‘ cycles
per second, the program execution time is given by

N S
T 
R
This is often referred to as the basic performance equation.

We must emphasize that N, S & R are not independent

parameters changing one may affect another
 Cont..
 Introducing a new feature in the design of a processor will
lead to improved performance only if the overall result is to
reduce the value of T.
Pipeline and Superscalar Operation
• We assume that instructions are executed one after
the other. Hence the value of S is the total number of
basic steps, or clock cycles, required to execute one
instruction.
• A substantial improvement in performance can be
achieved by overlapping the execution of successive
instructions using a technique called pipelining.
• Consider
Add R1 R2 R3
• This adds the contents of R1 & R2 and places the
sum into R3.
 Cont..
• The processor can read the next instruction from the
memory, while the addition operation is being
performed.
• Then of that instruction also uses, the ALU, its
operand can be transferred to the ALU inputs at the
same time that the add instructions is being
transferred to R3.
• A higher degree of concurrency can be achieved if
multiple instructions pipelines are implemented in
the processor.
Pipelining-Example
Without Pipelining-Example
With Pipelining-Example
 Cont..
• This means that multiple functional units are used
creating parallel paths through which different
instructions can be executed in parallel with such an
arrangement, it becomes possible to start the
execution of several instructions in every clock cycle.
This mode of operation is called superscalar
execution.
• If it can be sustained for a long time during program
execution the effective value of S can be reduced to
less than one.
 Cont..
• But the parallel execution must preserve logical
correctness of programs, that is the results produced
must be same as those produced by the serial
execution of program instructions.
• Now a days may processor are designed in this
manner.
 Clock Rate
These are two possibilities for increasing the clock rate ‘R‘.

1. Improve the integrated-circuit (IC) technology to make the

circuits faster
2. Reduce the amount of processing done in one basic step
(however, this may increase the number of basic steps needed)

• Increases in R that are entirely caused by improvements in IC

technology affect all aspects of the processor’s operation
equally except the time to access the main memory.
• In the presence of cache the percentage of accesses to the main
memory is small. Hence much of the performance gain
expected from the use of faster technology can be realized.
 Cont..
CISC and RISC:
• Tradeoff between N and S
• A key consideration is the use of pipelining
 S is close to 1 even though the number of basic steps per
instruction may be considerably larger
 It is much easier to implement efficient pipelining in processor
with simple instruction sets
• Reduced Instruction Set Computers (RISC)
• Complex Instruction Set Computers (CISC)
 Cont..
• Reduced Instruction Set Architecture (RISC) –
The main idea behind this is to make hardware simpler by
using an instruction set composed of a few basic steps for
loading, evaluating, and storing operations just like a load
command will load data, a store command will store the data.

• Complex Instruction Set Architecture (CISC) –

The main idea is that a single instruction will do all loading,
evaluating, and storing operations just like a multiplication
command will do stuff like loading data, evaluating, and
storing it, hence it’s complex.
Cont..
Cont..
 Performance measurements
 Inspite of the performance equation being so simple, the
evaluation of ‘T‘ is highly complex.
 Moreover the parameters like the clock speed and various
architectural features are not reliable indicators of the
expected performance.
 Hence measurement of computer performance using bench
mark programs is done to make comparisons possible,
standardized programs must be used.
• A non profit organization called SPEC- System Performance
Evaluation Corporation selects and publishes bench marks.
• The program selected range from game playing, compiler, and
data base applications to numerically intensive programs in
astrophysics and quantum chemistry
 Cont..
The ‘SPEC‘ rating is computed as follows.

Running time on the reference computer

SPEC rating 
Running time on the computer under test
n 1
SPEC rating  ( SPECi ) n

i 1
Ex:
If the SPEC rating = 50 , means that the computer under test is 50 times as fast
as the ultra sparc 10.
This is repeated for all the programs in the SPEC suit, and the geometric mean
of the result is computed.
Since actual execution time is measured the SPEC rating is a measure of the
combined effect of all factors affecting performance, including the compiler, the
OS, the processor, the memory of comp being tested.
 Multiprocessors and Multicomputers
• Multiprocessor computer
 Execute a number of different application tasks in parallel
 Execute subtasks of a single large task in parallel
 All processors have access to all of the memory – shared-memory
multiprocessor
 Cost – processors, memory units, complex interconnection networks
• Multicomputers
 Each computer only have access to its own memory
 Exchange message via a communication network – message-passing
multicomputers
Chapter 2. Machine
Instructions and
Programs
Memory Locations,
Addresses, and
Operations
 Memory Location, Addresses, and
Operation
n bits
first word
• Memory consists of
second word
many millions of
storage cells, each
•
of which can store 1 •
bit. •

• Data is usually i th word

accessed in n-bit
groups. n is called •
word length. •
•

last word

Figure 2.5. Memory words.

 Memory Location, Addresses, and
Operation
• 32-bit word length example
32 bits

b31 b30 b1 b0

•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location, Addresses, and
Operation
• To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location are
needed.
• A k-bit address memory has 2k memory locations, namely
0 – 2k-1, called memory space.
• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
• 32-bit memory: 232 = 4G (1G=230)
• 1K(kilo)=210
• 1T(tera)=240
Memory Location, Addresses, and
Operation
• It is impractical to assign distinct addresses to
individual bit locations in the memory.
• The most practical assignment is to have
successive addresses refer to successive byte
locations in the memory – byte-addressable
memory.
• Byte locations have addresses 0, 1, 2, … If word
length is 32 bits, they successive words are
located at addresses 0, 4, 8,…
 Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing.

 Memory Location, Addresses, and
Operation
• Address ordering of bytes
• Word alignment
– Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
• 16-bit word: word addresses: 0, 2, 4,….
• 32-bit word: word addresses: 0, 4, 8,….
• 64-bit word: word addresses: 0, 8,16,….
• Access numbers, characters, and character
strings
 Memory Operation

• Load (or Read or Fetch)

 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
• Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used
 Instruction and
Instruction Sequencing
 “Must-Perform” Operations

• Data transfers between the memory and the

processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers
 Register Transfer Notation

• Identify a location by a symbolic name

standing for its hardware binary address (LOC,
R0,…)
• Contents of a location are denoted by placing
square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
• Register Transfer Notation (RTN)
 Assembly Language Notation

• Represent machine instructions and

programs.
• Move LOC, R1 = R1←[LOC]
• Add R1, R2, R3 = R3 ←[R1]+[R2]
 CPU Organization
• Single Accumulator
– Result usually goes to the Accumulator
– Accumulator has to be saved to memory quite often
• General Register
– Registers hold operands thus reduce memory traffic
– Register bookkeeping
• Stack
– Operands and result are always in the stack
 Instruction Formats
• Three-Address Instructions
– ADD R1, R2, R3 R3 ← R1 + R2
• Two-Address Instructions
– ADD R1, R2 R ← R1 + R2
• One-Address Instructions
– ADD M AC ← AC + M[AR]
• Zero-Address Instructions
– ADD TOS ← TOS + (TOS – 1)
• RISC Instructions
– Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

 Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Two-Address
1. MOV A, R1 ; R1 ← M[A]
2. ADD B, R1 ; R1 ← R1 + M[B]
3. MOV C, R2 ; R2 ← M[C]
4. ADD D, R2 ; R2 ← R2 + M[D]
5. MUL R2, R1 ; R1 ← R1 R2
6. MOV C, R1 ; M[C] ← R1
 Instruction Formats
Example: Evaluate (A+B)  (C+D)
• One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
 Instruction Formats
Example: Evaluate (A+B)  (C+D)
• RISC
1. LOAD A, R1 ; R1 ← M[A]
2. LOAD B, R2 ; R2 ← M[B]
3. LOAD C,R3 ; R3 ← M[C]
4. LOAD D, R4 ; R4 ← M[D]
5. ADD R1, R2, R1 ; R1 ← R1 + R2
6. ADD R3, R4, R3 ; R3 ← R3 + R4
7. MUL R1, R3, R1 ; R1 ← R1  R3
8. STORE R1, X ; M[X] ← R1
 Using Registers

• Registers are faster

• Shorter instructions
– The number of registers is smaller (e.g. 32
registers need 5 bits)
• Potential speedup
• Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.
 Instruction Execution and Straight-
Line Sequencing
Address Contents

i
Assumptions:
Begin execution here Move A,R0
i+4
3-instruction
program
- One memory operand
Add B,R0
segment per instruction
i+8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
-Instruction fetch
C -Instruction execute

Figure 2.8. A program for C  [A] + [B].

• PC –Program counter: hold the address of the next
instruction to be executed
• Straight line sequencing: If fetching and executing of
instructions is carried out one by one from successive
addresses of memory, it is called straight line
sequencing.
•Major two phase of instruction execution
• Instruction fetch phase: Instruction is fetched form
memory and is placed in instruction register IR
• Instruction execute phase: Contents of IR is decoded
and processor carries out the operation either by
reading data from memory or registers.
BRANCHING
• Branch instruction are those which changes the
normal sequence of execution.
– Sequence can be changed either conditionally or
unconditionally.
– Accordingly we have conditional branch instructions
and unconditional branch instruction.
• Conditional branch instruction changes the sequence
only when certain conditions are met.
• Unconditional branch instruction changes the
sequence of execution irrespective of condition of the
results.
 i Move NUM1,R0

Branching i+4
i+8
Add
Add
NUM2,R0
NUM3,R0

•
•
•
i + 4n - 4 Add NUMn,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUMn

Figure 2.9. A straight-line program for adding n numbers.

 Move N,R1

Branching LOOP
Clear R0

Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM

Conditional branch
•
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUMn
 Condition Codes
• CONDITIONAL CODE FLAGS: The processor keeps track of
information about the results of various operations for use by
subsequent conditional branch instructions
– N –Negative 1 if results are Negative
– 0 if results are Positive
– Z –Zero 1 if results are Zero
– 0 if results are Non zero
– V –Overflow 1 if arithmetic overflow occurs
– 0 non overflow occurs
– C –Carry 1 if carry and from MSB bit
– 0 if there is no carry from MSB bit
 Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check
Addressing Modes
 Generating Memory Addresses

• How to specify the address of branch target?

• Can we give the memory operand address
directly in a single Add instruction in the loop?
• Use a register to hold the address of NUM1;
then increment by 4 on each pass through the
loop.
 Addressing Modes

Opcode Mode ...

• Immediate
– The use of a constant in “MOV #5, R1”, i.e. R1 ← 5
• Register
– Indicate which register holds the operand
 Addressing Modes
• Register Indirect
– Indicate the register that holds the number of the
register that holds the operand R1
MOV (R2), R1
R2 = 3
• Autoincrement / Autodecrement
– Access & update in 1 instr. R3 = 5

• Direct Address
– Use the given address to access a memory location
 Addressing Modes
• Indirect Address
– Indicate the memory location that holds the
address of the memory location that holds the
data
AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A
 Addressing Modes

• Relative Address
0
– EA = PC + Relative Addr 1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
Could be Positive or 103
Negative 104
(2’s Complement)
 Addressing Modes
• Indexed
– EA = Index Register + Relative Addr

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive or
Negative 102 1 1 0 A
(2’s Complement) 103
104
 Addressing Modes
• Base Register
– EA = Base Register + Relative Addr

Could be Positive or AR = 2
Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array
 Addressing Modes
Name Assembler syntax Addressingfunction
• The different
ways in which Immediate #Value Op erand = Value
the location of
an operand is Register Ri EA = Ri
specified in an Absolute(Direct) LOC EA = LOC
instruction are
referred to as Indirect (Ri ) EA = [Ri ]
addressing (LOC) EA = [LOC]
modes.
Index X(R i) EA = [Ri ] + X

Basewith index (Ri ,Rj ) EA = [Ri ] + [Rj ]

Basewith index X(R i,Rj ) EA = [Ri ] + [Rj ] + X
and offset

Relative X(PC) EA = [PC] + X

Autoincrement (Ri )+ EA = [Ri ] ;

Increment Ri

Autodecrement  (Ri ) Decrement Ri ;

EA = [Ri]
 Indexing and Arrays
• Index mode – the effective address of the operand is
generated by adding a constant value to the contents of a
register.
• Index register
• X(Ri): EA = X + [Ri]
• The constant X may be given either as an explicit number
or as a symbolic name representing a numerical value.
• If X is shorter than a word, sign-extension is needed.
 Indexing and Arrays

• In general, the Index mode facilitates access to

an operand whose location is defined relative
to a reference point within the data structure
in which the operand appears.
• Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]
 Relative Addressing
• Relative mode – the effective address is determined by
the Index mode using the program counter in place of
the general-purpose register.
• X(PC) – note that X is a signed number
• Branch>0 LOOP
• This location is computed by specifying it as an offset
from the current value of PC.
• Branch target may be either before or after the branch
instruction, the offset is given as a singed num.
 Additional Modes
• Autoincrement mode – the effective address of the operand is the
contents of a register specified in the instruction. After accessing the
operand, the contents of this register are automatically incremented to
point to the next item in a list.
• (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit operands,
and 4 for 32-bit operands.
• Autodecrement mode: -(Ri) – decrement first
Move N,R1
Move #NUM1,R2 Initialization
Clear R0
LOOP Add (R2)+,R0
Decrement R1
Branch>0 LOOP
Move R0,SUM

Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.