Modeling and Simulation of Shipboard Power

System Protection Schemes Using Coordination

of Overcurrent Relay
Ankush Saran, Student Member, IEEE, Anurag K. Srivastava, Member, IEEE and Noel N. Schulz,
Senior Member, IEEE

Genetic Algorithm method of relay coordination [6], and

Abstract-- Combining the modeling and simulation of power systems other intelligent automatic coordination of relays [7, 8].
and control systems is a challenge. Several packages allow the Most of the coordination schemes were developed based on the
optimization of either the power system functionality or the control two different domains of the power and control systems. With
system functionality. Research efforts are underway at Mississippi the advancement in digital technology, signal processing and
State University to model the protection functionality of computing power, it is possible to do integrated modeling,
microprocessor controlled relays to allow the integration of the
design, simulation and analysis of power and control systems.
protection system and power system models for advanced
optimization and simulation analysis related to shipboard power Coordination schemes deigned with integrated modeling and
systems (SPS). This paper presents a detailed overview of the simulation will give better performance. The first step for that
overcurrent relay model and procedures used to conduct closed loop will be modeling a relay considering all its parameters and
coordination testing of relays using a real time digital simulator characteristics. The second step will be to demonstrate he
(RTDS). The coordination of a relay is a useful concept, which is requirement of relay coordination and model that
used widely in the protection of a power system. This paper mainly characteristics for different test scenarios.
focuses on the coordination of overcurrent relays in order to protect Research efforts at Mississippi State University are
the SPS after severe disturbances. working in direction of designing integrated adaptive relay. A
Index Terms- RTDS, Shipboard Power System (SPS), real time simple relay model has been developed and hardware in the
simulation, overcurrent relay.
loop platforms were developed to validate the developed model
[9-11]. In this work, the relay model has been developed and
I. INTRODUCTION integrated with the power system model. Test cases have been
developed to demonstrate coordination of two software relay
Real time protective relay coordination is an effective and widely models using the RTDS.
used technique which has been used from decades by power RTDS is an effective tool for the simulations of small as
system utilities in order to protect the system [1,2]. The concept well as large power systems developed in RSCAD. RTDS
of relay coordination is not new but it has been modified with the employs high-speed DSP (digital signal processor) chips to
advancement in technologies for the power industry [3]. Initially, compute simulations results with simulation step sizes as small
the relay coordination was done by carrying out manual as two microseconds. RSCAD is the Graphical User Interface
calculations for relay settings. With development of computer (GUI) software that has power system and control system
aided methods for relay coordination it has become easier to libraries that enables development of the power system and
assess the impact of a fault on the system and setting the relay different control logics to be simulated on the RTDS. The SEL
parameters with proper coordination to protect the system from 351S is a directional overcurrent relay, which generates an
different types of contingencies. Many methods were adopted for automatic trip and reclose signal. In this paper two software
the relay coordination like GAMS (General Algebraic Modeling models of SEL 351 relays were developed by keeping the
Systems) technology [4], computer aided relay coordination [5], functionality of overcurrent relay in the RSCAD software [12].
A software model of the 4-bus Shipboard Power System (SPS)
has been integrated with control logic like fault inception logic,
This work is supported by the ONR Funds Grant No. N00014-08-1-0080and
N00014-06-1-0752.
breaker logic, sampling logic as well as SEL 351 overcurrent
The authors are with Department of Electrical and Computer Engineering, relay model developed in the RSCAD.
Mississippi State University, Mississippi State, MS 39762. The SEL 351 overcurrent relay has a basic principle to
([email protected], 662-325-5838) generate a trip signal upon the occurrence of fault in the

978-1-4244-3439-8/09/$25.00 ©2009 IEEE 282

system in order to open the breaker when the current exceeds the 3PC, GPC and RPC. 3PC is the Triple Processor Card which
pickup value of current and it recloses the breaker when the fault includes three independent Analog Digital Signal Processor
is cleared. The two software models of SEL 351 overcurrent (ADSP21062) having a clock speed of 40 MHz. RPC is
relays were developed in RSCAD in order to achieve the relay referred as RISC Processor card which consists of two
coordination. Simulations results were obtained using Real Time PowerPC 750Cxe RISC processors operating at a clock speed
Digital Simulator (RTDS) under different line to ground fault of 600 MHz. The Giga Processor Card is abbreviated as GPC
conditions to observe the system behavior. The system is which combines two IBM PowerPC 750GX RISC processors
simulated on the RTDS for 1.7 second for the three phase to each operating at 1 GHz. The RTDS simulators are available
ground (L-L-L-G) fault. The results obtained by the simulation in different configurations having only 3PC or a combination
are analyzed and the relay coordination in SPS system is verified. of the 3PC, GPC and RPC cards in it.
The Graphical User Interface known as RSCAD is used
II. MODELING AND REAL TIME SIMULATION IN RTDS to construct, run and analyze the simulation test cases.
RSCAD allows the user to build a test case by using the
RTDS is a real time digital simulator which is used for the different power and control system components present in the
simulation of large power system in real time. It is an effective RSCAD library.
and efficient real time tool for the designing, testing and
development of small and large power system to analyze the III. POWER SYSTEM TEST CASE
system under different fault conditions. The systems simulated
A. Test Case in RSCAD
on the RTDS are developed in user friendly software called as
RSCAD, which is a Graphical User interface (GUI) with the Shipboard power system test case taken here consists of
RTDS. The RSCAD software consists of control as well as four buses for conducting the relay coordination test. The
power system component libraries, which enables the user to main components of Shipboard bus system are
develop small as well as large power systems. Figure 1 shows
the RTDS at the Mississippi State University Power and Energy • Two generators of 36 MVA
Research Laboratory (MSU PERL). • Two generators of 4 MVA
• Two 4.16 kV, 60Hz induction motor loads.
• Current transformer, potential transformer and
breakers.
• Gas turbine with governor mechanism and
frequency of 60Hz.

The Shipboard Power System (SPS) was developed in

RSCAD software and simulated on RTDS. The test system
consists of two parallel cable (cable1 and cable2). There are
four generators (NE, NW, SE and SW generators) where NW
and SE generators have a rating of 36 MVA while SW and
NE generators are having a rating of 4MVA. The SPS system
consists of 4 breakers (namely BRK1, BRK2, BRK3 and
BRK4), current transformers (CT1 and CT2) and potential
transformers (PT1 and PT2). BRK1 and BRK2 are located on
the cable 1 while BRK3 and BRK4 are present on the cable 2.
The current transformer and potential transformer are
modeled in detail to reflect real system characteristics. The
relay coordination is performed on cable 1 where the BRK1
Fig 1. Real Time Digital Simulator at MSU and BRK2 are coordinated for different types of line-to-
ground faults. The line to ground faults are applied on bus 1.
RTDS is a complex machine and its hardware is based on Fig. 2 shows the shipboard power system built in RSCAD.
Digital Signal Processor (DSP) and Reduced Instruction Set The CT ratio of the current transformer (CT1) is 300:1 and
Computer (RISC), and utilizes advanced parallel processing the CT ratio of current transformer (CT2) is 200:1. At no fault
techniques which provide faster computational speeds required condition normal RMS currents are flowing in to the CT1 and
to maintain continuous operation in real-time. One rack of the CT2 having values of 156A and 206A while the current
RTDS consists of three types of processor cards. These are coming out of the CT1 and CT2 is 156/300= 0.52 A and

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206/200= 1.03A. Line to ground faults are applied on the bus 1 IV. CONTROL LOGIC
of the SPS system. At no fault condition there is no disturbance
in the currents. The pick up value of the current for the two Different types of control logics like fault control logic,
breakers to generate trip signal should be at least 1.5 times of the analog signal sampling logic, fault locator and breaker control
normal RMS current. The RMS value of current under no fault logic were developed in the RSCAD software. Fault logic is
condition coming out of the CT1 is 0.54A, so the pickup value of necessary to simulate a fault on the specific location in the cable
current is set at 0.90 A (greater then the 1.5 times of 0.54 A) of the shipboard power system.
while the RMS value of current coming out of CT2 is 0.78 A, so
the pickup value of current to generate trip signal in BRK2 is set The analog signal sampling logic is to measure the RMS value of
as 1.20A (which is also greater then the 1.5 times of the 0.78 A). current coming out of the current transformer while the BRK
The power system is compiled and simulated on the RTDS. open and reclose logics are developed in order to open and
During the no-fault condition, the normal current flows in to the reclose the breakers in a coordinated manner. These control logic
system. Fig. 3 shows the normal burden current entering in to the functions are explained below in detail.
each phase of current transformers.

Fig 2. Test Case: Shipboard (4-Bus) Power System

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 Fig. 3: No-Fault condition in RTDS

A. Fault Control Logic

The fault inception control logic was developed in RSCAD.
The fault logic is used to place the line to ground faults on bus
1 on the cable 1 of the shipboard power system. The fault
inception logic consists of 2 parts: fault inception point and
type of fault. The fault inception point logic is used to decide
the duration of the fault and it also determines the point of the
wave at which the fault should be applied. When the fault
button is pressed then a pulse of 20 millisecond is produced,
which is longer than the one cycle at 60Hz. The pulse is
generated by the AND gate and then combined with the zero
crossing. The pulse derives the point on wave logic, which
consists of a gain block, slider and pulse duration timer. Figure 3: Fault control logic
The second part of the logic is used to decide the type of
fault to be applied. Switches are created in the logic to put The root mean square value will be calculated using two
different type of faults, which generates an integer value. The sampling techniques and the equation (1) calculates the
pulse generated in the first part is integrated with an integer magnitude of input signal using this technique.
value to generate a pulse, which reflects the specific type of
fault. Fig.3. shows the complete fault control logic.

B. Analog Signal Sampler

Analog Signal Sampler is used to calculate the root mean
Equation 1 introduces the two-sample technique for
square (RMS) value of the current which is flowing in the
determining the magnitude of a signal from sampled data
three phase line of the power system. The analog signals
taken at discrete intervals. In this model, sampling is done
should be sampled at a rate equal to the protection cycle time
at a constant rate. Therefore the numerator and
for the digital relays. In the sampler logic, the analog signal is
denominator containing the terms cos, sin, Δt and w can be
up sampled at a rate of 5.76 kHz or 96 samples per cycle for a
computed. A single state buffer is used to get the present
60Hz base. The signal is down sampled at a rate of 480 Hz or
and previous sampled data. The sampled data is squared
8 times per cycle as the protection cycle is set to 8 times per
and summed together completing the first part of the
cycle.
numerator in the equation 1. The analog signal sampler is
used to calculate the RMS current coming out of the
current transformer.

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C. Fault Locator The circuit breaker 1 (BRK1) and 2 (BRK2) control logic
Fig. 4 shows the fault locator logic designed in RSCAD, models were built in RSCAD software in order to open and
which is used to specify the location of the fault on the cable reclose the breaker for different types of line to ground
of the SPS system. The workings of this logic are quite simple faults. The actions of breaker logic are when the
and based on the comparison of the existing fault location with measured/calculated RMS current is greater than the
a predefined location on the cable. The logic block “Len” is specified pick up value, the IF THEN ELSE block output
the predefined cable length which is set at 50% of the cable will be 1. The type of fault is checked by the second IF
length while the other logic FLOC is the existing variable fault THEN ELSE block, if the fault applied is phase to ground
location. The Len block is compared with the FLOC block and then the output will be 1. These two outputs forms an input
gives the output signal “P” and “Q”. The signal “P” is to the AND gate. A trip signal to the BRK1 and BRK2 are
generated when the fault is at = < 50% of the cable while “Q” send out if the output of the AND gate is high.
signal is generated when the fault is located at > 50% of the The main task of the breaker control logic is to
cable length. The signals “P” and “Q” are given to the breaker coordinate between the two breakers present on the cable1.
open and reclose logics in order to coordinate them depending The output of the fault locator, which is P and Q signals,
upon the fault location. are used to decide which breaker should open first and
which breaker should open later in order to achieve the
coordination of the breakers. In other words, if the output
of the fault locator is P (which means the fault is at =<50%
of the cable) then the BRK1 should open first to protect
one part of the system and to protect the other part of the
system BRK2 should also open after BRK1 but after a
delay of few cycles. Now, if the fault is cleared then the
BRK1 recloses and the BRK2 should also reclose after a
delay of few cycles from BRK1. In a similar way, if the
Fig.4. Fault Locator Logic fault locator logic generates Q (which means the fault is at
D. Breaker Control Logic >50% of the cable length) then the BRK2 should open first
and then the BRK 1 should open after a delay of few
The breaker logic was developed in RSCAD in order to open cycles. Now if the fault is cleared then the BRK2 is
and reclose during different types of line to ground fault. reclosed first and then the BRK1 should be reclosed after
some delay.

Fig.5. Simulation Result of L-L-L-G Fault at 20% of the Cable length

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 Fig.6. Simulation Result of L-L-L-G Fault at 50% of the Cable length

Fig.7. Simulation Result of L-L-L-G Fault at 80% of the Cable 1 length

then software model of overcurrent relay sends a trip

V. PROTECTIVE RELAY COORDINATION signal to BRK1 to open it first and then the BRK2 is
coordinated with BRK1 with some delay by using the
A. Basic operation of relay coordination in SPS system other software relay model. After the fault is cleared, the
In the shipboard system, two software models of an BRK1 recloses first and then the BRK2 is reclosed after
overcurrent relay were developed in RSCAD software to be some delay after getting the reclose signals from the
simulated on RTDS in order to conduct the coordination of software relay models. On the other hand, if the fault is at
relay test. In this technique when the fault is present at a the length > 50% of the cable length then BRK2 opens up
specific location on the cable then only a specific relay will first by getting the trip signal from the software model of
operate and acts as a main relay while the other relay will be overcurrent relay and then the BRK1 is coordinated with
coordinated with the main relay with some time delay and acts BRK2 with some delay in order to protect the system from
as backup relays. heavy damages. But if the fault is cleared then the BRK2
The basic principle of relay coordination in SPS system is and BRK1 both are reclosed.
when the fault is at the length = < 50% of the cable length
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B. How the BRK1 and BRK2 are coordinated Table 1 shows the time in seconds for different signals
Let’s assume that the fault is at a length =<50% of the cable. generated during the coordination of relays for three-phase
In this case the BRK1 is opened and reclosed first followed by to ground fault at different fault locations.
the BRK2 opening and reclosing with some delay. Now at a
fault condition the current exceeds the threshold current and a As shown in the figures and table that integrated
fault signal is generated. The software overcurrent relay modeling and simulation was done to coordinate the time
model senses the fault and gives a trip cycle after one cycle delay characteristics of relay successfully. Research
(16.67 ms) to open BRK1. The breaker opens after 3 cycles presented here demonstrates the modeling and simulation
from the trip signal. Now, if the fault is cleared then the relay capabilities with developed relay model. These developed
generates a reclose signal after 65 cycles from the breaker relay model will be extended to hardware prototype and
opening to reclose the BRK1. After getting the reclose signal operation of multiple commercial relays with hardware-in-
BRK 1 recloses after 3 cycles. But if the fault is not cleared, the-loop platform in future.
BRK 1 goes to lockout stage.
VI. SUMMARY
C. Simulation Results of Relay coordination on SPS system
This paper presents an integrated modeling and
The SPS system is simulated on the RTDS for 1.7 seconds for simulation for coordination of relay software model using
different types of line to ground faults and the relay the RTDS for the shipboard power system. Control logic to
coordination is observed. The simulation results for the three design relay model and to perform integrated simulation
phase to ground fault (L-L-L-G) are presented here for have been discussed. The 4-bus SPS system has been used
different fault location like: at 20% of the cable, at 50% of the as a test case. Simulations results are presented for three
cable and at 80% of the cable. phase fault at different locations within the cable in SPS.
i) Fault at 20% of the Cable length The results obtained are analyzed verifying that the
When the fault is present at the 20% of the cable length software models of relays are coordinating properly for the
then BRK1 opens first and then BRK2 opens after some delay. SPS system. Extending developed relay model in hardware
After fault clearing, BRK1 is reclosed after getting reclose prototype and performing hardware in the loop simulation
signal from the software relay model and the BRK2 is also for relay coordination using commercial relay will be part
reclosed after a delay of few cycles. Fig. 5 shows the of the future work. By combining the protection and
simulation results for the SPS system put under three phase to power system within one simulation environment,
ground fault at 20% of the cable. researchers can develop innovative operational solutions.

ii) Fault at 50% of the Cable length VII. ACKNOWLEDGEMENTS

In this case when the fault is at 50% of the cable then either Authors acknowledge ONR Funds N00014-08-1-0080,
of the breakers (BK1 or BRK2) can operate first and the other and DOD DURIP fund N00014-06-1-0752, for supporting
breaker will be coordinated with first operating breaker. Here, this research work. Authors are also appreciative of
BRK1 will operate first and the BRK2 will operate later. Fig. 6 researchers at the Center for Advanced Power Systems at
shows the simulation result for the L-L-L-G fault at 50% of Florida State University for providing the specifications of
the cable. the SPS system. Authors are also thankful to Chenfeng
Zhang and Padmavathy Kankanala for helping with some
TABLE 1: TIME STATISTICS FOR RELAY COORDINATION of the work presented here.
Signal Names FAULT FAULT at FAULT at
at 20% of 50% of 80% of
VIII. REFERENCES
the Cable the Cable the Cable
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TRIP1 0.3894 0.3894 0.4057
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BREAKER 1 OPEN 0.4376 0.4376 0.4600 coordination studies”, 57th Annual Conference on Protective Relay
BREAKER 2 OPEN 0.4651 0.4651 0.4374 Engineers, 30 Mar-1 Apr 2004, pp. 220 – 246.
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[5] V. V. Bapeswara Rao and K. Sankara Rao, “Computer aided
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IX. BIOGRAPHIES
Ankush Saran is pursuing his Master’s degree at Mississippi State University
in the Electrical and Computer Engineering Department and he received his
Bachelor of Engineering (B.E) degree from Vaish College of Engineering,
Haryana, India in 2007. He is a member of IEEE and his research interest
includes protection, security, simulation and modeling of power system.

Anurag K. Srivastava received his Ph.D. degree from Illinois Institute of

Technology (IIT), Chicago, in 2005, M. Tech. from Institute of Technology,
India in 1999 and B. Tech. in Electrical Engineering from Harcourt Butler
Technological Institute, India in 1997. He is working as Assistant Research
Professor at Mississippi State University since September 2005. Before that,
he worked as Research Assistant and Teaching Assistant at IIT, Chicago, USA
and as Senior Research Associate at Electrical Engineering Department at the
Indian Institute of Technology, Kanpur, India as well as Research Fellow at
Asian Institute of Technology, Bangkok, Thailand. His research interest
includes real time simulation, power system modeling, power system security,
power system deregulation and artificial intelligent application in power
system. Dr. Srivastava is member of IEEE, IET, Power and Energy Society,
Sigma Xi, ASEE and Eta Kappa Nu. He is recipient of several awards and
serves as reviewer for IEEE Transactions, international journals and
conferences.

Noel N. Schulz received her B.S.E.E. and M.S.E.E. degrees from Virginia
Polytechnic Institute and State University in 1988 and 1990, respectively. She
received her Ph.D. in EE from the University of Minnesota in 1995. She has
been a professor in the ECE department at Mississippi State University since
July 2001. She is currently the TVA Endowed Professor in power systems
engineering. Her research interests are in computer applications in power
system operations including artificial intelligence techniques. She is a NSF
CAREER award recipient. She has been active in the IEEE Power & Energy
Society and served as Secretary for 2004-2007 and Treasurer for 2008-2009.
She was the 2002 recipient of the IEEE/PES Walter Fee Outstanding Young
Power Engineer Award. Dr. Schulz is a member of Eta Kappa Nu and Tau
Beta Pi.

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