W3 Working Principles of Microprocessor and Implementation of Interrupts
W3 Working Principles of Microprocessor and Implementation of Interrupts
Objectives:
At the end of the lesson the learner will be able to:
Define microprocessor
Describe the working principles of microprocessor
Define Interrupts
What is a Microprocessor?
Advantages of a Microprocessor
Low Cost
Microprocessors are available at low cost due to integrated circuit technology.
Which will reduce the cost of a computer system.
High Speed
Microprocessor chips can work at very high speed due to the technology
involved in it. It is capable of executing millions of instructions per second.
Small Size
Due to very large scale and ultra large scale integration technology, a
microprocessor is fabricated in a very less footprint. This will reduce the size of
the entire computer system.
Versatile
Microprocessors are very versatile, the same chip can be used for a number of
applications by simply changing the program (instructions stored in the
memory).
Here are some common terms that we will use in microprocessor field.
Bus
Instruction Set
Word Length
Word Length is the number of bits in the internal data bus of a processor or it is the
number of bits a processor can process at a time. For eg. An 8-bit processor will have
an 8-bit data bus, 8-bit registers and will do 8-bit processing at a time. For doing higher
bits (32-bit, 16-bit) operations, it will split that into a series of 8-bit operations.
Cache Memory
Cache memory is a random access memory that is integrated into the processor. So the
processor can access data in the cache memory more quickly than from a regular RAM.
It is also known as CPU Memory. Cache memory is used to store data or instructions
that are frequently referenced by the software or program during the operation. So it
will increase the overall speed of the operation.
Clock Speed
Microprocessors uses a clock signal to control the rate at which instructions are
executed, synchronize other internal components and to control the data transfer
between them. So clock speed refers to the speed at which a microprocessor executes
Classification of Microprocessors
Hope you read about word length above. So based on the word length of a processor
we can have 8-bit, 16-bit, 32-bit and 64-bit processors.
RISC is a type of microprocessor architecture which uses small, general purpose and
highly optimized instruction set rather than more specialized set of instructions found
in others. RISC offers high performance over its opposing architecture CISC (see
below). In a processor, execution of each instruction require a special circuit to load
and process the data. So by reducing instructions, the processor will be using simple
circuits and faster in operation.
CISC is the opposing microprocessor architecture for RISC. It is made to reduce the
number of instructions per program, ignoring the number of cycles per instruction. So
complex instructions are directly made into hardware making the processor complex
and slower in operation.
This architecture is actually designed to reduce the cost of memory by reducing the
program length.
There are some processors which are designed to handle some specific functions.
IMPLEMENTATION OF INTERRUPTS
TYPES
Interrupt signals may be issued in response to hardware or software events. These are
classified as hardware interrupts or software interrupts, respectively. For any
particular processor, the number of hardware interrupts is limited by the number of
interrupt request (IRQ) signals to the processor, whereas the number of software
interrupts is determined by the processor design.
7|Page Computer Architecture and Organization
WEEK 3: Working Principles of Microprocessor and Implementation of Interrupts
Hardware interrupts
A hardware interrupt request (IRQ) is an electronic signal issued by an external (to the
processor) hardware device, to communicate that it needs attention from the operating
system (OS) or, if there is no OS, from the "bare-metal" program running on the CPU.
Such external devices may be part of the computer (e.g., disk controller) or they may
be external peripherals. For example, pressing a keyboard key or moving
the mouse triggers hardware interrupts that cause the processor to read the keystroke
or mouse position.
Unlike software interrupts, hardware interrupts can arrive asynchronously with
respect to the processor clock, and at any time during instruction execution.
Consequently, all hardware interrupt signals are conditioned by synchronizing them
to the processor clock, and acted upon only at instruction execution boundaries.
In many systems, each device is associated with a particular IRQ signal. This makes it
possible to quickly determine which hardware device is requesting service, and to
expedite servicing of that device.
Masking
Processors typically have an internal interrupt mask register which allows selective
enabling and disabling of hardware interrupts. Each interrupt signal is associated with
a bit in the mask register; the interrupt is enabled when the bit is set and disabled
when the bit is clear, or vice versa. When the interrupt is disabled, the associated
interrupt signal will be ignored by the processor. Signals which are affected by the
mask are called maskable interrupts.
Some interrupt signals are not affected by the interrupt mask and therefore cannot be
disabled; these are called non-maskable interrupts (NMI). NMIs indicate high priority
events which cannot be ignored under any circumstances, such as the timeout signal
from a watchdog timer.
Spurious interrupts
A spurious interrupt is the occurrence of a false interrupt request signal. These are
typically short-lived, invalid signal levels which are generated by electrical
interference or malfunctioning devices.
Software interrupts
A software interrupt is requested by the processor itself upon executing particular
instructions or when certain conditions are met. Every software interrupt signal is
associated with a particular interrupt handler.
TRIGGERING METHODS
Each interrupt signal input is designed to be triggered by either a logic signal level or a
particular signal edge (level transition). Level-sensitive inputs continuously request
processor service so long as a particular (high or low) logic level is applied to the input.
Edge-sensitive inputs react to signal edges: a particular (rising or falling) edge will
cause a service request to be latched; the processor resets the latch when the interrupt
handler executes.
Level-triggered inputs allow multiple devices to share a common interrupt signal via
wired-OR connections. The processor polls to determine which devices are requesting
service. After servicing a device, the processor may again poll and, if necessary, service
other devices before exiting the ISR.
Edge-triggered
An edge-triggered interrupt is an interrupt signaled by a level transition on the interrupt
line, either a falling edge (high to low) or a rising edge (low to high). A device wishing
to signal an interrupt drives a pulse onto the line and then releases the line to its
inactive state. If the pulse is too short to be detected by polled I/O then special
hardware may be required to detect it.
PROCESSOR RESPONSE
The processor samples the interrupt trigger signal during each instruction cycle, and
will respond to the trigger only if the signal is asserted when sampling occurs.
Regardless of the triggering method, the processor will begin interrupt processing at
the next instruction boundary following a detected trigger, thus ensuring:
SYSTEM IMPLEMENTATION
REFERENCES:
https://electrosome.com/microprocessor/
https://en.m.wikipedia.org/wiki/Interrupt