TYPES OF EMBEDDED SYSTEMS

TYPES OF EMBEDDED SYSTEMS Schematic Representation

Embedded systems are classified into four categories

Based on their performance and functional requirements:
• Stand alone embedded systems
• Real time embedded systems
• Networked embedded systems
• Mobile embedded systems
Based on the performance of the microcontroller:
• Small scale embedded systems
• Medium scale embedded systems
• Sophisticated embedded systems
TYPES OF EMBEDDED SYSTEMS
REAL TIME EMBEDDED SYSTEMS Schematic Representation
▪ A Real-Time Embedded System is strictly time specific,
these provides output in a particular/defined time interval.
▪ These type of embedded systems provide quick response in
critical situations which gives most priority to time based
task performance and generation of output.
▪ That’s why real time embedded systems are used in defense
sector, medical and health care sector, and some other
industrial applications where output in the right time is given
more importance. MRI Scanner Blood pressure device

Soft Real Time Embedded Systems

▪ In these types of embedded systems time/deadline is not so
strictly followed. If deadline of the task is passed (means the
system didn’t give result in the defined time) still result or output
is accepted.
Hard Real-Time Embedded Systems
Example
▪ In these types of embedded systems time/deadline of task is •Traffic control system
strictly followed. •Military usage in defense sector
▪ Task must be completed in between time frame (defined time •Medical usage in health sector
interval) otherwise result/output may not be accepted.
TYPES OF EMBEDDED SYSTEMS
STAND ALONE EMBEDDED SYSTEMS Schematic Representation
▪ Stand alone embedded systems do not require a host system
like a computer, it works by itself.
▪ It takes the input from the input ports either analog or digital
and processes, calculates and converts the data and gives the
resulting data through the connected device-Which either
controls, drives and displays the connected devices.
Examples
▪ MP3 players,
▪ Digital cameras,
▪ Microwave ovens
▪ Calculator
TYPES OF EMBEDDED SYSTEMS
NETWORKED EMBEDDED SYSTEMS Schematic Representation
• Networked Embedded Systems are connected to a network
which may be wired or wireless to provide output to the
attached device.
• They communicate with embedded web server through
network.
• The embedded web server is a type of system wherein
all embedded devices are connected to a web server and
accessed and controlled by a web browser.
Example:
• Home security system
• ATM machine
• Card swipe machine
TYPES OF EMBEDDED SYSTEMS
MOBILE EMBEDDED SYSTEMS Schematic Representation
• Mobile embedded systems are small and easy to use and
requires less resources.
• They are the most preferred embedded systems. In portability
point of view mobile embedded systems are also best.
• The basic limitation of these devices is the other resources and
limitation of memory.
Examples:
•MP3 player
•Mobile phones
•Digital Camera
TYPES OF EMBEDDED SYSTEMS
SMALL SCALE EMBEDDED SYSTEMS
▪ Small Scale Embedded Systems are designed using an 8-bit or
16-bit micro-controller.
▪ They can be powered by a battery.
▪ The processor uses very less/limited resources of memory and
processing speed.
▪ Mainly these systems does not act as an independent system
they act as any component of computer system but they did not
compute and dedicated for a specific task.

MEDIUM SACLE EMBEDDED SYSTEMS

▪ Medium Scale Embedded Systems are designed using an 16-bit or
32-bit micro-controller.
▪ These medium Scale Embedded Systems are faster than that of small
Scale Embedded Systems.
▪ Integration of hardware and software is complex in these systems.
▪ Java, C, C++ are the programming languages are used to develop medium
scale embedded systems. Different type of software tools like compiler,
debugger, simulator etc. are used to develop these type of systems.
TYPES OF EMBEDDED SYSTEMS
SOPHISTICATED EMBEDDED SYSTEMS
▪ Sophisticated or Complex Embedded Systems are designed using multiple 32-
bit or 64-bit micro-controller.
▪ These systems are developed to perform large scale complex functions.
▪ These systems have high hardware and software complexities.
▪ We use both hardware and software components to design final systems
or hardware products.
COMPARISON OF ES WITH GENERAL PURPOSE PROCESSORS

COMPARISON OF EMBEDDED SYSTEM WITH GPP

GENERAL PURPOSE
CRITERIA EMBEDDED SYSTEMS
COMPUTERS/PROCESSORS

Combination of generic Combination of special

hardware and general purpose hardware and
Contents purpose operating system embedded operating
for executing variety of system for executing special
applications. set of applications.
It contains general purpose It may or may not contain
Operating System
operating system. operating system.
Applications are alterable Applications are non-
Alterations
by the user. alterable by the user.
Application specific
Key factor Performance is a key factor.
requirement are key factor.
Power consumption More Less
Critical for some
Response Time Not critical
applications.
EMBEDDED SYSTEM HARDWARE
EMBEDDED SYSTEM HARDWARE Schematic Representation
▪ Embedded system hardware’s basic task is to receive input
process it and provide output.
▪ The basic hardware is built to meet the requirement of the
information processing system of the embedded appliance.
▪ The information processing system basically it would consist Information
of a processor and the other peripherals to maintain and Input Output
processing
manage input and output interfaces. Interface Interface
system
▪ The processors are micro processors and micro-controllers, in
comparison to general purpose processors considerations are
▪ High energy efficiency- Enhanced battery life or less
power consumption
▪ High code density- Less requirement of program
memory
Example: Intel Pentium microprocessors used as CPU for
computers
MICROPROCESSORS
MICROPROCESSORS Schematic Representation
▪ The entire CPU is fabricated on a single chip for computers
▪ Consists of registers to store the temporary data
▪ Consists of an Arithmetic and Logical Unit (ALU) for
arithmetic and logical operations
▪ Consist of some mechanism to interface external devices
(memory and I/O) through buses (address, data and control)
▪ No RAM, ROM, I/O on CPU chip itself
▪ Consists of a control unit that synchronize the operation.
▪ Example: Intel’s X86, Motorola’s 680x0
▪ These are general purpose microprocessors.
▪ A typical computer is build around this microprocessor having
this architecture.
▪ This is the architecture of general purpose microprocessor.

What is microcontroller?
MICROCONTROLLER
MICROCONTROLLER Schematic Representation
▪ A microcontroller is a device which integrates a number of
components of a microprocessor onto a single chip.
▪ A micro-controller combines onto a same microchip:
▪ The CPU core
▪ Memory (both RAM and ROM)
▪ Some parallel digital I/O and many other peripherals

BLOCK DIAGRAM:
▪ CPU
▪ I/O ports
▪ Memory
▪ All connected via bus.
▪ All these things are integrated on the same silicon chip.
▪ There are other component of microprocessor as well.
COMPONENTS OF MICROCONTROLLER
MICROCONTROLLER COMPONENTS Schematic Representation
▪ A timer module to allow microcontroller to perform task for
certain time periods.
▪ A serial I/O port to allow data to flow between the
microcontroller and other devices such as PC or another
microcontroller.
▪ An ADC to allow the microcontroller to accept analog input
data for processing.
WHY MICROCONTROLLER?
WHY MICROCONTROLLER?
▪ Low cost and small packaging
▪ Low power consumption
▪ Programmable, reprogrammable
▪ Lots of I/O capabilities
▪ Easy integration with circuits
▪ For application in which cost, power and space are
critical
▪ Single-purpose
COMPUTER ARCHITECTURE
1. VONNEUMAN ARCHITECTURE Schematic Representation
▪ Only one bus between CPU and memory
▪ RAM and program memory share the same bus and the same
Memory, and so must have the same bit width
▪ Bottleneck, Getting instructions interfaces with accessing RAM
Program
and
▪ Address is provided from the CPU to the memory to fetch instruction Data
as well as to fetch data and we use the bus to read the data as well BUS
Memory
as write the data on to that memory.
▪ There is no difference between the data and instruction in VonNeuman
architecture.
▪ Both program and data memory is connected to the CPU by the same
address and data bus.
▪ we can get a bottleneck because getting instructions may interfere
accessing RAM for data.
▪ we have the same bus and hence the instruction and the data word is
typically of the same bit width.
COMPUTER ARCHITECTURE
2. HARVARD ARCHITECTURE Schematic Representation
▪ Uses two separate memory spaces for program
instruction and data
▪ Improved operation bandwidth
▪ Allows for different bus widths
▪ Instruction pipelining easy
Data
▪ Program memory different from that of the data Memory
memory. Program 8-Bits
▪ Two distinct buses connecting CPU to the program Memory
12/14/16-Bits
memory and data memory.
▪ Two distinct buses their bit widths can be different.

▪ Modern micro-controller are build around

Harvard Architecture.
CISC-COMPLEX INSTRUCTION SET COMPUTER

▪ A large number of instruction each carrying out a different permutation of

the same operation
▪ Instruction provide for complex operations
▪ Different instruction of different format
▪ Different addressing modes
▪ Requires multiples cycle of execution
RISC-REDUCED INSTRUCTION SET COMPUTER

▪ Instruction for simple operation that can be executed in a single cycle

▪ Each instruction of fixed length
▪ Facilitates instruction pipelining
▪ Large general purpose register set
▪ Can contain data or address
▪ Load-Store Architecture
▪ No memory access for data processing instructions
ARM PROCESSORS
OBJECTIVE
▪ History

▪ ARM Architecture Versions

▪ Basic ARM Organization

▪ Status Registers

▪ Processor Modes
History

▪ ARM was developed at Acron Computer Limited of Cambridge,

England between 1983 & 1985
▪ RISC concept introduced in 1980 at Stanford and Berkley
▪ ARM Limited founded in 1990 (Initially owned by Acorn, Apple and
VLSI)
▪ ARM Cores
▪ Licensed to partners to develop and fabricate new micro-controllers
▪ Soft-core
ARM Partnership Model
ARM Powered Products
ARM Architecture
History
Based upon RISC Architecture with enhancements to meet requirements of
embedded applications
▪ A large uniform register file
▪ Load-store architecture, where data processing operations operate on register
contents only (does not involves memory locations)
▪ Uniform and fixed length instructions
▪ 32-bit processor (can supports both 16/32 bit operation)
▪ Instructions are 32-bit long
▪ Good Speed/Power Consumption Ratio
▪ High Code Density as needed for embedded systems.
Why do we talk about ARM?

• One of the most widely used processor cores.

• Some application examples:
• ARM7: iPod
• ARM9: BenQ, Sony Ericsson
• ARM11: Apple iPhone, Nokia N93, N100
• 90% of 32-bit embedded RISC processor till 2010
• Mainly used in battery-operated devices:
• Due to low power consumption and reasonably good performance.
ARM is based on RISC Architecture
• RISC supports simple but powerful instructions that execute in a single cycle
at high clock frequency.
• Major design features:
• Instructions: reduced set / single cycle / fixed length
• Pipeline: decode in one stage / no need for microcode
• Registers: large number of general-purpose registers (GPRs)
• Load/Store Architecture: data processing instructions work on registers only;
load/store instructions to transfer data from/to memory.
• RISC is having fewer addressing mode (Higher than PIC previously studied) as
most instructions are based on registers
• Now-a-days CISC machines also implement RISC concepts.
ARM Features
ARM architecture is different from pure RISC:

▪ Variable cycle execution for certain instructions (multiple-register load/store for

higher code density).
▪ In-line barrel shifter results in more complex instructions (improves performance
and code density).
▪ Thumb 16-bit instruction set (results in improvement in code density by about
30%).
▪ Auto-increment and auto-decrement addressing modes to optimize program loops
▪ Load and Store Multiple data elements through a single instructions to maximize
data throughput
▪ Conditional Execution (branching instructions) of instruction to maximize execution
throughput
▪ Enhanced instructions (some DSP instructions are present).
ARM Architecture Versions
▪ Version 1 (1983-85)
▪ 26 bit addressing, no multiply or coprocessor
▪ Version 2
▪ Includes 32-bit result multiply co-processor
▪ Version 3
▪ 32 bit addressing
▪ Version 4
▪ Add signed, unsigned half-word and signed byte load and store instructions
▪ Version 4T
▪ 16-bit Thumb compressed form of instruction introduced
▪ Version 5T
▪ Superset of 4T adding new instruction
▪ Version 5TE
▪ Add signal processing signal extension
▪ Examples:
▪ ARM 6 : v3
▪ ARM7(very popular) : v3, ARM7TDMI : v4T
▪ Strong ARM (developed by intel): v4
▪ ARM 9E-S (Extension Architecture) : v5TE- targeted for digital signals like speech, videos etc.
Popular ARM Architectures

• ARM7
• 3 pipeline stages (fetch/decode/execute)
• High code density / low power consumption
• Most widely used for low-end systems
• ARM9
• Compatible with ARM7
• 5 stages (fetch/decode/execute/memory/write)
• Separate instruction and data cache
• ARM10
• 6-stages (fetch/issue/decode/execute/memory/write)
ARM Family Comparison

ARM 7 ARM9 ARM10 ARM11

(1995) (1997) (1999) (2003)
Pipeline depth 3 Stage 5 Stage 6 Stage 8 Stage
Typical clock frequency (MHz) 80 150 260 335
Power (mW/MHz) 0.06 0.19 0.50 0.40
Throughput (MIPS/MHz) 0.97 1.1 1.3 1.2
Architecture Non Harvard Harvard Harvard
Neumann
Multiplier 8 x 32 8 x 32 16 x 32 16 x 32
Data Sizes and Instruction Sets
• The ARM is a 32-bit architecture.

• When used in relation to the ARM:

• Byte means 8 bits
• Halfword means 16 bits (two bytes)
• Word means 32 bits (four bytes)

• Most ARM’s implement two instruction sets

• 32-bit ARM Instruction Set
• 16-bit Thumb Instruction Set

• Jazelle cores can also execute Java bytecode

 Naming ARM

ARM {x}{y}{z} {T}{D}{M}{I} {E}{J}{F}{S}

– x : series
– y : MMU (memory management/protection unit)
– z : cache
– T : Thumb
– D : debugger
– M : Multiplier
– I : Embedded ICE (built-in debugger hardware)
– E : Enhanced instruction
– J : Jazelle (JVM)
– F : Floating-point
– S : Synthesiziable version (Source Code version for EDA tools)
Overview: Core Data Path

▪ Data items are placed in register file

▪ No data processing instructions directly manipulate data in memory
▪ Instructions typically use two source registers and single result or destination registers
▪ A Barrel shifter on the data path can pre-process data before it enters ALU
▪ Barrel shifter is a combinational circuit, which can shift the data bits to the left/right in the
same instruction cycle.
▪ Increment/decrement logic can update register content for sequential access independent of
ALU
Basic ARM Organization
Register bank: is connected to ALU via two data paths. A[31:0] control
A bus and B bus.
B bus goes by Barrel shifter which can pre-process the data. address r egister

Barrel shifter can shift to the right/left or rotate the date before
P
it fed to the ALU. C incr ementer

All the operation of Barrel shifter and ALU can be completed in a

Single instruction cycle, that speeds up the execution speed. PC
r egister
PC is the parts of the register bank that generates the address for bank

the instructions. instr uction

decode
A
Incremental block: Enables the decrement or increment in register L
multiply
r egister
&
U
Values independent of the ALU. A B
control
b
u b b
s u u
Instruction decode & Control: Provides the control signals. s bar rel s
shifter

Address Bus: 32 bits

ALU

Data Bus: 32 bits

It is a 32 bit processor which can operate on 32 bit operands.
Registers can handle address and data in symmetric fashion, it uses
Same number of bits for data and address and use similar kinds of data out regist er data in r egister

operation for manipulating data and addresses and data in the D[31:0]
registers.
Basic ARM Architecture/ Data Flow Model

❖ Barrel Shifter ❑ It is used to pre shift operand before it is given

to ALU
❑ It enables shifting of 32-bit operand in one of
Register the source registers left or right by a specific
number of positions within the cycle time of
instruction
❑ Basic Barrel shifter operations
❑ Shift left, shift right, rotate right
Immediate value
❑ Facilitates fast multiply, division and increases
code density
❑ Example: mov r7, r5, LSL #2
❖ MAC: Multiply Accumulate
❑ It is used to perform multiplication operation with
accumulation
❑ It is useful for long multiplication
❑ Example: MLA r0,r1,r2,r3
❑ It after execution r0=r1*r2+r3

❖ Address Register
❑ It is used to hold the operand address for load and store
instruction
❑ It has dedicated Incrementer for accessing the data from
subsequent location
❑ Incrementer plays a very important role in Base Index
Addressing Mode {Indirect Addressing Mode}.
Registers
▪ ARM7 has total 37 registers of size 32 bits.
▪ General Purpose registers (GPR) hold either data or address
▪ In user mode (common operating mode) 16 data registers and 2 status registers are visible
▪ Data registers: r0 to r15
▪ Three registers r13, r14, r15 perform special functions
▪ r13: stack pointer (There is no stack in ARM architecture. It is used as a pointer for software
managed stack)
▪ r14: link register ( Saves a copy of PC when executing the BL instruction/(subroutine call) or
when jumping to an exception or an interrupt handler)
▪ where return address is put whenever a subroutine is called)
▪ r15: program counter (pointed to the current instruction what is being executed )

• Depending upon context, registers r13 and r14 can also be used as GPR
• Any instruction which use r0 can as well be used with any other GPR (r1-r13)
• In addition, there are two status registers: set the processor operating mode, control of
enable/disable interrupts
• CPSR: current program status register
• SPSR: saved program status register
Program Counter (Register: r15)
▪ When the processor is executing in ARM state/mode
▪ All instructions are 32 bit wide
▪ All instructions are word aligned ( that mean all instructions must start from
an address that is multiple of 4)
▪ 32 bit address in ARM refers to Byte location
▪ Each Byte is associated with a unique address
▪ Total blocks of 4 Bytes
▪ PC value is stored in bits [31:2] with bits [1:0] undefined or 00 (as multiple of
4 byte )
▪ Due to pipelining, PC points 8 bytes ahead of the current instruction or 12
byte ahead if the current instruction includes a register specific shift
▪ When the processor is executing in Thumb Mode
▪ All instructions are 16 bit wide and are half word aligned (multiple of 2)
▪ The last bit of PC is 0 (i.e. not used)
Status Registers: CPSR
CPSR:
▪ Current program status register
▪ monitors and control internal operations
N: Negative Flag
1 = result negative or less than in last Condition code flags Interrupt Disable bits.
operation N = Negative result from ALU I = 1: Disables the IRQ.
0 = result positive or greater than. Z = Zero result from ALU F = 1: Disables the FIQ.
Z: Zero flag C = ALU operation Carried out
1 = result of 0 in last operation V = ALU operation oVerflowed T Bit
0 = nonzero result. Architecture xT only
C: Carry/Borrow flag T = 0: Processor in ARM state
1 = carry or borrow in last operation T = 1: Processor in Thumb state
0 = no carry or borrow.
Sticky Overflow flag - Q flag
V: ALU operation overflowed Architecture 5TE/J only
1 = overflow in last operation Indicates if saturation has occurred M: Mode field
0 = no overflow. b10000 = User mode
b10001 = FIQ mode
b10010 = IRQ mode
Q flag: Saturation Arithmetic Flag b10011 = Supervisor mode
b10111 = Abort mode
Note: In ARM like having Architecture 5TEJ, J bit is also there b11011 = Undefined mode
J = 1: Processor in Jazelle state b11111 = System mode.
Processor Modes
▪ Processor modes determine
▪ which registers are active, and
▪ access rights to CPSR register itself
▪ Each processor mode is either
▪ Privileged:
▪ full read-write access to the CPSR
▪ Change the control bits
▪ Change the processor mode
▪ Enable disable interrupts
▪ Non-privileged:
▪ only read access to the control field of CPSR but can not be changed
▪ read-write access to the condition flags
▪ ARM has seven modes
▪ Privileged: abort, fast interrupt request, interrupt request, supervisor, system and undefined
▪ Non-privileged: user
▪ User mode is used for programs and applications
Non - Privileged Mode
User Mode :
• only non-unprivileged mode
• This is normal mode in which user programs are executed.
• It has limited access to the memory, I/O and flags
• All other modes are entered through interrupts.
Privileged Mode

Fast Interrupt Request (FIQ)

Abort:
▪ Enter into this mode when high level interrupt available on
ARM ▪ Entered when there is a failed attempt to access
memory
▪ This interrupt should be served with minimum delay
▪ By default nested interrupts are enabled in this mode
Undefined:
Interrupt Request (IRQ) • when processor encounters an undefined instruction
▪ Enter into this mode when normal level interrupt available • This generally happens when co-processor
on ARM instruction encountered but coprocessor is not
▪ This interrupt should be served with some delay available

▪ By default nested interrupts are enabled in this mode System mode:

• special version of user mode that allows the used
Supervisor mode: enter into this mode
to get full read-write access of CPSR
• after reset and generally OS kernel or BIOS program
executes here • Also targeted for supervisory applications
• Can be invoked when by a Software Interrupt • Many OS routines can be configured to run in
instruction(SWI) by programmer system mode
Banked Registers

▪ Register file contains in all 37 User registers replaced by

registers banked registers
▪ 20 registers are hidden from
program at different times
▪ These registers are called banked
registers
▪ Banked registers are available
only when the processor is in a
particular mode
▪ Processor modes (other than
system mode) have a set of
associated banked registers that
are subset of 16 registers
▪ Maps one-to-one onto a user
mode register
Mode Changing

• Every processor mode except user mode can change mode by writing directly to the
mode bits of the cpsr. (the processor core has to be in privileged mode) or by
hardware when the core responds to an exception or interrupt.
• A banked register maps one-to one onto a user mode register.
• If you change processor mode, a banked register from the new mode will replace an
existing register.
• For example, when the processor is in the interrupt request mode, the instructions
you execute still access registers named r13 and r14. However, these registers are
the banked registers r13_irq and r14_irq. The user mode registers r13_usr and
r14_usr are not affected by the instruction referencing these registers.
▪ To return to user mode a special return instruction is used that instructs the core to
restore the original CPSR and banked registers
 Register Organization
▪ In privileged mode
processors write the
original data in the
register bank of which
the fresh copy is not
available.
▪ These register data
should be saved in
stack in order to get it
back when user process
is resumed.
▪ Software latency is
reduced for FIQ mode
because It has large
number of register
available i.e. r8-r14
ARM State Vs Thumb State
ARM State Thumb State
CPSR<T bit> T=0 T=1
Instruction Size 32 bits 16 bits
All instructions must be word aligned All instructions must be halfword aligned
Core Instructions 68 30
Conditional Execution Most Only Branch Instruction
CPSR Accessibility Full Access in System Mode No direct access
Register Usage 15 GPR + PC 8 GPR + 7 High Registers + PC
Code Density Low High
System Use Full use in ARM State Partial use of System in Thumb State
Application High Profile Applications Low Profile Applications
Memory Requirements More Memory required as size of Less Memory required as size of
instructions are 32 bit instructions are 16 bit
ARM7 Pipelining

❖ Fetch, Decode, Execute has equal size of machine

Cycle
❖ ARM7 has load and store architecture. So for
loading and storing the data with memory, there are
separate instructions
❖ As ARM7 supports 3 stage pipelining, Program
counter points 2 instruction ahead of the one being
executed now.
❖ Pipeline makes program execution fast
❖ But it fails in branch instruction execution

❖ ARM7 uses 3 stage pipeline: Fetch, Decode & Execute

❖ ARM9 uses 5 stage pipeline: Fetch, Decode, Execute, Memory Write & Register Write

❖ ARM10 uses 6 stage pipeline: Fetch, Issue, Decode, Execute, Memory Write & Register Write
ARM7 Exception Handling

• When an exception occurs, the ARM:

• Copies CPSR into SPSR_<mode>
• Sets appropriate CPSR bits
• Change to ARM state (T=0) 0x1C FIQ
0x18 IRQ
• Change to exception mode (by changing the mode bits of CPSR)
• Disable interrupts (if appropriate) 0x14 (Reserved)
0x10 Data Abort
• Stores the return address in LR_<mode>
0x0C Prefetch Abort
• Sets PC to vector address
0x08 Software Interrupt
• To return, exception handler needs to: 0x04 Undefined Instruction
• Restore CPSR from SPSR_<mode> 0x00 Reset
• Restore PC from LR_<mode> Vector Table
Vector table can be at
This can only be done in ARM state. 0xFFFF0000 on ARM720T
and on ARM9/10 family devices
 ARM7 Exception Handling

▪ Vector table – a table of addresses that the ARM core branches, may not
have space to put in complete service routine
▪ In the table it has a branch instruction, it changes the PC

▪ Fixed offset for each type of exception 0x1C FIQ

0x18 IRQ
▪ These addresses contain instructions of one of the following forms:
0x14 (Reserved)
▪ B <address> : branching relative to PC 0x10 Data Abort
0x0C Prefetch Abort
▪ LDR pc, [pc, #offset] : loads handler address from memory to PC
0x08 Software Interrupt
▪ Involves memory access and increases the delay latency 0x04 Undefined Instruction
0x00 Reset
▪ MOV PC, #immediate : loads immediate value into PC
Vector Table
▪ Give ability to locate the interrupt handler anywhere in the memory Vector table can be at
0xFFFF0000 on ARM720T
▪ Immediate operand can be appropriately changed and loaded on to the and on ARM9/10 family devices
PC to provide the address
Exceptions Priorities

Exceptions Priority I bit F bit

Reset 1 1 1
Data abort 2 1 -
FIQ 3 1 1
IRQ 4 1 -
Pre-fetch abort 5 1 -
SWI 6 1 -
Undefined 6 1 -
instructions
Exception Handler
Reset handler
▪ Initializes the system, setting up stack pointers, memory, external interrupt sources before enabling IRQ or FIQ
▪ Code should be designed to avoid further triggering of exceptions
Data Abort
▪ Occurs when memory controller indicates that an invalid memory address has been accessed
▪ An FIQ exception can be raised within data abort handler

FIQ
▪ Occurs when an external peripheral generates the FIQ input signal
▪ Core disables both FIQ and IRQ interrupts

IRQ
▪ Occurs when when an external device generates the IRQ input signal
▪ IRQ handler will be entered if neither an FIQ exception or Data abort exception occurs
▪ On entry IRQ exception is disabled and should remain disabled for the handler if not enabled by the handler

Prefetch Abort
▪ Occurs when an attempt to fetch an instruction results in memory fault
▪ FIQ exception can be serviced
Undefined instruction
▪ Occurs when an instruction is not in the ARM or Thumb instruction
▪ SWI and undefined instruction have the same level of priority because they cannot occur together
 Coprocessors
• Coprocessors can be attached to the ARM processor.
• A coprocessor extends the processing features of a core by extending the instruction set
or by providing configuration registers.
• More than one coprocessor can be added to the ARM core via the coprocessor interface.
• The coprocessor can be accessed through a group of dedicated ARM instructions that
provide a load-store type interface.
• The coprocessor can also extend the instruction set by providing a specialized group of
new instructions.

• These new instructions are processed in the decode stage of the ARM pipeline. If the
decode stage sees a coprocessor instruction, then it offers it to the relevant coprocessor.
But if the coprocessor is not present or doesn’t recognize the instruction, then the ARM
takes an undefined instruction exception, which allows you to emulate the behavior of
the coprocessor in software.