TYPES OF EMBEDDED SYSTEMS TYPES OF EMBEDDED SYSTEMS

TYPES OF EMBEDDED SYSTEMS Schematic Representation REAL TIME EMBEDDED SYSTEMS Schematic Representation
▪ A Real-Time Embedded System is strictly time specific,
Embedded systems are classified into four categories these provides output in a particular/defined time interval.
Based on their performance and functional requirements: ▪ These type of embedded systems provide quick response in
critical situations which gives most priority to time based
• Stand alone embedded systems task performance and generation of output.
• Real time embedded systems ▪ That’s why real time embedded systems are used in defense
sector, medical and health care sector, and some other
• Networked embedded systems industrial applications where output in the right time is given
more importance. MRI Scanner Blood pressure device
• Mobile embedded systems
Based on the performance of the microcontroller: Soft Real Time Embedded Systems
▪ In these types of embedded systems time/deadline is not so
• Small scale embedded systems strictly followed. If deadline of the task is passed (means the
• Medium scale embedded systems system didn’t give result in the defined time) still result or output
is accepted.
• Sophisticated embedded systems
Hard Real-Time Embedded Systems
Example
▪ In these types of embedded systems time/deadline of task is •Traffic control system
strictly followed. •Military usage in defense sector
▪ Task must be completed in between time frame (defined time •Medical usage in health sector
interval) otherwise result/output may not be accepted.

TYPES OF EMBEDDED SYSTEMS TYPES OF EMBEDDED SYSTEMS

STAND ALONE EMBEDDED SYSTEMS Schematic Representation NETWORKED EMBEDDED SYSTEMS Schematic Representation
▪ Stand alone embedded systems do not require a host system • Networked Embedded Systems are connected to a network
like a computer, it works by itself. which may be wired or wireless to provide output to the
▪ It takes the input from the input ports either analog or digital attached device.
and processes, calculates and converts the data and gives the • They communicate with embedded web server through
resulting data through the connected device-Which either network.
controls, drives and displays the connected devices. • The embedded web server is a type of system wherein
Examples all embedded devices are connected to a web server and
▪ MP3 players, accessed and controlled by a web browser.
▪ Digital cameras, Example:
▪ Microwave ovens • Home security system
▪ Calculator • ATM machine
• Card swipe machine
TYPES OF EMBEDDED SYSTEMS TYPES OF EMBEDDED SYSTEMS
MOBILE EMBEDDED SYSTEMS Schematic Representation SMALL SCALE EMBEDDED SYSTEMS
• Mobile embedded systems are small and easy to use and ▪ Small Scale Embedded Systems are designed using an 8-bit or
requires less resources. 16-bit micro-controller.
• They are the most preferred embedded systems. In portability ▪ They can be powered by a battery.
point of view mobile embedded systems are also best. ▪ The processor uses very less/limited resources of memory and
• The basic limitation of these devices is the other resources and processing speed.
limitation of memory. ▪ Mainly these systems does not act as an independent system
Examples: they act as any component of computer system but they did not
•MP3 player compute and dedicated for a specific task.
•Mobile phones
•Digital Camera
MEDIUM SACLE EMBEDDED SYSTEMS
▪ Medium Scale Embedded Systems are designed using an 16-bit or
32-bit micro-controller.
▪ These medium Scale Embedded Systems are faster than that of small
Scale Embedded Systems.
▪ Integration of hardware and software is complex in these systems.
▪ Java, C, C++ are the programming languages are used to develop medium
scale embedded systems. Different type of software tools like compiler,
debugger, simulator etc. are used to develop these type of systems.

TYPES OF EMBEDDED SYSTEMS COMPARISON OF ES WITH GENERAL PURPOSE PROCESSORS

SOPHISTICATED EMBEDDED SYSTEMS COMPARISON OF EMBEDDED SYSTEM WITH GPP

▪ Sophisticated or Complex Embedded Systems are designed using multiple 32-
bit or 64-bit micro-controller. GENERAL PURPOSE
CRITERIA EMBEDDED SYSTEMS
▪ These systems are developed to perform large scale complex functions. COMPUTERS/PROCESSORS
▪ These systems have high hardware and software complexities.
▪ We use both hardware and software components to design final systems Combination of generic Combination of special
or hardware products. hardware and general purpose hardware and
Contents purpose operating system embedded operating
for executing variety of system for executing special
applications. set of applications.
It contains general purpose It may or may not contain
Operating System
operating system. operating system.
Applications are alterable Applications are non-
Alterations
by the user. alterable by the user.
Application specific
Key factor Performance is a key factor.
requirement are key factor.
Power consumption More Less
Critical for some
Response Time Not critical
applications.
EMBEDDED SYSTEM HARDWARE MICROPROCESSORS
EMBEDDED SYSTEM HARDWARE Schematic Representation MICROPROCESSORS Schematic Representation
▪ Embedded system hardware’s basic task is to receive input ▪ The entire CPU is fabricated on a single chip for computers
process it and provide output. ▪ Consists of registers to store the temporary data
▪ The basic hardware is built to meet the requirement of the ▪ Consists of an Arithmetic and Logical Unit (ALU) for
information processing system of the embedded appliance. arithmetic and logical operations
▪ The information processing system basically it would consist Information ▪ Consist of some mechanism to interface external devices
of a processor and the other peripherals to maintain and Input Output (memory and I/O) through buses (address, data and control)
processing
manage input and output interfaces. Interface Interface ▪ No RAM, ROM, I/O on CPU chip itself
system
▪ The processors are micro processors and micro-controllers, in ▪ Consists of a control unit that synchronize the operation.
comparison to general purpose processors considerations are ▪ Example: Intel’s X86, Motorola’s 680x0
▪ High energy efficiency- Enhanced battery life or less ▪ These are general purpose microprocessors.
power consumption ▪ A typical computer is build around this microprocessor having
▪ High code density- Less requirement of program this architecture.
memory ▪ This is the architecture of general purpose microprocessor.
Example: Intel Pentium microprocessors used as CPU for
computers

What is microcontroller?

MICROCONTROLLER COMPONENTS OF MICROCONTROLLER

MICROCONTROLLER Schematic Representation MICROCONTROLLER COMPONENTS Schematic Representation
▪ A microcontroller is a device which integrates a number of ▪ A timer module to allow microcontroller to perform task for
components of a microprocessor onto a single chip. certain time periods.
▪ A micro-controller combines onto a same microchip: ▪ A serial I/O port to allow data to flow between the
▪ The CPU core microcontroller and other devices such as PC or another
▪ Memory (both RAM and ROM) microcontroller.
▪ Some parallel digital I/O and many other peripherals ▪ An ADC to allow the microcontroller to accept analog input
data for processing.

BLOCK DIAGRAM:
▪ CPU
▪ I/O ports
▪ Memory
▪ All connected via bus.
▪ All these things are integrated on the same silicon chip.
▪ There are other component of microprocessor as well.
WHY MICROCONTROLLER? COMPUTER ARCHITECTURE
WHY MICROCONTROLLER? 1. VONNEUMAN ARCHITECTURE Schematic Representation
▪ Only one bus between CPU and memory
▪ Low cost and small packaging ▪ RAM and program memory share the same bus and the same
▪ Low power consumption Memory, and so must have the same bit width
▪ Bottleneck, Getting instructions interfaces with accessing RAM
▪ Programmable, reprogrammable
Program
▪ Lots of I/O capabilities and
▪ Easy integration with circuits ▪ Address is provided from the CPU to the memory to fetch instruction Data
Memory
▪ For application in which cost, power and space are as well as to fetch data and we use the bus to read the data as well
as write the data on to that memory.
BUS

critical ▪ There is no difference between the data and instruction in VonNeuman

architecture.
▪ Single-purpose ▪ Both program and data memory is connected to the CPU by the same
address and data bus.
▪ we can get a bottleneck because getting instructions may interfere
accessing RAM for data.
▪ we have the same bus and hence the instruction and the data word is
typically of the same bit width.

COMPUTER ARCHITECTURE
2. HARVARD ARCHITECTURE Schematic Representation
CISC-COMPLEX INSTRUCTION SET COMPUTER
▪ Uses two separate memory spaces for program
instruction and data
▪ Improved operation bandwidth
▪ Allows for different bus widths
▪ A large number of instruction each carrying out a different permutation of
▪ Instruction pipelining easy the same operation
Data ▪ Instruction provide for complex operations
▪ Program memory different from that of the data Memory
memory.
▪ Different instruction of different format
Program 8-Bits
▪ Two distinct buses connecting CPU to the program Memory ▪ Different addressing modes
12/14/16-Bits
memory and data memory. ▪ Requires multiples cycle of execution
▪ Two distinct buses their bit widths can be different.

▪ Modern micro-controller are build around

Harvard Architecture.
RISC-REDUCED INSTRUCTION SET COMPUTER

▪ Instruction for simple operation that can be executed in a single cycle

▪ Each instruction of fixed length
▪ Facilitates instruction pipelining
▪ Large general purpose register set
▪ Can contain data or address
▪ Load-Store Architecture ARM PROCESSORS
▪ No memory access for data processing instructions

OBJECTIVE History
▪ History
▪ ARM was developed at Acron Computer Limited of Cambridge,
▪ ARM Architecture Versions England between 1983 & 1985
▪ Basic ARM Organization ▪ RISC concept introduced in 1980 at Stanford and Berkley
▪ Status Registers
▪ ARM Limited founded in 1990 (Initially owned by Acorn, Apple and
VLSI)
▪ Processor Modes
▪ ARM Cores
▪ Licensed to partners to develop and fabricate new micro-controllers
▪ Soft-core
 ARM Partnership Model
ARM Powered Products

ARM Architecture Why do we talk about ARM?

History
Based upon RISC Architecture with enhancements to meet requirements of
embedded applications • One of the most widely used processor cores.
• Some application examples:
▪ A large uniform register file • ARM7: iPod
▪ Load-store architecture, where data processing operations operate on register • ARM9: BenQ, Sony Ericsson
contents only (does not involves memory locations) • ARM11: Apple iPhone, Nokia N93, N100
• 90% of 32-bit embedded RISC processor till 2010
▪ Uniform and fixed length instructions
• Mainly used in battery-operated devices:
▪ 32-bit processor (can supports both 16/32 bit operation) • Due to low power consumption and reasonably good performance.
▪ Instructions are 32-bit long
▪ Good Speed/Power Consumption Ratio
▪ High Code Density as needed for embedded systems.
 ARM Features
ARM is based on RISC Architecture ARM architecture is different from pure RISC:

• RISC supports simple but powerful instructions that execute in a single cycle ▪ Variable cycle execution for certain instructions (multiple-register load/store for
at high clock frequency. higher code density).
• Major design features: ▪ In-line barrel shifter results in more complex instructions (improves performance
• Instructions: reduced set / single cycle / fixed length and code density).
• Pipeline: decode in one stage / no need for microcode
• Registers: large number of general-purpose registers (GPRs) ▪ Thumb 16-bit instruction set (results in improvement in code density by about
• Load/Store Architecture: data processing instructions work on registers only; 30%).
load/store instructions to transfer data from/to memory.
▪ Auto-increment and auto-decrement addressing modes to optimize program loops
• RISC is having fewer addressing mode (Higher than PIC previously studied) as
most instructions are based on registers ▪ Load and Store Multiple data elements through a single instructions to maximize
data throughput
• Now-a-days CISC machines also implement RISC concepts.
▪ Conditional Execution (branching instructions) of instruction to maximize execution
throughput
▪ Enhanced instructions (some DSP instructions are present).

ARM Architecture Versions

Popular ARM Architectures
▪ Version 1 (1983-85)
▪ 26 bit addressing, no multiply or coprocessor
▪ Version 2 • ARM7
▪ Includes 32-bit result multiply co-processor • 3 pipeline stages (fetch/decode/execute)
▪ Version 3
▪ 32 bit addressing • High code density / low power consumption
▪ Version 4 • Most widely used for low-end systems
▪ Add signed, unsigned half-word and signed byte load and store instructions
▪ Version 4T • ARM9
▪ 16-bit Thumb compressed form of instruction introduced
▪ Version 5T
• Compatible with ARM7
▪ Superset of 4T adding new instruction • 5 stages (fetch/decode/execute/memory/write)
▪ Version 5TE • Separate instruction and data cache
▪ Add signal processing signal extension
▪ Examples: • ARM10
▪ ARM 6 : v3
▪ ARM7(very popular) : v3, ARM7TDMI : v4T • 6-stages (fetch/issue/decode/execute/memory/write)
▪ Strong ARM (developed by intel): v4
▪ ARM 9E-S (Extension Architecture) : v5TE- targeted for digital signals like speech, videos etc.
ARM Family Comparison Data Sizes and Instruction Sets
• The ARM is a 32-bit architecture.
ARM 7 ARM9 ARM10 ARM11
(1995) (1997) (1999) (2003) • When used in relation to the ARM:
Pipeline depth 3 Stage 5 Stage 6 Stage 8 Stage • Byte means 8 bits
80 150 260 335
• Halfword means 16 bits (two bytes)
Typical clock frequency (MHz) • Word means 32 bits (four bytes)
Power (mW/MHz) 0.06 0.19 0.50 0.40
Throughput (MIPS/MHz) 0.97 1.1 1.3 1.2 • Most ARM’s implement two instruction sets
• 32-bit ARM Instruction Set
Architecture Non Harvard Harvard Harvard • 16-bit Thumb Instruction Set
Neumann
Multiplier 8 x 32 8 x 32 16 x 32 16 x 32
• Jazelle cores can also execute Java bytecode

Naming ARM
Overview: Core Data Path
ARM {x}{y}{z} {T}{D}{M}{I} {E}{J}{F}{S}
▪ Data items are placed in register file
– x : series
– y : MMU (memory management/protection unit) ▪ No data processing instructions directly manipulate data in memory
– z : cache
– T : Thumb ▪ Instructions typically use two source registers and single result or destination registers
– D : debugger ▪ A Barrel shifter on the data path can pre-process data before it enters ALU
– M : Multiplier
– I : Embedded ICE (built-in debugger hardware) ▪ Barrel shifter is a combinational circuit, which can shift the data bits to the left/right in the
– E : Enhanced instruction same instruction cycle.
– J : Jazelle (JVM) ▪ Increment/decrement logic can update register content for sequential access independent of
– F : Floating-point
– S : Synthesiziable version (Source Code version for EDA tools) ALU
Basic ARM Organization
Register bank: is connected to ALU via two data paths. A[31:0] control
Basic ARM Architecture/ Data Flow Model
A bus and B bus.
B bus goes by Barrel shifter which can pre-process the data. address r egister

Barrel shifter can shift to the right/left or rotate the date before
P ❖ Barrel Shifter ❑ It is used to pre shift operand before it is given
it fed to the ALU.
All the operation of Barrel shifter and ALU can be completed in a
C incr ementer
to ALU
Single instruction cycle, that speeds up the execution speed. ❑ It enables shifting of 32-bit operand in one of
PC
r egister
PC is the parts of the register bank that generates the address for bank

the instructions. instr uction

Register the source registers left or right by a specific
A
decode
number of positions within the cycle time of
Incremental block: Enables the decrement or increment in register multiply
instruction
&
L r egister
U
Values independent of the ALU. A B
control
b
u
s
b
u
b
u ❑ Basic Barrel shifter operations
Instruction decode & Control: Provides the control signals. s bar rel s

❑ Shift left, shift right, rotate right

shifter

Address Bus: 32 bits Immediate value

ALU ❑ Facilitates fast multiply, division and increases
Data Bus: 32 bits
It is a 32 bit processor which can operate on 32 bit operands.
code density
Registers can handle address and data in symmetric fashion, it uses ❑ Example: mov r7, r5, LSL #2
Same number of bits for data and address and use similar kinds of data out regist er data in r egister

operation for manipulating data and addresses and data in the D[31:0]
registers.

Registers
❖ MAC: Multiply Accumulate ▪ ARM7 has total 37 registers of size 32 bits.
▪ General Purpose registers (GPR) hold either data or address
❑ It is used to perform multiplication operation with ▪ In user mode (common operating mode) 16 data registers and 2 status registers are visible
accumulation ▪ Data registers: r0 to r15
❑ It is useful for long multiplication ▪ Three registers r13, r14, r15 perform special functions
❑ Example: MLA r0,r1,r2,r3 ▪ r13: stack pointer (There is no stack in ARM architecture. It is used as a pointer for software
❑ It after execution r0=r1*r2+r3
managed stack)
▪ r14: link register ( Saves a copy of PC when executing the BL instruction/(subroutine call) or
❖ Address Register when jumping to an exception or an interrupt handler)
▪ where return address is put whenever a subroutine is called)
❑ It is used to hold the operand address for load and store ▪ r15: program counter (pointed to the current instruction what is being executed )
instruction
❑ It has dedicated Incrementer for accessing the data from • Depending upon context, registers r13 and r14 can also be used as GPR
subsequent location • Any instruction which use r0 can as well be used with any other GPR (r1-r13)
• In addition, there are two status registers: set the processor operating mode, control of
❑ Incrementer plays a very important role in Base Index
enable/disable interrupts
Addressing Mode {Indirect Addressing Mode}.
• CPSR: current program status register
• SPSR: saved program status register
 Status Registers: CPSR
Program Counter (Register: r15) CPSR:
▪ Current program status register
▪ When the processor is executing in ARM state/mode ▪ monitors and control internal operations
▪ All instructions are 32 bit wide N: Negative Flag
1 = result negative or less than in last Condition code flags Interrupt Disable bits.
▪ All instructions are word aligned ( that mean all instructions must start from operation I = 1: Disables the IRQ.
N = Negative result from ALU
an address that is multiple of 4) 0 = result positive or greater than. Z = Zero result from ALU F = 1: Disables the FIQ.
▪ 32 bit address in ARM refers to Byte location Z: Zero flag C = ALU operation Carried out
1 = result of 0 in last operation V = ALU operation oVerflowed T Bit
▪ Each Byte is associated with a unique address 0 = nonzero result. Architecture xT only
C: Carry/Borrow flag T = 0: Processor in ARM state
▪ Total blocks of 4 Bytes T = 1: Processor in Thumb state
1 = carry or borrow in last operation
▪ PC value is stored in bits [31:2] with bits [1:0] undefined or 00 (as multiple of 0 = no carry or borrow.
Sticky Overflow flag - Q flag
4 byte ) V: ALU operation overflowed Architecture 5TE/J only
1 = overflow in last operation M: Mode field
▪ Due to pipelining, PC points 8 bytes ahead of the current instruction or 12 0 = no overflow.
Indicates if saturation has occurred
b10000 = User mode
byte ahead if the current instruction includes a register specific shift b10001 = FIQ mode
b10010 = IRQ mode
▪ When the processor is executing in Thumb Mode Q flag: Saturation Arithmetic Flag b10011 = Supervisor mode
▪ All instructions are 16 bit wide and are half word aligned (multiple of 2) b10111 = Abort mode
Note: In ARM like having Architecture 5TEJ, J bit is also there b11011 = Undefined mode
▪ The last bit of PC is 0 (i.e. not used) J = 1: Processor in Jazelle state b11111 = System mode.

Processor Modes
▪ Processor modes determine
▪ which registers are active, and
▪ access rights to CPSR register itself
▪ Each processor mode is either
▪ Privileged:
▪ full read-write access to the CPSR
▪ Change the control bits
▪ Change the processor mode
▪ Enable disable interrupts
▪ Non-privileged:
▪ only read access to the control field of CPSR but can not be changed
▪ read-write access to the condition flags
▪ ARM has seven modes
▪ Privileged: abort, fast interrupt request, interrupt request, supervisor, system and undefined
▪ Non-privileged: user
▪ User mode is used for programs and applications
 Privileged Mode
Non - Privileged Mode
User Mode : Fast Interrupt Request (FIQ)
Abort:
• only non-unprivileged mode ▪ Enter into this mode when high level interrupt available on
ARM ▪ Entered when there is a failed attempt to access
• This is normal mode in which user programs are executed. memory
• It has limited access to the memory, I/O and flags ▪ This interrupt should be served with minimum delay
• All other modes are entered through interrupts. ▪ By default nested interrupts are enabled in this mode
Undefined:
Interrupt Request (IRQ) • when processor encounters an undefined instruction
▪ Enter into this mode when normal level interrupt available • This generally happens when co-processor
on ARM instruction encountered but coprocessor is not
▪ This interrupt should be served with some delay available

▪ By default nested interrupts are enabled in this mode System mode:

• special version of user mode that allows the used
Supervisor mode: enter into this mode
to get full read-write access of CPSR
• after reset and generally OS kernel or BIOS program
executes here • Also targeted for supervisory applications
• Can be invoked when by a Software Interrupt • Many OS routines can be configured to run in
instruction(SWI) by programmer system mode

Banked Registers Mode Changing

• Every processor mode except user mode can change mode by writing directly to the
▪ Register file contains in all 37 User registers replaced by mode bits of the cpsr. (the processor core has to be in privileged mode) or by
registers banked registers hardware when the core responds to an exception or interrupt.
▪ 20 registers are hidden from
program at different times • A banked register maps one-to one onto a user mode register.
▪ These registers are called banked • If you change processor mode, a banked register from the new mode will replace an
registers existing register.
▪ Banked registers are available
only when the processor is in a • For example, when the processor is in the interrupt request mode, the instructions
particular mode you execute still access registers named r13 and r14. However, these registers are
▪ Processor modes (other than the banked registers r13_irq and r14_irq. The user mode registers r13_usr and
system mode) have a set of r14_usr are not affected by the instruction referencing these registers.
associated banked registers that ▪ To return to user mode a special return instruction is used that instructs the core to
are subset of 16 registers restore the original CPSR and banked registers
▪ Maps one-to-one onto a user
mode register
 Register Organization
ARM State Vs Thumb State
▪ In privileged mode
processors write the ARM State Thumb State
original data in the CPSR<T bit> T=0 T=1
register bank of which
Instruction Size 32 bits 16 bits
the fresh copy is not All instructions must be word aligned All instructions must be halfword aligned
available.
Core Instructions 68 30
▪ These register data
should be saved in Conditional Execution Most Only Branch Instruction
stack in order to get it CPSR Accessibility Full Access in System Mode No direct access
back when user process Register Usage 15 GPR + PC 8 GPR + 7 High Registers + PC
is resumed.
Code Density Low High
▪ Software latency is
reduced for FIQ mode System Use Full use in ARM State Partial use of System in Thumb State
because It has large Application High Profile Applications Low Profile Applications
number of register Memory Requirements More Memory required as size of Less Memory required as size of
available i.e. r8-r14 instructions are 32 bit instructions are 16 bit

ARM7 Pipelining ARM7 Exception Handling

❖ Fetch, Decode, Execute has equal size of machine • When an exception occurs, the ARM:
Cycle • Copies CPSR into SPSR_<mode>
❖ ARM7 has load and store architecture. So for • Sets appropriate CPSR bits
loading and storing the data with memory, there are • Change to ARM state (T=0) 0x1C FIQ
separate instructions 0x18 IRQ
• Change to exception mode (by changing the mode bits of CPSR)
❖ As ARM7 supports 3 stage pipelining, Program 0x14 (Reserved)
counter points 2 instruction ahead of the one being • Disable interrupts (if appropriate)
0x10 Data Abort
executed now. • Stores the return address in LR_<mode>
0x0C Prefetch Abort
❖ Pipeline makes program execution fast • Sets PC to vector address
0x08 Software Interrupt
❖ But it fails in branch instruction execution
• To return, exception handler needs to: 0x04 Undefined Instruction
• Restore CPSR from SPSR_<mode> 0x00 Reset
❖ ARM7 uses 3 stage pipeline: Fetch, Decode & Execute
❖ ARM9 uses 5 stage pipeline: Fetch, Decode, Execute, Memory Write & Register Write
• Restore PC from LR_<mode> Vector Table
Vector table can be at
This can only be done in ARM state. 0xFFFF0000 on ARM720T
and on ARM9/10 family devices
❖ ARM10 uses 6 stage pipeline: Fetch, Issue, Decode, Execute, Memory Write & Register Write
 Exceptions Priorities
ARM7 Exception Handling

▪ Vector table – a table of addresses that the ARM core branches, may not
Exceptions Priority I bit F bit
have space to put in complete service routine
▪ In the table it has a branch instruction, it changes the PC
Reset 1 1 1
▪ Fixed offset for each type of exception 0x1C FIQ Data abort 2 1 -
FIQ 3 1 1
0x18 IRQ
▪ These addresses contain instructions of one of the following forms:
0x14 (Reserved)
▪ B <address> : branching relative to PC 0x10 Data Abort IRQ 4 1 -
Pre-fetch abort 5 1 -
0x0C Prefetch Abort
▪ LDR pc, [pc, #offset] : loads handler address from memory to PC
0x08 Software Interrupt
▪ Involves memory access and increases the delay latency 0x04 Undefined Instruction SWI 6 1 -
0x00 Reset
▪ MOV PC, #immediate : loads immediate value into PC Undefined 6 1 -
Vector Table
▪ Give ability to locate the interrupt handler anywhere in the memory Vector table can be at
instructions
0xFFFF0000 on ARM720T
▪ Immediate operand can be appropriately changed and loaded on to the and on ARM9/10 family devices
PC to provide the address

Exception Handler Coprocessors

Reset handler
▪ Initializes the system, setting up stack pointers, memory, external interrupt sources before enabling IRQ or FIQ • Coprocessors can be attached to the ARM processor.
▪ Code should be designed to avoid further triggering of exceptions
Data Abort • A coprocessor extends the processing features of a core by extending the instruction set
▪ Occurs when memory controller indicates that an invalid memory address has been accessed or by providing configuration registers.
▪ An FIQ exception can be raised within data abort handler
• More than one coprocessor can be added to the ARM core via the coprocessor interface.
FIQ
▪ Occurs when an external peripheral generates the FIQ input signal • The coprocessor can be accessed through a group of dedicated ARM instructions that
▪ Core disables both FIQ and IRQ interrupts provide a load-store type interface.
IRQ • The coprocessor can also extend the instruction set by providing a specialized group of
▪ Occurs when when an external device generates the IRQ input signal
▪ IRQ handler will be entered if neither an FIQ exception or Data abort exception occurs
new instructions.
▪ On entry IRQ exception is disabled and should remain disabled for the handler if not enabled by the handler

Prefetch Abort • These new instructions are processed in the decode stage of the ARM pipeline. If the
▪ Occurs when an attempt to fetch an instruction results in memory fault
▪ FIQ exception can be serviced decode stage sees a coprocessor instruction, then it offers it to the relevant coprocessor.
Undefined instruction But if the coprocessor is not present or doesn’t recognize the instruction, then the ARM
▪ Occurs when an instruction is not in the ARM or Thumb instruction takes an undefined instruction exception, which allows you to emulate the behavior of
▪ SWI and undefined instruction have the same level of priority because they cannot occur together
the coprocessor in software.