IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO.

11, NOVEMBER 2008 1581

Layout of Decoupling Capacitors in

IP Blocks for 90-nm CMOS
Xiongfei Meng, Student Member, IEEE, Resve Saleh, Fellow, IEEE, and Karim Arabi, Member, IEEE

Abstract—On-chip decoupling capacitors (decaps) in the form cell decap layout [7], [8], [15] at the 90-nm technology node and
of MOS transistors are widely used to reduce power supply below.
noise. This paper provides guidelines for standard cell layouts of A number of relatively new issues for standard cell decaps
decaps for use within Intellectual Property (IP) blocks in applica-
tion-specific integrated circuit (ASIC) designs. At 90-nm CMOS must be addressed that impact the design and layout of these
technology and below, a tradeoff exists between high-frequency ef- cells at scaled technology nodes. We address two important
fects and electrostatic discharge (ESD) reliability when designing problems of decap frequency response and electrostatic dis-
the layout of such decaps. In this paper, the high-frequency effects charge (ESD) protection [11]. Since decaps are required to
are modeled using simple equations. A metric is developed to perform at increasingly higher operating frequencies, we first
determine the optimal number of fingers based on the frequency
response. Then, a cross-coupled design is described that has been
investigate the frequency response [6], [9], [10] and propose
recently introduced by cell library developers to handle ESD improvements to optimize decap layouts. Next, we investigate
problems. Unfortunately, it suffers from poor response times due the problems of reduced oxide thickness of a transistor, namely,
the large resistance inherent in its design. Improved cross-coupled ESD [11] and thin-oxide gate leakage [3], [4], in the context
designs are presented that properly balance issues of frequency of decap design. A potential ESD event across a thin gate
response with ESD performance, while greatly reducing thin-oxide
oxide increases the likelihood that a chip will be permanently
gate leakage.
damaged due to a short circuit in the decap itself. Higher gate
Index Terms—Electrostatic discharges, integrated circuit layout, leakage increases the total static power consumption of the
leakage currents, MOS capacitors.
chip.
A cross-coupled standard-cell design was proposed [12] to
I. INTRODUCTION address the issue of ESD performance. The design provides
sufficient ESD protection, but does not offer any savings in
ITH increasing clock frequency and decreasing supply
W voltage as CMOS technology scales, maintaining the
quality of the power supply has become a primary issue. Voltage
gate leakage and it may compromise the frequency response.
This paper suggests improved layouts of the cross-coupled de-
sign that properly tradeoff frequency response and ESD perfor-
variations in the power supply arise due to IR drop and Ldi/dt
mance, while greatly reducing gate leakage current.
[1]. The IR drop has been increasing over time due to increased
The rest of this paper is organized as follows. In Section II,
resistances in the power grid as the metal widths continue to
layout design based on the frequency response of decaps is ad-
shrink with each successive technology generation. The induc-
dressed. The two new design issues, ESD reliability and gate
tive Ldi/dt effects are also increasing due to the high current de-
tunneling leakage, are briefly discussed in Section III, followed
mands of application-specific integrated circuit (ASIC) designs
by the cross-coupled design and its layout modifications. Con-
in 90-nm CMOS technology. However, the pin and package in-
clusions are provided in Section IV.
ductance overwhelms the inductance of the on-chip power dis-
tribution network, and therefore, the on-chip inductance is usu-
II. HIGH-FREQUENCY RESPONSE OF DECOUPLING CAPACITORS
ally neglected [1].
There are a variety of different methods that can be used to Standard cell layouts of an Intellectual Property (IP) block
manage voltage drops. Among them, the most popular is to use consist of rows of fixed-height cells in the ASIC design flow.
on-chip decoupling capacitors (decaps) to maintain the power After cell placement is completed, there are a number of empty
supply within a certain percentage (e.g., 10%) of the nominal cells that can be filled with decaps of various sizes depending on
supply voltage [2], [3]. Decaps are typically placed in regions the space available. Previous work has addressed the automatic
between areas of high current demands and the power pads and placement and sizing of decap cells [8]. Our focus is on optimal
input/output (I/O) pins [4]–[6]. This paper addresses standard- layout of each decap filler cell. Typically, these standard cells
have both nMOS and pMOS devices as shown in Fig. 1(a), with
Manuscript received July 13, 2006; revised May 3, 2007. First published
a corresponding layout in Fig. 1(b). Thin-oxide MOS devices
October 3, 2008; current version published October 22, 2008. This work are generally used for standard-cell decap implementation.
was supported in part by the Natural Sciences and Engineering Research As the frequency of operation increases, a fingering approach
Council of Canada (NSERC) and by PMC-Sierra Inc.
X. Meng and R. Saleh are with the Department of Electrical and Computer
is required to implement the layout. That is, a single transistor is
Engineering, University of British Columbia, Vancouver, BC V6T 1Z4, Canada split into a number of parallel transistors with the same width,
(e-mail: [email protected]; [email protected]). but smaller channel lengths. The overhead of this approach is
K. Arabi was with PMC-Sierra, Inc., Burnaby, BC V5A 4X1, Canada. additional spacing for source/drain contacts and an overall re-
He is now with Qualcomm, San Diego, CA 92121 USA (e-mail:
[email protected]). duction in the low-frequency capacitance. However, the average
Digital Object Identifier 10.1109/TVLSI.2008.2001240 capacitance of the decap over a given frequency range improves
1063-8210/$25.00 © 2008 IEEE

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 1582 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008

Fig. 3. Circuit setup to extract the effective resistance and the effective capac-
itance values from an ac analysis.

the number of fingers. Thus, the effective capacitance at dc is

given by
Fig. 1. (a) Standard cell decap can be implemented as an nMOS in parallel with
a pMOS device. The corresponding layout is shown in (b). (3)

For capacitance, each additional finger adds extra overlap and

fringing capacitances but loses area due to the contact spacing.
Therefore, the capacitance actually decreases linearly as we in-
crease the number of fingers. The corresponding equation for
with fingers in a parallel combination is

(4)

In previous work [10], the resistance was used to select the

Fig. 2. Decap can be implemented as an nMOS device and modeled as channel length and there were no area constraints involved.
a lumped-RC circuit with effective resistance and effective capacitance as
functions of frequency f .
However, since the resistance drops off as , it is not as
important in the selection of a suitable . In fact, the goal of
an optimal layout should be to provide the highest capacitance
as we increase the number of fingers. Therefore, we address the value in the given area over a desired operating frequency, 0 to
problem of how many fingers to use, given a fixed area of a , while delivering a low resistance. A simple metric is needed
filler cell and fixed gate-oxide thickness, and develop a useful to evaluate layouts with differing number of fingers. The logical
metric to capture the frequency response characteristics in order choice for a metric is to use the average capacitance over this
to choose the optimal number of fingers. frequency response up to , as follows:
To derive the needed equations, we begin with an nMOS de-
coupling capacitance as shown in Fig. 2. Non-idealities associ- (5)
ated with MOS devices are modeled as a lumped-resistance–ca-
pacitance (RC) circuit [10] where both the effective resistance where is obtained from (3) and is the effec-
, and effective capacitance , are functions of frequency tive capacitance with fingers at frequency . A weighted av-
, as shown in Fig. 2. erage is also feasible, but we find that the simple average works
The dc capacitance and resistance are given by well in practice.
[7], [10], [13] The main issue with the metric is that is diffi-
cult to compute without the aid of HSPICE or an equivalent
(1a) simulation tool. To facilitate the process, we developed simple
frequency-dependent models for both and . We also
(1b) wanted the characteristics of both functions to be accurate as
technology scales. First, we performed a number of ac simu-
where is the oxide capacitance per unit area, is the lations in HSPICE for a 90-nm CMOS technology using non-
overlap and fringing capacitances per unit width of the device, quasi-static (NQS) models, which are essential when simulating
is the mobility, is the voltage across the oxide, is the decaps in the gigahertz frequency range of operation. Two pa-
threshold voltage, and and are the width and length of the rameters, ACNQSMOD and TRNQSMOD, were set to “1” in
transistor, respectively. BSIM4 [13]. The circuit in Fig. 3 was used to extract the effec-
Assuming that a given filler cell has a horizontal dimension tive resistance and capacitance from HSPICE results as follows:
and vertical dimension , the channel length of each device
in a fingered layout is

(2)
where , and are the real, imagi-
where is the number of fingers and is the distance nary, and magnitude components of , respectively.
between fingers required by contact spacing rules. Modified ex- Both nMOS and pMOS decaps were simulated with
pressions for and can be derived as a function of W L sizes as follows: 15 m 5 m, 10 m 10 m,

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 MENG et al.: LAYOUT OF DECOUPLING CAPACITORS IN IP BLOCKS FOR 90-NM CMOS 1583

Fig. 4. Circuit setup to extract the effective resistance and the effective capacitance values from an ac analysis.

and 5 m 15 m. The simulation frequency ranged from 0 where [13] and .

to 10 GHz. Typical ASIC clock rates today are in the range Shown in Fig. 5 are the results of curve-fitting using (6a)
of 500 MHz to 1 GHz, but it is important to study frequency and (6b) against HSPICE for the nMOS device. The results
response well beyond the clock frequency. Most of the spectral are very close. A factor of 1/2 was applied to in order to
power density of digital signals lies within frequencies of up produce results shown in Fig. 5. That is, the equation for
to , where is a signal’s rise time (which must be adjusted by a fitting factor of 0.5 in order to obtain
can be on the order of 50 ps or less), and is the 3-dB good results. Similar results were obtained for pMOS devices.
cutoff frequency of the spectral power density [14]. We assume This demonstrates that the first-order equations for and
conservatively that 50 ps, and carry out the analysis up are reasonably accurate and, perhaps more importantly,
to 10 GHz. that can be easily computed for the metric without
The results of the simulations are shown in Fig. 4. As in- running HSPICE.
creases, there is a noticeable rolloff in the curves due to finite We now have all the necessary information to determine the
transit time effects. Devices with large L’s have a more pro- number of fingers based on the frequency response. From (6a),
nounced effect. In fact, the curve for 5 m 15 um quickly the effective capacitance in (5) at with fingers is
decays in value relative to 15 m 5 m. A general observa-
tion on nMOS and pMOS decaps can also be made: nMOS is
superior to pMOS in its high-frequency behavior since it has a
larger and a smaller at high frequencies, assuming the where
area is fixed. Although standard cells employ both nMOS and
pMOS devices for decaps, these results show that nMOS decaps
would provide better frequency response characteristics.
Based on the frequency responses of and , we pos-
To demonstrate the efficacy of the metric, we apply it to
tulated functions for modeling purposes of the form
the layout of a standard-cell decap in an available area of
(6a) 2 m 9 m. Using (5), Table I lists the metric values
for the nMOS or pMOS devices for different frequency ranges.
The optimal number of fingers corresponds to the largest entries
(6b)
in bold. For example, if the frequency range of interest is 0 to

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 1584 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008

Fig. 5. Plots of C and R for three nMOS devices (HSPICE versus model).

TABLE I
OPTIMAL NUMBER OF FINGERS FOR DIFFERENT FREQUENCY RANGES

10 GHz, then 3 nMOS fingers and 4 pMOS fingers are optimal

relative to our metric. Of course, if the range is 0 to 2 GHz, two
fingers are sufficient for both N or P devices. Note that pMOS
devices typically require one more finger than nMOS devices
at higher frequencies of operation.
Table I was shown to illustrate the use of the metric in de-
termining the optimal number of fingers. In practice, the design
process would be as follows. First, the area of a filler cell (in
particular, the -dimension of the cell) and frequency range of
operation are used as input parameters. Then, the capacitance
value as a function of is computed using (5). Finally, the value
of producing the highest capacitance is used to implement the
layout.
The results in Table I can be validated by using (3) and
(6a) to generate plots for both nMOS and pMOS
devices, as shown in Fig. 6. The results in the plot were
verified with HSPICE to ensure consistency. As an example, Fig. 6. Effective capacitance C (f ) of nMOS and pMOS decaps in 90 nm
consider the cases with 1 finger and 10 GHz. For the for different numbers of fingers in a fixed area of Y = 2 m and X = 9 m.
nMOS case in Fig. 6
190 fF 50 fF 120 fF, whereas for pMOS,
190 fF 10 fF 100 fF. Fig. 7 illustrates how standard cell layouts would be imple-
These are the same values that are found in the last row of the mented using the previous results, assuming a 10-GHz operating
table with . The rest of the table is produced in the same range. These layouts would be automatically created by a decap
manner for different values of and frequency range . filler cell generator. Two possible layouts are shown: (a) uses
By inspection, the plots indicate that three fingers would be the N and P devices and (b) is nMOS only. Fig. 9(a) uses three
optimal for nMOS decaps and four fingers would be optimal fingers for the nMOS device and four fingers for the pMOS de-
for pMOS decaps, based on the flatness of the lines and the ini- vice. From an average capacitance perspective, the nMOS-only
tial value of the capacitance. This conclusion is consistent with layout style of Fig. 9(b) is better, and this is also reflected in
Table I. However, by using the metric, designers can quickly Table I. To implement this type of layout in a standard cell, the
obtain the optimal number of fingers for a target operating fre- p-well region must be extended to cover the entire area, which
quency, without the need for such plots or SPICE simulations. is not typical of standard cell design. This approach can be used

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 MENG et al.: LAYOUT OF DECOUPLING CAPACITORS IN IP BLOCKS FOR 90-NM CMOS 1585

Fig. 7. Two sample layouts showing (a) N and P decap with four pMOS
and three nMOS fingers and (b) nMOS-only with three fingers in a 90-nm
technology.

Fig. 9. C (f ) and R (f ) comparison of fixed-area standard decap and

cross-coupled decap: same MOS device sizes but different poly connections.

Fig. 8. Cross-coupled decap schematic [12].

resistance for ESD protection in our case is a min-
imum of 500 . We increased the number of fingers to reduce
the resistance from 3500 down to that required by ESD. Ac-
as long as the design rules at the boundaries of adjacent standard cording to (4), the scale factor on the 3N-4P design can be found
cells are satisfied. as follows:

III. CROSS-COUPLED DECOUPLING CAPACITOR DESIGNS

At the 90-nm technology node, there is the possibility of
oxide breakdown during an ESD event. A simple ESD protec- Scaling the 3N-4P by approximately this amount, we produced
tion scheme for decaps is to insert a relatively large resistance in a cross-coupled 8N-9P decap. Similarly, for an ESD target
series to limit the maximum voltage seen at the gate of the decap , we find that , so we chose
[11]. A minimum is needed to ensure ESD reliability for 6N-7P. The plots for 6N-7P and 8N-9P fingers are also illus-
decap cells. A cross-coupled decap design has been proposed trated in Fig. 9. The results show that the 8N-9P cross-coupled
by cell library developers [12] to address the issue of ESD reli- version is the best configuration to address both frequency
ability. Fig. 8 illustrates the new decap wherein the drain of the response and ESD protection.
pMOS device is connected to the gate of the nMOS, and vice From a layout perspective, the cross-coupled decaps can be
versa [12]. The cross-coupled design provides additional series realized by simply rerouting the poly connections of the stan-
resistance to the inherent decap resistance to increase . dard decaps, while keeping the MOS devices the same. The lay-
The frequency response characteristics of this new configura- outs of two cases, 3N-4P and 8N-9P, are shown in Fig. 10.
tion can be evaluated to determine if the results obtained in the We addressed one other issue of thin-oxide gate leakage
last section can be applied directly to the new circuit. We first current [16] of the decap, which contributes to the chip’s total
compared a standard 3N-4P decap of Fig. 7(a) to a same-area static power. Using HSPICE, the standard and cross-coupled
cross-coupled decap using HSPICE ac analysis in Fig. 9. decap circuits were found to have almost identical gate leakage.
The standard 3N-4P decap has a very low resistance (around That is, since the cell area is fixed and only the poly terminal
30 ), which makes it prone to ESD failure. The cross-coupled connections are swapped, the cross-coupled design provides
3N-4P design has a much higher dc (around 3500 ) but no inherent savings in gate leakage as compared to the stan-
a poorer frequency response for . Consequently, the tradeoff dard design. There exists a simple design approach to save
between ESD reliability and frequency response must be con- gate leakage. Simulations using BSIM4 SPICE models [17]
sidered in the design process and decap layout. To improve the indicated that pMOS gate leakage is roughly 3 times smaller
frequency response, additional fingers must be used. The target than nMOS gate leakage for same size transistors [18], [19].

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 1586 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008

TABLE II
COMPARISON OF THE NEW DESIGNS AND THEIR GATE LEAKAGE CURRENT

Fig. 10. Sample layouts of cross-coupled decap cells for (a) 3N-4P (b) 8N-9P.

Fig. 11. Sample layouts of improved decap cells for (a) 1N-9P (b) 1N-16P.

Therefore, pMOS devices are preferred from a leakage per-

spective. Since pMOS devices have a poor frequency response,
more fingers can be used to obtain the desired result. But this
must be carried out in the context of the cross-coupled design
to preserve ESD protection.
The basic idea to control leakage is to have the smallest Fig. 12. Frequency response of various cross-coupled designs.
possible nMOS device cross-coupled with the largest possible
multi-fingered pMOS device. This way, the advantages of
pMOS leakage and cross-coupling ESD protection are pre-
the small nMOS devices, the leakage is cut in half. In fact, the
served. The layouts of two configurations are illustrated in
case with 1N-16P, the leakage is 62% less than the standard
Fig. 11. A small nMOS device is used in both cases. Note
decap 3N-4P.
the n-well regions have been expanded in both layouts to
The of the cross-coupled design must be set
accommodate the larger pMOS device. Fig. 11(a) uses 9 pMOS
based on ESD considerations, but that also controls the max-
fingers while Fig. 11(b) has a total of 16 fingers. The same cell
imum number of fingers permitted . Since the nMOS
area as before (2 m 9 m) was used for the two designs.
device is fixed while the pMOS device is multi-fingered, we
Table II summarizes the leakage values for the different cases.
use the following equation to determine the resistance:
The standard and cross-coupled 3N-4P decaps have roughly the
same leakage. It is somewhat reduced for the 8N-9P case since
there is less area for leakage. However, for the two layouts with

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 MENG et al.: LAYOUT OF DECOUPLING CAPACITORS IN IP BLOCKS FOR 90-NM CMOS 1587

where and are the resistance of the decaps without fin- REFERENCES
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Xiongfei Meng (S’06) received the B.A.Sc. and
the layout with the smallest nMOS device and a multi-fingered M.A.Sc. degrees in electrical and computer engi-
pMOS device delivers acceptable frequency response and ESD neering from the University of British Columbia,
reliability, while providing the lowest leakage. Vancouver, BC, Canada, in 2004 and 2006, respec-
tively, where he is currently pursuing the Ph.D.
degree under the supervision of Prof. R. Saleh in
electrical and computer engineering.
He is a Visiting Researcher with PMC-Sierra
ACKNOWLEDGMENT Inc., Burnaby, BC, Canada, where he works on IP
improvement and design automation. His research
interests include analog and mixed-signal VLSI
The authors would like to thank J. Chia for early work in this designs, with an emphasis on power delivery systems and power supply noise
area. control.

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 1588 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008

Resve Saleh (M’79–SM’03–F’06) received the Karim Arabi (M’94) received the B.Sc. degree
B.S. degree in electrical engineering from Carleton in electrical engineering from Tehran Polytechnic,
University in Ottawa, ON, Canada, and the M.S. Tehran, Iran, and the M.Sc. and Ph.D. degrees in
and Ph.D. degrees in electrical engineering from the electrical engineering from Ecole Polytechnique de
University of California, Berkeley. Montreal, Montreal, QC, Canada.
He is currently a Professor in the field He is Director of Engineering with Qualcomm
of system-on-chip design and test and the where he is involved in design, DFT, and method-
NSERC/PMC-Sierra Chairholder with the De- ology development. Previously, he was with
partment of Electrical and Computer Engineering, PMC-Sierra, where he was responsible for R&D ac-
University of British Columbia, Vancouver, BC, tivities in advanced technology development, design
Canada. He has published over 100 journal articles methodology enhancement, and design services. His
and conference papers. He was a founder of Simplex Solutions which devel- research interests include low-power design, power management, DFT, and
oped CAD software for deep submicrometer digital design verification. Prior mixed-signal design and test. He is program committee member of several
to starting Simplex, he spent nine years as a Professor with the Department IEEE conferences and workshops.
of Electrical and Computer Engineering, University of Illinois, Urbana. He
also taught for one year at Stanford University, Stanford, CA. He has worked
for Mitel Corporation, Ottawa, ON, Canada, Toshiba Corporation, Japan,
Tektronix, Beaverton, OR, and Nortel, Ottawa, ON, Canada. He coauthored
a book entitled Design and Analysis of Digital Integrated Circuit Design: In
Deep Submicron Technology (McGraw Hill, 2004).
Prof. Saleh was a recipient of the Presidential Young Investigator Award in
1990 from the National Science Foundation in the United States. He is a Profes-
sional Engineer of British Columbia. He served as general chair (1995), confer-
ence chair (1994), and technical program chair (1993) for the Custom Integrated
Circuits Conference. He held the positions of Technical Program Chair, Confer-
ence Chair and Vice-General Chair of the International Symposium on Quality
in Electronic Design (2001), and has served as Associate Editor of the IEEE
TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND
SYSTEMS.

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