Module-4

Faults in digital circuits:

• Failures and faults,
• Modelling of faults,
• Temporary faults
Test generation for combinational logic circuits:
• Fault diagnosis of digital circuits,
• Test generation techniques for combinational circuits,
• Detection of multiple faults in combinational logic circuits.
(1.1 to 1.3, 2.1 to 2.3 of TEXT3)
1.1 Failures and Faults

• A failure is said to have occurred in a circuit or system if it deviates from its

specified behaviour .
• A fault, on the other hand, is a physical defect that may or may not cause a
failure.
• A fault is characterized by its nature, value, extent, and duration [1.2].
• The nature of a fault can be classified as logical or non logical.
• A logical fault causes the logic value at a point in a circuit to become opposite
to the specified value.
• Nonlogical faults include the rest of the faults, such as the malfunction of the
clock signal, power failure, and so forth.
• The value of a logical fault at a point in the circuit indicates whether the fault
creates fixed or varying erroneous logical values.
• The extent of a fault specifies whether the effect of the fault is localized or
distributed.
• A local fault affects only a single variable, whereas a distributed fault affects
more than one.
1.2 Modeling of Faults

• Faults in a circuit may occur due to defective

components, breaks in signal lines, lines
shortened to ground or power supply, short-
circuiting of signal lines, excessive delays, and
so forth.
• Besides errors or ambiguities in design
specifications, design rule violations, among
other things, also result in faults.
1.2 Modeling of Faults

In general, the effect of a fault is represented by means of a

model, which represents the change the fault produces in
circuit signals.
The fault models in use today are
1. Stuck-at fault
2. Bridging fault
3. Stuck-open fault
1.2.1 STUCK-AT FAULTS

• The most common model used for logical faults is

the single stuck-at fault.
• It assumes that a fault in a logic gate results in one
of its inputs or the output being fixed to either a
logic 0 (stuck-at-0) or a logic 1 (stuck-at-1).
• Stuck-at-0 and stuck- at-1 faults are often
abbreviated to s-a-0 and s-a-1, respectively, and
these abbreviations will be adopted here.
 1.2.1 STUCK-AT FAULTS

• Let us consider a NAND gate with

input A s-a-1 (Fig. 1.1).
• The NAND gate perceives the
input A as a 1 irrespective of the
logic value placed on the input.
• The output of the NAND gate in
Fig. 1.1 is 0 for the input pattern
shown, when the s-a-1 fault is
present.
• The fault-free gate has an output
of 1.
• Therefore, the pattern shown in
Fig. 1.1 can be used as a test for
the A input s-a-1, because there
is a difference between the
output of the fault-free and the
faulty gate.
 1.2.1 STUCK-AT FAULTS
• The numbers 1, 2, 3, and 4 indicating places where opens have
occurred.
• The numbers 5 and 6 identify the short between the output node
and the ground, and the short between the output node and the
VDD, respectively.
• A short in a CMOS results if not enough metal is removed by the
photolithography, whereas over removal of metal results in an open
circuit .
1.2.1 STUCK-AT FAULTS
1.2.2 BRIDGING FAULTS
• With the increase in the number or devices on the VLSI chips,
the probability of shorts between two or more signal lines has
been significantly increased.
• Unintended shorts between the lines form a class of permanent
faults, known as bridging faults, which cannot be modeled as
stuck-at faults.
• It has been observed that physical defects in MOS (Metal Oxide
Semiconductor) circuits are manifested as bridging faults more
than as any other type of fault.
• Bridging faults can be categorized into three groups:
1. Input bridging
2. Feedback bridging
3. Nonfeedback bridging
• An input bridging fault corresponds to the
shorting of a certain number of primary input
lines (Fig. 1.5), whereas a feedback bridging
fault occurs if there is a short between an
output line to an input line (Fig. 1.6).
• A nonfeedback bridging fault identifies a
bridging fault that does not belong to either
of the two previous categories.
1.2.3 BREAKS AND TRANSISTOR STUCK-ON/-OPEN
FAULTS IN CMOS
• As discussed previously, not all defects in CMOS VLSI can be
represented by using the stuck-at fault model.
• Recent research indicates that breaks and transistor stuck ons
are two other types of defects that, like bridging, may remain
undetected if testing is performed based on the stuck-at fault
assumption.
• These defects have been found to constitute a significant
percentage of defects occurring in CMOS circuits.
• In the following two subsections, we discuss the effects of these
defects on CMOS circuits.
Breaks
Breaks or opens in CMOS circuits are caused either by
missing conducting material or extra insulating material.
Breaks can be either of the following two types:
1. Intragate breaks
2. Signal line breaks
1.2.4 DELAY FAULTS
• As mentioned previously, not all manufacturing defects in VLSI
circuits can be represented by the stuck-at fault model.
• The size of a defect determines whether the defect will affect the
logic function of a circuit.
• Smaller defects, which are likely to cause partial open or short in
a circuit, have a higher probability of occurrence due to the
statistical variations in the manufacturing process.
• These defects result in the failure of a circuit to meet its timing
specifications without any alteration of the logic function of the
circuit.
• A small defect may delay the transition of a signal on a line either
from 0 to 1, or vice versa.
• This type of malfunction is modeled by a delay fault.
Two types of delay faults have been proposed in literature:
1. Gate delay fault
2. Path delay fault
 Gate delay faults have been used to model defects that cause the
actual propagation delay of a faulty gate to exceed its specified
worst case value.
For example, if the specified worst case propagation delay of a gate is
x units, and the actual delay is x + Ax units, then the gate is said to
have a delay fault of size Ax.
 The path delay fault model can be used to model isolated as well as
distributed defects. In this model, a fault is assumed to have occurred
if the propagation delay along a path in the circuit under test exceeds
the specified limit.
Temporary faults

• A major portion of digital system malfunctions are

caused by temporary faults .
• These faults have also been found to account for more
than 90% of the total maintenance expense, because
they are difficult to detect and isolate.
• In the literature, temporary faults have often been
referred to as intermittent or transient faults with the
same meaning.
• It is only recently that a distinction between the two
types of faults has been made.
• Transient faults are nonrecurring temporary faults. They are usually
caused by a-particle radiation or power supply fluctuation, and they
are not repairable because there is no physical damage to the
hardware. They are the major source of failures in semiconductor
memory chips.
• Intermittent faults are recurring faults that reappear on a regular
basis. Such faults can occur due to loose connections, partially
defective components, or poor designs.
• Intermittent faults occurring due to deteriorating or aging
components may eventually become permanent. Some intermittent
faults also occur due to environmental conditions such as
temperature, humidity, vibration, and so forth.
• The likelihood of such intermittents depends on how well the system
is protected from its physical environment through shielding,
filtering, cooling, and so on. An intermittent fault in a circuit causes a
malfunction of the circuit only if it is active; if it is inactive, the circuit
operates correctly. A circuit is said to be in a fault- active state if a
fault present in the circuit is active, and it is said to be in the fault-
 An intermittent fault is well behaved if, during an application of a test pattern, the
circuit under test behaves as if either it is fault-free or a permanent fault exists. An
intermittent fault is signal independent if its being active does not depend on the
inputs or the present state of a circuit. Figure 1.11 shows the fault model proposed by
Breuer. It assumes that the fault oscillates between the fault-active state (FA) and the
fault-not-active state (FN). The transition proba- bilities indicated in Fig. 1.11 depend
on a selected time-step; they have to be changed if this time-step is changed. Lala and
Hopkins [1.33] used an adaptation
In this model, shown in Fig. 1.12, the transition probabilities depend linearly
on the time-step At.
For example, if a circuit is in the fault-not- active (FN) state at time t, the
probability that it will go to the fault-active (FA) state at time t + At is
proportional to At. If a constant of proportionality λ is assumed, then this
probability is given by λ At.
Similarly the probability for going from FA state at time t to FN state at time
t + At is μ At.
The time-period during which a circuit stays in state FA (FN) is exponentially
distributed with mean 1/μ (1/A). When the time-step At is very large, the
continuous Markov model reduces
The major problem with the intermittent fault models discussed so far is that it is very
hard to obtain the statistical data needed to verify their validity.
It consists of five states (Fig. 1.13). States A and B are the fault-active and the benign
state, respectively.
If a fault occurs, the error state E is entered. D is a fault-detected state, and F is a failed
state resulting from the propagation of an undetected error.
a(t) represents the probability of transition from the fault-active to the benign state. B(t)
is the rate of occurrence of the transition from the benign state to the fault-active state.
p(t), y(t, and e(t) denote respectively the rates of occurrence of error generation, fault
detection, and error propagation. Each of these transition functions is a function only of
the time t, spent in the source state. The parameter C represents the coverage
probability, which is the probability of detecting an error before it causes any damage.
 Test generation for combinational logic circuits

2.1 Fault Diagnosis of Digital Circuits

• When a circuit ultimately does develop a fault, it has to be
detected and located so that its effect can be removed.
• Fault detection means the discovery of something wrong in a
digital system or circuit. Fault location means the identification
of the faults with components, functional modules, or
subsystems, depending on the requirements.
• Fault diagnosis includes both fault detection and fault location.
• Fault detection in a logic circuit is carried out by applying a
sequence of test inputs and observing the resulting outputs.
• One of the main objectives in testing is to minimize the length
of the test sequence.
 Test generation for combinational logic circuits

• Any fault in a nonredundent n-input combinational circuit can be

completely tested by applying all 2" input combinations to it;
however, 2 increases very rapidly as n increases.
• For a sequential circuit with n inputs and m flip-flops, the total
number of input combinations necessary to test the circuit
exhaustively is 2" x 2" = 2"+".
• If, for example, n = 20, m = 40, there would be 260 tests. At a rate
of 10,000 tests per second, the total test time for the circuit would
be about 3 million years! Fortunately, a complete truth-table
exercise of a logic circuit is not necessary-only the number of input
combinations that detect most of the faults in the circuit is
required.
 Test generation for combinational logic circuits
For example, if a circuit has x stuck-at faults, then fault simulation is
the process of applying every test pattern to the fault-free circuit, and
to each of the x copies of the circuit containing exactly one stuck-at
fault.
When all test patterns have been simulated against all the faults x, the
detected faults ƒ are used to compute the fault coverage (f.) which is
defined as

• Instead of simulating one fault at a time, the method of parallel

simulation, which uses the word size N of a host computer to
process N faults at a time, can be employed.
• It has been shown that the time required to compute test patterns
for a combinational circuit grows in proportion to the square of the
number of gates in the circuit. Hence, for circuits of VLSI
complexity the computation time required for test generation is
often unacceptably high.
2.2 Test Generation Techniques for Combinational
Circuits
• There are several methods available for deriving tests for
combinational circuits.
• All these methods are based on the assumption that the circuit
under test is non- redundant and only a single stuck-at fault is
present at any time.

2.2.1 ONE-DIMENSIONAL PATH SENSITIZATION

• The basic principle involved in path sensitizing is to choose some path from
the origin of the failure to the circuit output.
• The path is said to be "sensitized" if the inputs to the gates along the path are
assigned values so as to propagate the fault along the chosen path to the
output [2.3].
2.2.3 D-ALGORITHM
• The D-algorithm is the first algorithmic
method for generating tests for non
redundant combinational circuits [2.7].
• If a test exists for detecting a fault, the
D-algorithm is guaranteed to find this
test.
• Before the D-algorithm can be discussed
in detail, certain new terms must be
defined.
The D algebra
• .
The D-algebra is a 5-value logic consisting of logic: 1, 0, D, D', X
• The D stands for Discrepancy, as discussed in the path sensitization
method.

Terminologies in D Algorithm
1.Singular cover
2.D intersection
3.Primitive D cube for a fault ( pdcf)
4.Propagation D cubes ( pdc)
1.Singular cover
1.Singular cover

The singular cover of an AND gate.

Each row of a singular cover is termed as Singular Cube. The above

singular cover of the AND gate has three singular cubes.
1.Singular cover
Propagation D-cube

• Propagation D-cubes (PDCs) of a gate causes the output of

the gate to depend upon the minimum number of its
specified inputs.
• It is used to propagate D or D’ from a specified input to the
output.
• Propagation D-Cubes can be derived from the intersection of
singular cubes of gates of opposite output values.
Example:
Here’s the truth table of an OR gate. To generate the PDC, we
find the singular cover for the OR gate.

Now, we intersect the singular cubes of every possible combination(s) with opposite
output values. Intersecting the singular cubes of row2 and row1, also row3 and row1
serves the purpose.

{1, x, 1} ∩ {0, 0, 0} = {1 ∩ 0, x ∩ 0, 1 ∩ 0} = {D’, 0, D’}

{x, 1, 1} ∩ {0, 0, 0} = {x ∩ 0, 1 ∩ 0, 1 ∩ 0} = {0, D’, D’}
Primitive D-cube of a Fault (PDCF) is used to specify the minimum
input conditions required at inputs of a gate to produce an error at
its output. This is used for fault activation. PDCF can be derived
from the intersection of singular covers of gates in faulty and non-
faulty conditions having different outputs.

Example:
Here is an AND gate with s-a-0 fault at the output. To generate the
PDCF, we first draw the truth table of the faulty and non-faulty
circuit. Next, we derive the singular cover for faulty as well as non-
faulty circuits.
For faulty AND gate, the output is always stuck-at-0 independent
of its input; hence its singular cover has only one row with inputs
(a, b) as don’t cares.
Now, we intersect the singular cubes of the non-faulty and faulty
circuits. For PDCF we need to intersect only those columns for
which output is different for non-faulty and faulty circuits.
Since for faulty circuits, we only have one singular cube {x, x, 0}; we
need to intersect it with a singular cube of the non-faulty circuit
having the opposite output value (i.e. logic-1).
The singular cube {1, 1, 1} perfectly fits this criterion.
{x, x, 0} ∩ {1, 1, 1} = {1 ∩ x, 1 ∩ x, 1 ∩ 0} = {1, 1, D}
Finally, PDCF of this faulty AND gate is {a, b, out} = {1, 1, D}.
 D-algorithm
1. Choosing a primitive D-cube of the fault under
consideration.
2. To sensitize all possible paths from the faulty gate to a
primary output of the circuit; this is done by successive
intersection of the primitive D-cube of the fault with the
propagation D-cubes of successor gates. The procedure
is called the D-drive. The D-drive is continued until a
primary output has a D or D(bar).
3. The consistency operation, which is performed to
develop a consistent set of primary input values that will
account for all lines set to 0 or 1 during the D-drive.
Refer text book :
Detection of multiple faults in
combinational logic circuits.