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17 views2 pages

Resume Template

Uploaded by

Sachin S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Ratn Nabh Sharma

+91-9980589302 | [email protected]

Highly motivated Alumni of Indian Institute of Science - IISc, Bangalore with a master’s degree in
electronic systems. Possesses fundamentals in digital logic design, CMOS VLSI design, Design For
Testability etc.

TECHNICAL SKILLS

● Design For Testability


o Scan Insertion
o DRC Analysis during Scan Insertion
o Scan Compression (EDT)
o ATPG Pattern Generation in Compressed mode and Bypass Mode
o Coverage Analysis and Improvement
o On-Chip Clock Controller
o Scan Pattern Simulation
o JTAG and Boundary Scan
o MBIST Insertion
● Digital Design
o Combinational and Sequential Circuit Design
o Basics of Verilog HDL
● Basics of Static Timing Analysis

Software Skills:
● Automation Languages: TCL
● Operating Systems: Linux and Windows
● HDL: Verilog
● Text Editor: GVIM
● EDA Packages: Tessent (Scan, TestKompress, MBIST), QuestaSim and DesignCompilers

EXPERIENCE
VLSIGURU Training Institute Bengaluru June 2024 to Dec 2024
 Completed 6 months Design for Testability (DFT) Course
 During course time Gained more Knowledge in Digital Electronics, CMOS and DFT advance Topics.

Intel Technology India Pvt. Ltd. July. 2018 – Dec. 2018


Job Title: Core Digital Design Engineer Bengaluru, India
 Scan Chain Implementation: Participating in the implementation of scan chains, ensuring proper insertion
and optimization for efficient testing.
 Block Level ATPG Pattern Generation and Simulations
 Memory Built-In Self-Test (MBIST): Implementation and Simulations

INSTITUTE PROJECTS
Projects (DFT Related)
MBIST and Scan Insertion on 2 small designs
Design 1 (Communication Chip):
 Worked on small Hierarchical designs consisting of a Parent and multiple Child cores with flop count of
~4K. Performed MBIST Insertion, Scan Stitching and DRC Cleanup, EDT and OCC Insertion.
 Worked on ATPG Coverage analysis, Pattern generation and Serial & Parallel Scan pattern Simulation.
Design 2 (Navigation Chip):
 Worked on small design with flop count ~42K. Performed MBIST insertion, Scan Stitching and DRC
cleanup, EDT and OCC Insertion. Worked on ATPG Coverage analysis.

M. Tech: SOLVING DIFFERENTIAL EQUATION USING FPGA June 2017 – June 2018
 The continuous physical domain is discretized into a discrete finite difference grid in order to
approximate the individual exact partial derivatives in the ODE by algebraic finite difference
approximations, then the approximations are substituted into the PDE to form a set of algebraic finite
difference equations and, finally, the resulting algebraic equations are solved.
 FDM can be mapped onto an FPGA-based reconfigurable computing platform. Finite Difference
Method followed by the Thomas algorithm is one of the best methods to implement on FPGA

COURSES STUDIED
 Digital VLSI circuits
 Analog VLSI circuits
 Electronic Circuit Design
 Electronic Packaging
 Digital system design with FPGA’s

EDUCATION
Indian Institute of Science - IISc, Bangalore Bangalore, Karnataka
Master of Technology in Electronic Systems Engineering (CEDT) Aug 2016 - Jun 2018
Dayalbagh Educational Institute Agra, Uttar Pradesh
Bachelor of Technology in Electrical Engineering July 2012 - June2016

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