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Venus Microprocessor & Microcontroller 1

Model Set-1 (a) Jump to an absolute address

(b) Short jump to a relative address
(c) Call a subroutine
Microprocessor & Microcontroller (d) Jump if zero
Ans.(b)
Group-A (ix) Which instruction is used to perform a logical AND
1. Choose the most suitable answer from the following operation?
options: (a) ORL (b) ANL
(i) Which of the following is an improvement of the (c) CPL (d) ADD
8085 over the 8080? Ans.(b)
(a) 16-bit architecture (x) What is the primary function of the Accumulator
(b) On-chip clock generator (ACC) in the 8051 microcontroller?
(c) Increased number of general-purpose registers (a) Store the program counter
(d) None of the above (b) Perform arithmetic and logic operations
Ans.(b) (c) Control interrupts
(ii) What is the size of the address bus in the 8085 (d) Manage external memory access
microprocessor? Ans.(b)
(a) 4 bits (b) 8 bits (xi) Which of the following pins is used to reset the 8051
(c)16 bits (d) 32 bits microcontroller?
Ans.(c) (a) PSEN (b) RST
(iii)The accumulator in the 8085 microprocessor is used (c) ALE (d) EA
for : Ans.(b)
(a) Temporary data storage (xii) The 8051 microcontroller has how many I/O ports?
(b) Control signals (a) 2 (b) 4 (c) 8 (d) 16
(c) Addressing modes Ans.(b)
(d) None of the above (xiii)What is a microcontroller primarily used for?
Ans.(a) (a) General-purpose computing
(iv) Which pin is used to indicate that the 8085 is ready (b) Embedded control applications
to communicate with a peripheral? (c) High-performance gaming
(a) ALE (b) READY (d) Scientific simulations
(c) IO/M (d) RD Ans.(b)
Ans.(b) (xiv)Which architecture uses separate memory for data
(v) What does the IO/M signal indicate? and instructions?
(a) Memory operation (a) Von Neumann (b) Harvard
(b) I/O operation (c) RISC (d) CISC
(c) Both memory and I/O operations Ans.(b)
(d) None of the above (xv) Which of the following microcontrollers is part of
Ans.(c) the 8051 family?
(vi) What does the MOV instruction do in the 8051 (a) PIC16F877 (b) AT89S51
microcontroller? (c) ARM Cortex-M3 (d) MSP430
(a) Moves data from the accumulator to a register Ans.(b)
(b) Moves data between registers or memory locations (xvi) What does the address bus in a microcomputer do?
(c) Moves data from the stack to the accumulator (a) Carries data between components
(d) Moves data from one external device to another (b) Carries control signals
Ans.(b) (c) Specifies the memory location of data
(vii) Which of the following addressing modes uses the (d) Regulates power supply
operand directly in the instruction? Ans.(c)
(a) Direct Addressing (b) Register Addressing (xvii) Which of the following is NOT an I/O port of the
(c) Immediate Addressing 8051?
(d) Register Indirect Addressing (a) P0 (b) P1 (c) P4 (d) P3
Ans.(c) Ans.(c)
(viii)What is the purpose of the SJMP instruction? (xviii)In which mode does Timer 0 operate as a 13-bit
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timer? microprocessor is used to distinguish between the ad-
(a) Mode 0 (b) Mode 1 dress and data portions of a multiplexed address/data
(c) Mode 2 (d) Mode 3 bus.
Ans.(a) Here’s how it works :
(xix)What is the purpose of the TMOD register? (i) The lower 8 bits of the 16-bit address (A0–A7) are mul-
(a) To control the serial communication mode tiplexed with the data bus (D0–D7). This means that
(b) To configure the timer modes the same set of lines are used to carry both addresses
(c) To enable interrupts and data at different times during a machine cycle.
(d) To control power saving modes (ii) During the first part of the machine cycle, these lines
Ans.(b) carry the lower 8 bits of the address (A0–A7).
(xx) In 8051 serial communication, what does SCON (iii) The ALE signal is used to indicate that the information
stand for? on the bus at that time is an address. It goes high during
(a) Serial Control the initial part of the cycle when the address is present
(b) Serial Configuration on the multiplexed bus.
(c) Serial Communication Operation (iv) External circuitry, typically a latch, is used to capture
(d) Serial Control Register and hold the lower byte of the address when ALE is
Ans.(d) high. After that, the same lines (AD0–AD7) are used
Group-B for data transfer, and the ALE signal goes low.
Answer all Five Questions. [ 4 x 5 = 20 ]
Q2.Explain the role of the accumulator in the 8085 mi- Q4.Define a bus in the context of a microcomputer, and
croprocessor. explain the different types of buses used in a
Ans.In the 8085 microprocessor, the accumulator plays a microcontroller.
central role in arithmetic, logic, and data transfer op- Ans.In the context of a microcomputer, a bus is a communi-
erations. It is an 8-bit register, labeled as A, and is inte- cation system that transfers data between components
gral to performing operations and storing results. Here inside the computer, or between computers. It can be
are its key roles : thought of as a set of physical connections (wires, traces)
(i) Arithmetic Operations : The accumulator is used in and a protocol that define how data moves from one
addition, subtraction, increment, and decrement opera- part of the system to another. Buses play a critical role
tions. For example, when you add two numbers, one in connecting the microcontroller's central processing
operand is usually in the accumulator, and the result of unit (CPU) with memory, input/output devices, and other
the addition is stored back in it. peripherals.
(ii) Logic Operations : Logical operations such as AND, Types of Buses in a Microcontroller
OR, XOR, and complement operations are performed 1. Data Bus :
using the accumulator. After performing these opera- The data bus carries the actual data being transferred
tions, the result is also stored in the accumulator. between components. Its width (number of lines)
(iii)Data Transfer : The accumulator is involved in data determines how much data can be transferred at once
transfer operations where data is moved between (e.g., 8-bit, 16-bit, 32-bit).
memory, registers, or I/O ports and the accumulator. 2. Address Bus :
(iv) Immediate and Direct Instructions : Many The address bus carries the addresses of where data
instructions in the 8085 microprocessor are designed should be read from or written to in memory. The width
specifically to work with the accumulator. For instance, of the address bus determines the maximum address-
instructions like `ADI`, `ANI`, `SUI`, etc., directly able memory space (e.g., a 16-bit address bus can
involve the accumulator. address 2^16 memory locations).
(v) Interaction with ALU : The accumulator works in con- 3. Control Bus :
junction with the Arithmetic Logic Unit (ALU) of the The control bus carries control signals that manage the
microprocessor. During an operation, the ALU uses the operations of the microcontroller. These signals
data in the accumulator as one of the operands and stores indicate whether the data is being read or written and
the result back in the accumulator after processing. synchronize actions among different components.
OR 4. Peripheral Bus :
Q2.What is the purpose of the ALE signal in the 8085 This type of bus connects peripheral devices (like
microprocessor? sensors, displays, etc.) to the microcontroller. Examples
Ans.The ALE (Address Latch Enable) signal in the 8085 include I2C, SPI, and UART, which are used for
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specific communication tasks. (i) Crystal Oscillator: The 8051 typically uses a crystal
5. Expansion Bus : oscillator to generate a stable clock frequency. This crys-
An expansion bus allows additional hardware compo- tal is connected between the oscillator pins (usually
nents or modules to be added to the microcontroller XTAL1 and XTAL2) of the microcontroller. The fre-
system, facilitating scalability and customization. quency of the crystal directly influences the clock speed
OR of the 8051.
Q3.Compare and contrast the Von Neumann and (ii) Clock Frequency: The clock frequency (f_clk) is de-
Harvard architectures. fined by the crystal's specifications, which can range
Ans.Refer to Chapter 2 of Venus Publication Question from a few MHz to tens of MHz. For example, a 12
Bank MHz crystal will generate a clock frequency of 12 mil-
lion cycles per second.
Q4.What is the difference between external interrupts (iii)Machine Cycle: The 8051 microcontroller uses machine
and timer interrupts in the 8051? cycles, which are defined by the internal architecture.
Ans.External Interrupts Each machine cycle consists of a certain number of clock
(i) Source: External interrupts are generated by external cycles. In the 8051 architecture:
devices or signals. In the 8051, there are typically two  1 machine cycle = 12 clock cycles for most instruc-
external interrupts, labeled INT0 (External Interrupt 0) tions.
and INT1 (External Interrupt 1).  This means that for a crystal frequency of 12 MHz, the
(ii) Triggers: These interrupts can be triggered by specific duration of one clock cycle is
events, such as a change in the state of a pin (for ex- 1 1
ample, a rising or falling edge). The triggering condi-  seconds, or approximately 83.3
12MHz 12,000,000
tions can often be configured (edge-triggered or level-
triggered). nanoseconds.
(iii)Usage: They are used to handle events that require im- (iv) Instruction Cycle: Each instruction in the 8051 takes a
mediate attention, such as input from sensors, user in- specific number of machine cycles to execute. For ex-
puts (like button presses), or signals from other devices. ample:
(iv) Prioritization: External interrupts can be prioritized  Simple instructions like MOV might take 1 machine
with the use of interrupt enable and priority control reg- cycle.
isters.  More complex instructions could take 2 or more ma-
Timer Interrupts chine cycles.
(i) Source: Timer interrupts are generated by the internal (v) Instruction Cycle Time Calculation: The instruction
timers (Timer 0 and Timer 1) of the 8051. These timers cycle time can be calculated by multiplying the number
can be configured to count clock pulses or generate of machine cycles required for the instruction by the
delays. duration of a machine cycle:
(ii) Triggers: Timer interrupts are typically triggered at Instruction Cycle Time =
regular intervals, based on the timer's configuration  12 
(mode and count value). When the timer overflows or  Number of Machine Cycles   
reaches a specified count, it generates an interrupt.  f clk 
(iii)Usage: These interrupts are commonly used for timing For example, if an instruction takes 2 machine cycles
operations, generating delays, or creating time-based at a clock frequency of 12 MHz:
events in applications like periodic data sampling or Instruction Cycle Time} = 2  12 cycles  83.3 ns 
generating PWM signals. 200 ns
(iv) Prioritization: Timer interrupts can also be prioritized,
and they may have different priorities compared to ex- Q5.What is the purpose of the MOV instruction in the
ternal interrupts. 8051 microcontroller? Can you provide an example?
OR Ans.The MOV instruction in the 8051 microcontroller is
Q4.How does the clock circuit in the 8051 determine the used to transfer data from one location to another. This
instruction cycle time? can include moving data between registers, from a reg-
Ans.The instruction cycle time in the 8051 microcontroller ister to a memory location, or from a memory location
is determined by its clock circuit, which operates based to a register. The MOV instruction is fundamental in
on a crystal oscillator connected to the microcontroller. programming the 8051 as it allows manipulation and
Here's how it works: organization of data within the microcontroller.
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Purpose of the MOV Instruction (iv) Use Case: LJMP is useful when the target address is
(i) Data Transfer: It facilitates the transfer of data between outside the range of SJMP, allowing for more flexible
registers and memory locations. program structure and organization.
(ii) Initialization: It can be used to initialize registers or When to Use Each
memory locations with specific values. Use SJMP when:
(iii)Data Manipulation: It allows for temporary storage of  The target address is within the -128 to +127 byte range
values during calculations or operations. of the current location.
Example of MOV Instruction:Here's a simple example  We want to save memory space in applications where
that illustrates the use of the MOV instruction: many jumps occur within a local range.
Example: Move immediate value to a register and then Use LJMP when:
to a memory location  The target address is outside the short jump range.
MOV A, #25h ; Move the immediate value 25h (37  We need to branch to a different section of the program
in decimal) into the accumulator (A) that could be located anywhere in the program memory.
MOV 30h, A ; Move the value in the accumulator
(A) to the memory address 30h Q6.What are the different modes of operation for the
Explanation: 8051 timers?
(i) MOV A, #25h: This instruction moves the immediate Ans.Refer to Chapter 5 of Venus Publication Question
value `25h` into the accumulator (register A). Bank
(ii) MOV 30h, A`: This instruction moves the contents of OR
the accumulator (which is now `25h`) into the memory Q5.Explain the role of the IO/M signal in differentiat-
location `30h`. ing between I/O and memory operations.
This way, the MOV instruction enables effective data Ans.The IO/M (Input/Output/Memory) signal is crucial in
handling in the 8051 microcontroller. microprocessors for distinguishing between memory
OR operations and I/O operations during instruction
Q5. Explain the difference between the SJMP and LJMP execution. Here’s how it works:
instructions. When would you use each? Memory Operations :
Ans.In assembly language programming, particularly in  When the processor executes an instruction that involves
microcontroller architectures like the Intel 8051, the accessing memory (such as fetching an instruction or
SJMP (Short Jump) and LJMP (Long Jump) instruc- reading/writing data), the IO/M signal is set to low (0).
tions are used to control the flow of execution. Here’s a  This indicates that the current operation is targeting
breakdown of the differences between them: memory addresses in the system.
SJMP (Short Jump)  For example, in a read or write instruction involving
(i) Definition: SJMP is a relative jump instruction that al- RAM, the IO/M signal helps the control unit recognize
lows the program to jump to a destination within a lim- that the memory space is being accessed.
ited range. I/O Operations :
(ii) Addressing Mode: It can only jump to an address that  When the processor communicates with external input/
is within a specified range of the current program counter output devices (such as reading from a keyboard or
(PC). Typically, this range is -128 to +127 bytes from writing to a display), the IO/M signal is set to high (1).
the address following the SJMP instruction.  This tells the system that the current operation is
(iii)Size: The instruction size is 2 bytes (1 byte for the targeting I/O ports instead of memory.
opcode and 1 byte for the offset).  This signal is important because I/O devices are
(iv) Use Case: SJMP is used when the target address is typically mapped to different address ranges than
within the range, which helps save space in the pro- memory, and differentiating between them ensures the
gram memory. correct devices are accessed.
LJMP (Long Jump) Group-C
(i) Definition: LJMP is an absolute jump instruction that Answer all Five Questions. [ 6 x 5 = 30 ]
allows the program to jump to any address within the Q7.What are the main functions of each of the 8051's I/
program memory. O ports?
(ii) Addressing Mode: It can jump to any address in the Ans.The 8051 microcontroller has four parallel I/O ports,
program memory (0x0000 to 0xFFFF). labeled Port 0, Port 1, Port 2, and Port 3. Each port has
(iii)Size: The instruction size is 3 bytes (1 byte for the specific functions:
opcode and 2 bytes for the target address). (i) Port 0 (P0.0 - P0.7)
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 General Purpose I/O: Can be used as an input or out- memory. After fetching the instruction, the PC is auto-
put port. matically incremented to point to the next memory lo-
 Open-Drain Output: When used as output, it requires cation (the next instruction).
external pull-up resistors. (ii) Jump, Call, and Interrupt Handling : In cases of jump,
 External Memory Interface: In the context of external call, or interrupt instructions, the PC is updated to the
memory access, Port 0 serves as the lower 8 bits of the new memory address provided by the instruction, al-
address bus and data bus. It is used to access external lowing the program to continue execution from the new
data memory and program memory. address.
(ii) Port 1 (P1.0 - P1.7) (iii) Program Control : The PC ensures that instructions
 General Purpose I/O: Functions primarily as a stan- are executed in the correct sequence by fetching them
dard I/O port for input and output. one by one from memory, unless an instruction (such as
 Pull-up Resistors: Port 1 has internal pull-up resistors, a jump or a branch) alters the flow.
allowing it to be used without external components. Example : If the PC holds the address `2000H`, it will
(iii) Port 2 (P2.0 - P2.7) fetch the instruction from memory location `2000H` and
 General Purpose I/O: Like Port 1, it can function as then increment to `2001H` to fetch the next instruction.
an I/O port. Stack Pointer (SP) : The Stack Pointer is used to keep
 High Order Address Bus: Port 2 serves as the higher 8 track of the top of the stack. The stack is a special re-
bits of the address bus when accessing external memory gion of memory used for temporary data storage, typi-
(addresses A8 to A15). cally during subroutine calls or when handling inter-
(iv) Port 3 (P3.0 - P3.7) rupts. The key functions of the Stack Pointer include:
 General Purpose I/O: Can also be used as an input or (i) Stack Management : The SP holds the address of the
output port. last element placed on the stack. It points to the top of
Special Functions: the stack in memory, which is organized in a Last In,
 P3.0: RXD (Receive Data Input) – used for serial First Out (LIFO) manner.
communication (UART). (ii) Push and Pop Operations : During push operations
 P3.1: TXD (Transmit Data Output) – used for serial (storing data onto the stack), the SP is decremented
communication (UART). (since the stack grows downward in memory), and the
 P3.2: INT0 – External interrupt 0 input. data is stored at the memory location pointed to by the
 P3.3: INT1 – External interrupt 1 input. SP. During **pop** operations (retrieving data from
 P3.4: T0 – Timer 0 external input. the stack), the SP is incremented after the data is
 P3.5: T1 – Timer 1 external input. retrieved.
 P3.6: WR – External data memory write control sig- (iii)Subroutine and Interrupt Handling : When a subrou-
nal. tine or an interrupt occurs, the address of the next
 P3.7: RD – External data memory read control sig- instruction to be executed is stored on the stack, and
nal. the SP is updated accordingly. Upon returning from the
OR subroutine or interrupt, the address is popped from the
Q7.What are the different types of interrupts available stack, allowing the program to resume execution from
in the 8051? where it left off.
Ans.Refer to Chapter 5 of Venus Publication Question Example : If the SP holds `3000H`, it means the top of
Bank the stack is at memory address `3000H`. After a push
operation, the SP would be decremented to `2FFFH`.
Q8. What is the function of the Program Counter (PC) OR
and Stack Pointer (SP) in 8085? Q8.Describe the architecture of the 8085 microproces-
Ans.In the 8085 microprocessor, both the Program Counter sor and its main components.
(PC) and the Stack Pointer (SP) are critical 16-bit Ans.Refer to Chapter 1 of Venus Publication Question
registers that manage the flow of execution and memory Bank
access. Their functions are as follows :
Program Counter (PC) : The Program Counter keeps Q9.What are the advantages of using a Harvard archi-
track of the address of the next instruction to be tecture in microcontrollers over the Von Neumann
executed in the program. Its main functions are: architecture?
(i) Instruction Sequencing : The PC holds the memory Ans.The Harvard architecture offers several advantages over
address of the next instruction to be fetched from the Von Neumann architecture, particularly in the
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context of microcontrollers : 6. Interrupts : Supports five interrupt sources, allowing
1. Separate Memory Spaces : Harvard architecture has responsive handling of external events.
separate memory areas for instructions and data, 7. Clock Speed : Typically operates at 12 MHz, but varia-
allowing simultaneous access. This can lead to faster tions exist in modern implementations.
execution since instruction fetching and data process- 8. Instruction Set : Has a rich instruction set, including
ing can occur at the same time. arithmetic, logical, data transfer, and control instruc-
2. Increased Performance : Because of the dual memory tions.
paths, Harvard architecture can achieve higher through- 9. Serial Communication : Provides built-in support for
put and efficiency, especially in applications requiring serial communication through a UART.
high-speed data processing. 10. Variants : There are many variants of the 8051, offering
3. Optimized for Specific Tasks : The separation of in- features like additional memory, enhanced I/O capabili-
struction and data memory allows for optimization in ties, and specialized functions for specific applications.
both areas. For example, instruction memory can be These features make the 8051 microcontroller family
designed for high-speed fetching, while data memory popular in consumer electronics, industrial automation,
can be tailored for efficient data manipulation. and other embedded systems.
4. Reduced Bottlenecks : The potential for bottlenecks
seen in Von Neumann architecture (where both instruc- Q10.Describe the immediate addressing mode with an
tions and data share the same bus) is minimized, example. How does it differ from direct addressing?
improving overall system performance in many Ans.Refer to Chapter 4 of Venus Publication Question
scenarios. Bank
5. Security and Reliability : With separate memory spaces, OR
it can be easier to implement certain security measures Q10.What is the function of the PUSH and POP instruc-
and error-checking mechanisms, enhancing system tions in 8051 assembly language? Provide a short
reliability. example program that demonstrates their use.
6. Flexibility in Memory Size : Each memory can be sized Ans.In 8051 assembly language, the `PUSH` and `POP` in-
independently, allowing designers to allocate resources structions are used to store data temporarily in the stack
based on specific application needs without being and retrieve it back. The stack is a section of memory
constrained by a unified memory architecture. used for temporary storage, and the stack pointer (SP)
OR keeps track of the top of the stack.
Q9.Explain the key features of the 8051 family of Function:
microcontrollers. PUSH: Stores the contents of a specified register onto
Ans.The 8051 family of microcontrollers, originally devel- the stack. The stack pointer (SP) is first incremented,
oped by Intel in the 1980s, is widely used in embedded and then the data is stored in the memory location
systems. Here are the key features : pointed to by the SP.
1. Architecture : The 8051 uses a modified Harvard POP: Retrieves data from the stack and loads it into a
architecture, allowing simultaneous access to program specified register. The data is first retrieved from the
and data memory. location pointed to by the SP, and then the SP is
2. Memory : decremented.
 On-chip RAM : Typically includes 128 bytes of Example:
internal RAM. Here is a short example program that demonstrates the
 On-chip ROM : Standard version has 4 KB of ROM use of `PUSH` and `POP` instructions in 8051 assem-
(program memory). bly:
 External Memory Support : Can access external ROM ORG 0000H ; Starting address
and RAM. MOV SP, #30H ; Initialize the stack pointer to 30H
3. Bit and Byte Operations : Supports both 8-bit and MOV A, #55H ; Load the value 55H into accumu-
bit-level operations, making it versatile for various lator A
applications. PUSH ACC ; Push the contents of A (55H) onto
4. I/O Ports : Contains four parallel I/O ports (P0, P1, the stack
P2, P3), each 8 bits wide, allowing connection to MOV B, #AAH ; Load the value AAH into register
external devices. B
5. Timers/Counters : Usually includes two 16-bit tim- PUSH B ; Push the contents of B (AAH) onto
ers/counters for various timing applications. the stack
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POP ACC ; Pop the value from the stack into 3. I/O Ports :
accumulator A (AAH will be loaded)  The 8051 has four parallel I/O ports (P0, P1, P2, P3)
POP B ; Pop the value from the stack into that allow it to interface with external devices and
register B (55H will be loaded) peripherals. Each port can be configured for input or
HERE: SJMP HERE ; Infinite loop output operations.
END 4. Timers/Counters :
Explanation:  The microcontroller includes two 16-bit timers/counters
(i) MOV SP, #30H: Sets the stack pointer to memory that can be used for timing operations, event counting,
address 30H. This is where the stack starts. and generating time delays. They are also useful for
(ii) MOV A, #55H: Moves the value 55H into the accu- generating baud rates for serial communication.
mulator (A register). 5. Interrupt System :
(iii)PUSH ACC: Stores the value of the accumulator  The 8051 has a built-in interrupt system that allows the
(55H) onto the stack. The stack pointer is microcontroller to respond to external events. It
incremented, and 55H is stored in memory location supports multiple interrupt sources with varying
31H. priorities, enabling efficient handling of events without
(iv) MOV B, #AAH: Moves the value AAH into register polling.
B. 6. Serial Communication Control :
(v) PUSH B: Stores the value of register B (AAH) onto  The 8051 features a full-duplex UART (Universal Asyn-
the stack. The stack pointer is incremented again, chronous Receiver/Transmitter) for serial communica-
and AAH is stored in memory location 32H. tion. This enables data exchange with other devices or
(vi) POP ACC: Pops the value from the stack (AAH) into microcontrollers.
the accumulator. The stack pointer is decremented, 7. Oscillator and Clock Circuit :
and the value at 32H is loaded into A. An external oscillator provides the clock signal that syn-
(vii)POP B: Pops the value from the stack (55H) into chronizes the operation of the microcontroller. The
register B. The stack pointer is decremented, and speed of the microcontroller is determined by the fre-
the value at 31H is loaded into B. quency of this clock signal.
This demonstrates how `PUSH` and `POP` work to 8. Control Logic :
save and restore register values using the stack. The control logic manages the overall operation of the
microcontroller, coordinating between the CPU,
Q11.What are the main components of the 8051 memory, I/O ports, and other components to ensure they
microcontroller? Describe the function of each work together effectively.
component. Each of these components plays a crucial role in the
Ans.The 8051 microcontroller is a widely used functionality of the 8051 microcontroller, making it a
microcontroller in embedded systems, featuring several versatile choice for various applications in embedded
key components. Here are the main components and systems.
their functions : OR
1. CPU (Central Processing Unit) : Q11.How does the READY signal synchronize the 8085
 The CPU is the brain of the microcontroller, respon- microprocessor with slower peripherals?
sible for executing instructions, performing arithmetic Ans.The READY signal in the 8085 microprocessor is used
and logical operations, and controlling other compo- to synchronize the microprocessor with slower
nents. It manages data flow and processing within the peripherals or memory devices. Here's how it works:
system. Purpose:The 8085 operates faster than many peripher-
2. Memory : als or memory devices. If a peripheral or memory
 RAM (Random Access Memory) : Used for tempo- device is too slow to respond to the microprocessor’s
rary data storage, including variables, stack, and inter- read or write operation, the READY signal allows the
mediate results during program execution. microprocessor to wait until the peripheral is ready to
 ROM (Read-Only Memory) : Stores the program code communicate.
permanently. In the case of the 8051, it typically Working Mechanism:
contains the firmware or application code. (i) READY Signal High (1) :
 EPROM/Flash Memory : Some versions of the 8051  When the READY signal is high (logic 1), it indicates
can use external memory for storing code and data, al- to the 8085 microprocessor that the peripheral or
lowing for easier updates. memory device is ready to complete the current data
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transfer (read or write operation). Follow Venus Publication Question
 The microprocessor proceeds with the operation with- bank For 100% result
out any delay.
(ii) READY Signal Low (0) :
 When the READY signal is low (logic 0), it indicates
that the peripheral or memory device is not yet ready
for the data transfer.
 The 8085 enters a wait state and halts its operation on
the data bus.
 The microprocessor will continue to check the status of
the READY signal in each cycle.
(iii)Synchronization via Wait States :
 The microprocessor keeps entering wait states as long
as the READY signal is low.
 Once the peripheral or memory device is ready and the
READY signal goes high, the microprocessor exits the
wait state and completes the data transfer.

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