CCS 1202

COMPUTER ORGANIZATION AND ARCHITECTURE

GENERAL MICROPROCESSOR
ORGANIZATION
 What is a Microprocessor?
• A microprocessor is the central processing unit (CPU) of a computer, typically an
integrated circuit (IC), responsible for performing arithmetic, logic, control, and
input/output operations.

• Microprocessor Functionality:
• Fetches instructions from memory
• Decodes instructions to determine required actions
• Executes instructions to modify data and produce outputs

• Basic Components:
• Arithmetic Logic Unit (ALU)
• Control Unit (CU)
• Registers
• Buses
 What is a Bus?
• A communication pathway connecting two or more devices
• A set of physical connections (wires, traces) that transfer data and control
signals between components.

• Usually broadcast
• Everyone listens, must share the medium
• Master – can read/write exclusively, only one master
• Slave – everyone else. Can monitor data but not produce
• Bus Width: The number of bits that can be transferred at once, which
affects data transfer rates and overall system performance.

• Often grouped
• A number of channels in one bus
• e.g. 32 bit data bus is 32 separate single bit channels
Functions of Computer Bus
• Data sharing– buses are designed to transfer data between the computer
and the peripherals connected to it. The data is transferred in parallel,
which allows the exchange of 1, 2, 4 or even 8 bytes of data at a time.
Buses are classified on how many bits they can move at the same time,
which means that we have 8-bit, 16-bit 32-bit or even 64-bit buses.
• Addressing– A bus has address lines, which match those of the processor.
This allows data to be sent to or from specific memory locations.
• Power– A bus supplies power to various peripherals that are connected to
it. This is unlike a disk drive that needs to be connected to the power
supply unit.
• Timing– The bus provides a system clock signal to synchronize the
peripherals attached to it with the rest of the system.
Structure and Topologies of Computer buses
Lines are grouped as mentioned below:
• Power line provides electrical power to the components connected

• Data lines carrying data or instructions between modules of the

system

• Address lines indicate the recipient of the bus data

• Control lines control the synchronization and operation of the bus

and the modules linked to the bus
 Types of computer buses
• Computers normally have two bus types:-

• System bus – This is the bus that connects the CPU to the
motherboard’s main memory. The system bus is also known as a front-
side bus, a memory bus, a local bus, or a host bus.

• A number of I / O (input/output) Buses, connecting various peripheral

devices to the CPU. These devices connect to the system bus through
a ‘bridge’ implemented on the chipset of the processors. Other I / O
bus names include “expansion bus,” “external bus” or “host bus”
Types of Computer Buses
• Data Bus: The data bus allows data to travel back and forth between
the microprocessor (CPU) and memory (RAM).

• Address Bus: The address bus carries information about the location of
data in memory. Identify the source or destination of data.

• Control Bus : The control bus carries the control signals that make sure
everything is flowing smoothly from place to place.

• Expansion Bus: If your computer has expansion slots, there’s an expansion

bus. Messages and information pass between your computer and the add-
in boards you plug in over the expansion bus.
System bus
 Control Bus
• Control and timing information
• Determines what modules can use the data and address lines
• If a module wants to send data, it must (1) obtain permission to use the bus, and
(2) transfer data – which might be a request for another module to send data
• Typical control lines
• Memory read
• Memory write
• I/O read
• I/O write
• Interrupt request
• Interrupt ACK
• Bus Request
• Bus Grant
• Clock signals
Expansion Bus Types
• ISA - Industry Standard Architecture
• EISA - Extended Industry Standard Architecture
• MCA - Micro Channel Architecture
• VESA - Video Electronics Standards Association
• PCI - Peripheral Component Interconnect
• PCI Express (PCI-X)
• PCMCIA - Personal Computer Memory Card Industry Association (Also
called PC bus)
• AGP - Accelerated Graphics Port
• SCSI - Small Computer Systems Interface
Peripheral Component Interconnection (PCI) Bus
• An expansion bus standard developed by Intel that became
widespread around 1994.

• It was used to add expansion cards such as extra serial or USB ports,
network interfaces, sound cards, modems, disk controllers, or video
cards.

• 32 or 64 bit

• 50 lines
 Bus Types
• Dedicated
• Separate data & address lines
• Multiplexed
• Shared lines
• Consider shared address, data lines
• Need separate Address valid or Data valid control line
• Time division multiplexing in this case
• Advantage - fewer lines
• Disadvantages
• More complex control
• Ultimate performance
 Single Bus Architecture
Single Bus System:
• Only one bus is used to connect the CPU components, memory, and
I/O devices.
• More cost-effective but less efficient compared to multiple bus
systems.

Advantages:
• Simple design and fewer interconnections.
• Lower hardware complexity.
• Reduces the cost of the processor.
 Single Bus Problems
• Lots of devices on one bus leads to:
• Propagation delays
• Long data paths mean that co-ordination of bus use can adversely affect
performance – bus skew, data arrives at slightly different times
• Device speed
• Slower data transfer speeds due to shared resources.
• Slowest device may determine bus speed!
• Consider a high-speed network module and a slow serial port on the
same bus; must run at slow serial port speed so it can process data
directed for it
• Power problems
• Most systems use multiple buses to overcome these problems
Bus Arbitration: Centralized
• Single hardware device is responsible for allocating bus access
• Bus Controller
• Arbiter
• Centralized
• If a device wants the bus, assert bus request
• Arbiter decides whether or not to send bus grant
• Bus grant travels through daisy-chain of devices
• If device wants the bus, it uses it and does not propagate bus grant down the line. Otherwise
it propagates the bus grant.
• Electrically close devices to arbiter get first priority
• Centralized with Multiple Priority Levels
• Can add multiple priority levels, grants, for more flexible system. Arbiter can issue bus grant
on only highest priority line
Bus Arbitration: Decentralized
• Decentralized
• To acquire bus, see if bus is idle and bus grant is on
• If bus grant is off, may not become master, propagate negative bus grant
• If bus grant is on, propagate negative bus grant
• When dust settles, only one device has bus grant
• Asserts busy on and begins transfer
• Leftmost device that wants the bus gets it
Distributed Arbitration
• No single arbiter
• Each module may claim the bus
• Proper control logic on all modules so they behave to share the bus

• Purpose of both distributed and centralized is to designate the master

• The recipient of a data transfer is the slave

• Many types of arbitration algorithms: round-robin, priority, etc.

Daisy Chaining
of devices
What if a device breaks?
Devices to left higher priority
Bus Gating
What is Bus Gating?
• A mechanism that controls when a bus is allowed to transfer data,
preventing conflicts.
Bus Gating and Control Signals:
• A gate (or switch) is placed on the bus to allow or block data transfer
based on control signals.
• Control signals such as read/write and enable signals decide when
data flows to or from a particular register or memory.
Purpose:
• To avoid data conflicts or bus contention.
• To ensure that data is only transferred when appropriate.
Control Sequences
Definition: A series of control signals sent to various components to coordinate the
execution of instructions.
Role of Control Unit (CU):
The control unit generates these sequences based on the current instruction to
manage data flow, register access, memory access, etc.
Control Signals:
• Read/Write control for memory
• Register select signals
• ALU operation control
Instruction Execution:
• Fetch Phase: Instruction is fetched from memory using control signals.
• Decode Phase: The control unit decodes the instruction and generates appropriate
signals.
• Execute Phase: The ALU performs the required operation, and results are stored back
in registers or memory.
 Control Sequence Example
• Example: Load Instruction (LD A, (mem)):
• Step 1: Fetch instruction from memory (memory address is placed on the address
bus, the instruction is transferred over the data bus).
• Step 2: Decode the instruction (control unit identifies the operation and prepares
to transfer data).
• Step 3: ALU or other components execute the operation (data from memory is
transferred to register A).
• Step 4: Store result in the destination register (register A is updated).

• Control Sequence Breakdown:

• Memory Address (address bus)
• Read/Write (control bus)
• Data Transfer (data bus)
• Register Selection (register control)
Timing Diagrams
• Co-ordination of events on bus
• Synchronous
• Events determined by clock signals
• Control Bus includes clock line
• A single 1-0 is a bus cycle
• All devices can read clock line
• Usually sync on leading edge
• Usually a single cycle for an event

• Purpose of Timing Diagrams: To represent the sequence of control signals

over time and ensure that data is correctly fetched, processed, and written
back.
100 million cycles per second
1 cycle in (1/100,000,000) seconds = 0.0000001s = 10 ns

In reality, the clock is a bit more sawtoothed

Synchronous Timing Diagram: Read Operation Timing

Indicates read/address lines valid, noticed by memory

Indicates we want to read, not write

Address from memory we want

delay
Data from memory

Indicates data lines valid

Synchronous - Disadvantages
• Although synchronous clocks are simple, there are some
disadvantages
• Everything done in multiples of clock, so something finishing in 3.1 cycles
takes 4 cycles
• With a mixture of fast and slow devices, we have to wait for the slowest
device
• Faster devices can’t run at their capacity, all devices are tied to a fixed clock
rate
• Consider memory device speed faster than 10ns, no speedup increase for
100Mhz clock
• One solution: Use asynchronous bus
 Asynchronous Bus
• No clock
• Occurrence of one event on the bus follows and depends on a
previous event
• Requires tracking of state, hard to debug, but potential for higher
performance

• Also used with networking

• Problem with “drift” and loss of synchronization
• Some use self-clocking codes, e.g. Ethernet
Asynchronous Timing Diagram
Asserted once read/address lines stabilize
Deasserted when finished reading
Master sync
Slave = memory, ACK’s master sync
Master reads the data from the data bus
Slave sync

Slave places requested data on bus

Optimization in Single Bus Architecture
• Challenges:
• Contention for the bus.
• Latency due to bus sharing.

• Solutions:
• Use of faster clock speeds.
• Optimizing control signal sequences to avoid delays.
• Employing techniques like bus arbitration (when multiple components request
the bus at the same time).
 Registers
• Registers are high-speed storage areas within the CPU that temporarily
hold data, instructions, or addresses during processing.
• Both instructions or data can be stored in registers for processing by
the ALU.
• All processors have a certain number of registers, the exact number
varies between different CPUs
• Functions of Registers:
• Fast access to data
• Temporary storage during processing
• Facilitate quick context switching in multitasking systems
Types of registers
• Instruction Register (IR)
• It holds the instruction that is currently being executed.
• Its output is available to the control unit which generated the timing
signals that control the various processing elements involved in
executing the instruction

• General Purpose Register

• General purpose registers are used to store temporary data within the
microprocessor. It is a multipurpose register. They can be used either by
programmer or by a user.
Types of registers
• Program Counter (PC)
• It holds the address of the instruction to be fetched and executed.
• During the execution of an instruction, its contents are updated to point
to the next instruction to be executed.

• Stack Pointer (SP)

• It contains the address of a section of memory known as stack which
may be used for temporary storage of data or addresses.
 Types of registers
• Memory Address Register (MAR)
• It holds the address in memory to or from which data are to be
transferred.

• Memory Data Register (MDR)

• It contains the data to be written into or read out of the addressed
memory location.
• It is also known as memory buffer register (MBR).
Types of registers
• Status Register (SR) / Conditional Code Register (CCR) / Status Flags
• A register with individual bits (flags) to indicate condition of the
processor as a result of an arithmetic/logical operations.
• Common status flags:
• Carry (C)
• Positive result (P)
• Zero result (Z)
• Negative result (N)
• arithmetic oVerflow (V)
The advantages of using registers:
• Reducing instruction (program) length
• Memory address usually requires many bits, referencing registers
requires only a few bits.
• Cutting down execution time
• Using register in complex expressions and storing results instead of
writing back to memory, the number of CPU clock cycle (time) can be
reduced
• Ease of programming
• In processing a block of data consecutively in memory, one can store
starting address of block in register.
• To retrieve data item, one can simply increment the address in register,
corresponding to consecutive data in data block. Thus, fewer number of
instructions are needed
Summary and Recap
• Microprocessors consist of components like ALU, CU, registers, and
buses working in harmony.

• Single Bus Architecture uses a single bus for data transfer but may face
limitations in speed and efficiency.

• Registers and buses are essential for temporary data storage and
communication between CPU components.

• Control sequences, timing diagrams, and bus gating help coordinate the
execution of instructions and prevent conflicts.