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LAB 03

The document outlines two experiments in a Digital Logic Design Laboratory course focused on implementing a 3-8 line decoder using both 2-input AND gates and 2-4 line decoders. It details the necessary equipment, theoretical background, and circuit diagrams for both methods of implementation. The conclusion highlights the learning outcomes related to constructing decoders and using them to implement combinational functions.

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21 views

LAB 03

The document outlines two experiments in a Digital Logic Design Laboratory course focused on implementing a 3-8 line decoder using both 2-input AND gates and 2-4 line decoders. It details the necessary equipment, theoretical background, and circuit diagrams for both methods of implementation. The conclusion highlights the learning outcomes related to constructing decoders and using them to implement combinational functions.

Uploaded by

azr.yt.pri
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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United International University

QUEST FOR EXCELLENCE


Course Title: Digital logic Design Laboratory
Course Code: CSE 1326
Experiment No: 1 & 2
Experiment Name: Implementing 3-8 line decoder
Submitted by ASIF RAHMAN
ID: 0112310389
Group No: 5
Date of Performance: 16/10/23
Date of Submission: 25/10/23
Experiment 1:
Implementing 3-8 line decoder using
1. 2 input AND Gates
2. 2 – 4 line decoders
Equipment needed:
1. AND gate 7408
2. NOT gate 7404
3. 2-4 line decoder 74139
4. Logisim Software
5. Wiring
6. Trainer board

1.1
Theory:
A decoder is a combinational logic circuit that is used to change the code into a
set of signals. It is the reverse process of an encoder. A decoder circuit takes
multiple inputs and gives multiple outputs. A decoder circuit takes binary data of
‘n’ inputs into ‘2^n’ unique output. In addition to input pins, the decoder has a
enable pin. This enables the pin when negated, to make the circuit inactive.
Figure 1: Pinout of 3-8 bit decoder with 2 2-4 bit decoders

We can easily make a 3-8 line decoder using only 2 input AND gates and NOT gates. The circuit
diagram is shown below.
E I1 I0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Figure 2: 3-8 line decoders using 2 input AND gates Table 1: 3-8 line decoder

1.2
3-8 line decoder using 2-4 line decoders
We can also make a 3-8 line decoder by joining 2 2-4 bit decoders. The circuit diagram is shown
below.

Figure 3: 3-8 line decoder using 2 2-4 line decoders


We can implement this circuit on the trainer board.

Experiment 2:
Implement combinational circuits (functions) using decoder
and basic gates
F = M1 . M3 . M6 . M7
We can implement this functions if we consider each Max terms as the negated outputs of the
3-8 bit decoder. Such as M1=Output1’, M3=Output3’, M6=Output6’, M7=Output7’. Then we
can use AND gates and NOT gates to show the final output. The circuit diagram is shown below.

Figure 4: MAX terms Function

Now we’re going to implement the function F = m0 + m4 + m5 + m7 using the


decoder.
If we consider the outputs as minterms. Such as m0=Output0, m4=Output4,
m5=Output5, m7=Output7. We can easily implement the function only using OR
gates. The circuit diagram is shown below.
Figure 5: F = m0 + m4 + m5 + m7 with decoder

Figure 6: F = m0 + m4 + m5 + m7with decoder


Conclusion:
I learned how to make decoders from AND gates and NOT gates, I also learned how to make 3-8
bit decoder from 2 2-4 bit decoders. Moreover, I learned how to implement minterms and
maxterms functions using decoders.

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